Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k20dx/gpio.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file gpio.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "MK20D5.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "DAP_config.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 static void busy_wait(uint32_t cycles)
Pawel Zarembski 0:01f31e923fe2 28 {
Pawel Zarembski 0:01f31e923fe2 29 volatile uint32_t i;
Pawel Zarembski 0:01f31e923fe2 30 i = cycles;
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 while (i > 0) {
Pawel Zarembski 0:01f31e923fe2 33 i--;
Pawel Zarembski 0:01f31e923fe2 34 }
Pawel Zarembski 0:01f31e923fe2 35 }
Pawel Zarembski 0:01f31e923fe2 36
Pawel Zarembski 0:01f31e923fe2 37 void gpio_init(void)
Pawel Zarembski 0:01f31e923fe2 38 {
Pawel Zarembski 0:01f31e923fe2 39 // Enable hardfault on unaligned access for the interface only.
Pawel Zarembski 0:01f31e923fe2 40 // If this is done in the bootloader than then it might (will) break
Pawel Zarembski 0:01f31e923fe2 41 // older application firmware or firmware from 3rd party vendors.
Pawel Zarembski 0:01f31e923fe2 42 #if defined(DAPLINK_IF)
Pawel Zarembski 0:01f31e923fe2 43 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
Pawel Zarembski 0:01f31e923fe2 44 #endif
Pawel Zarembski 0:01f31e923fe2 45 // enable clock to ports
Pawel Zarembski 0:01f31e923fe2 46 SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK;
Pawel Zarembski 0:01f31e923fe2 47 // configure pin as GPIO
Pawel Zarembski 0:01f31e923fe2 48 LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 49 // led off - enable output
Pawel Zarembski 0:01f31e923fe2 50 LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 51 LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 52 // led on
Pawel Zarembski 0:01f31e923fe2 53 LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 54 // reset button configured as gpio input
Pawel Zarembski 0:01f31e923fe2 55 PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 56 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 // configure pin as GPIO
Pawel Zarembski 0:01f31e923fe2 59 PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 60 // set output to 0
Pawel Zarembski 0:01f31e923fe2 61 PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 62 // switch gpio to output
Pawel Zarembski 0:01f31e923fe2 63 PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 64
Pawel Zarembski 0:01f31e923fe2 65 // Let the voltage rails stabilize. This is especailly important
Pawel Zarembski 0:01f31e923fe2 66 // during software resets, since the target's 3.3v rail can take
Pawel Zarembski 0:01f31e923fe2 67 // 20-50ms to drain. During this time the target could be driving
Pawel Zarembski 0:01f31e923fe2 68 // the reset pin low, causing the bootloader to think the reset
Pawel Zarembski 0:01f31e923fe2 69 // button is pressed.
Pawel Zarembski 0:01f31e923fe2 70 // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
Pawel Zarembski 0:01f31e923fe2 71 busy_wait(1000000);
Pawel Zarembski 0:01f31e923fe2 72 }
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 void gpio_set_board_power(bool powerEnabled)
Pawel Zarembski 0:01f31e923fe2 75 {
Pawel Zarembski 0:01f31e923fe2 76 if (powerEnabled) {
Pawel Zarembski 0:01f31e923fe2 77 // enable power switch
Pawel Zarembski 0:01f31e923fe2 78 PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 79 }
Pawel Zarembski 0:01f31e923fe2 80 else {
Pawel Zarembski 0:01f31e923fe2 81 // disable power switch
Pawel Zarembski 0:01f31e923fe2 82 PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 83 }
Pawel Zarembski 0:01f31e923fe2 84 }
Pawel Zarembski 0:01f31e923fe2 85
Pawel Zarembski 0:01f31e923fe2 86 void gpio_set_hid_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 87 {
Pawel Zarembski 0:01f31e923fe2 88 if (state) {
Pawel Zarembski 0:01f31e923fe2 89 LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT; // LED on
Pawel Zarembski 0:01f31e923fe2 90 } else {
Pawel Zarembski 0:01f31e923fe2 91 LED_CONNECTED_GPIO->PSOR = 1UL << LED_CONNECTED_BIT; // LED off
Pawel Zarembski 0:01f31e923fe2 92 }
Pawel Zarembski 0:01f31e923fe2 93 }
Pawel Zarembski 0:01f31e923fe2 94
Pawel Zarembski 0:01f31e923fe2 95 void gpio_set_cdc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 96 {
Pawel Zarembski 0:01f31e923fe2 97 gpio_set_hid_led(state);
Pawel Zarembski 0:01f31e923fe2 98 }
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 void gpio_set_msc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 101 {
Pawel Zarembski 0:01f31e923fe2 102 gpio_set_hid_led(state);
Pawel Zarembski 0:01f31e923fe2 103 }
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 uint8_t gpio_get_reset_btn_no_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 106 {
Pawel Zarembski 0:01f31e923fe2 107 return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 }
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 uint8_t gpio_get_reset_btn_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 112 {
Pawel Zarembski 0:01f31e923fe2 113 return 0;
Pawel Zarembski 0:01f31e923fe2 114 }