DAPLink Reset - Repostiory containing DAPLink source code with Re…

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Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:: Pawel Zarembski
Date:: Tue Apr 07 12:55:42 2020 +0200
Revision:: 0:01f31e923fe2

hani: DAPLink with reset workaround

Who changed what in which revision?

User	Revision	Line number	New contents of line
Pawel Zarembski	0:01f31e923fe2	1	/*
Pawel Zarembski	0:01f31e923fe2	2	** ###################################################################
Pawel Zarembski	0:01f31e923fe2	3	** Compilers: Keil ARM C/C++ Compiler
Pawel Zarembski	0:01f31e923fe2	4	** Freescale C/C++ for Embedded ARM
Pawel Zarembski	0:01f31e923fe2	5	** GNU C Compiler
Pawel Zarembski	0:01f31e923fe2	6	** IAR ANSI C/C++ Compiler for ARM
Pawel Zarembski	0:01f31e923fe2	7	**
Pawel Zarembski	0:01f31e923fe2	8	** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
Pawel Zarembski	0:01f31e923fe2	9	** K20P32M50SF0RM Rev. 1, Oct 2011
Pawel Zarembski	0:01f31e923fe2	10	** K20P48M50SF0RM Rev. 1, Oct 2011
Pawel Zarembski	0:01f31e923fe2	11	**
Pawel Zarembski	0:01f31e923fe2	12	** Version: rev. 3.4, 2013-10-29
Pawel Zarembski	0:01f31e923fe2	13	** Build: b151120
Pawel Zarembski	0:01f31e923fe2	14	**
Pawel Zarembski	0:01f31e923fe2	15	** Abstract:
Pawel Zarembski	0:01f31e923fe2	16	** CMSIS Peripheral Access Layer for MK20D5
Pawel Zarembski	0:01f31e923fe2	17	**
Pawel Zarembski	0:01f31e923fe2	18	** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
Pawel Zarembski	0:01f31e923fe2	19	** All rights reserved.
Pawel Zarembski	0:01f31e923fe2	20	**
Pawel Zarembski	0:01f31e923fe2	21	** Redistribution and use in source and binary forms, with or without modification,
Pawel Zarembski	0:01f31e923fe2	22	** are permitted provided that the following conditions are met:
Pawel Zarembski	0:01f31e923fe2	23	**
Pawel Zarembski	0:01f31e923fe2	24	** o Redistributions of source code must retain the above copyright notice, this list
Pawel Zarembski	0:01f31e923fe2	25	** of conditions and the following disclaimer.
Pawel Zarembski	0:01f31e923fe2	26	**
Pawel Zarembski	0:01f31e923fe2	27	** o Redistributions in binary form must reproduce the above copyright notice, this
Pawel Zarembski	0:01f31e923fe2	28	** list of conditions and the following disclaimer in the documentation and/or
Pawel Zarembski	0:01f31e923fe2	29	** other materials provided with the distribution.
Pawel Zarembski	0:01f31e923fe2	30	**
Pawel Zarembski	0:01f31e923fe2	31	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Pawel Zarembski	0:01f31e923fe2	32	** contributors may be used to endorse or promote products derived from this
Pawel Zarembski	0:01f31e923fe2	33	** software without specific prior written permission.
Pawel Zarembski	0:01f31e923fe2	34	**
Pawel Zarembski	0:01f31e923fe2	35	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Pawel Zarembski	0:01f31e923fe2	36	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Pawel Zarembski	0:01f31e923fe2	37	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Pawel Zarembski	0:01f31e923fe2	38	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Pawel Zarembski	0:01f31e923fe2	39	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Pawel Zarembski	0:01f31e923fe2	40	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Pawel Zarembski	0:01f31e923fe2	41	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Pawel Zarembski	0:01f31e923fe2	42	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Pawel Zarembski	0:01f31e923fe2	43	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Pawel Zarembski	0:01f31e923fe2	44	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Pawel Zarembski	0:01f31e923fe2	45	**
Pawel Zarembski	0:01f31e923fe2	46	** http: www.freescale.com
Pawel Zarembski	0:01f31e923fe2	47	** mail: support@freescale.com
Pawel Zarembski	0:01f31e923fe2	48	**
Pawel Zarembski	0:01f31e923fe2	49	** Revisions:
Pawel Zarembski	0:01f31e923fe2	50	** - rev. 2.0 (2011-11-07)
Pawel Zarembski	0:01f31e923fe2	51	** Initial public version.
Pawel Zarembski	0:01f31e923fe2	52	** - rev. 2.1 (2011-12-13)
Pawel Zarembski	0:01f31e923fe2	53	** Removed registers for AIPS and AXBS modules.
Pawel Zarembski	0:01f31e923fe2	54	** - rev. 3.0 (2012-03-19)
Pawel Zarembski	0:01f31e923fe2	55	** PDB Peripheral register structure updated.
Pawel Zarembski	0:01f31e923fe2	56	** DMA Registers and bits for unsupported DMA channels removed.
Pawel Zarembski	0:01f31e923fe2	57	** - rev. 3.1 (2012-04-13)
Pawel Zarembski	0:01f31e923fe2	58	** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
Pawel Zarembski	0:01f31e923fe2	59	** Added new #define symbols <peripheralType>_BASE_PTRS.
Pawel Zarembski	0:01f31e923fe2	60	** - rev. 3.2 (2013-04-05)
Pawel Zarembski	0:01f31e923fe2	61	** Changed start of doxygen comment.
Pawel Zarembski	0:01f31e923fe2	62	** - rev. 3.3 (2013-06-24)
Pawel Zarembski	0:01f31e923fe2	63	** NV_FOPT register - NMI_DIS bit added.
Pawel Zarembski	0:01f31e923fe2	64	** - rev. 3.4 (2013-10-29)
Pawel Zarembski	0:01f31e923fe2	65	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Pawel Zarembski	0:01f31e923fe2	66	**
Pawel Zarembski	0:01f31e923fe2	67	** ###################################################################
Pawel Zarembski	0:01f31e923fe2	68	*/
Pawel Zarembski	0:01f31e923fe2	69
Pawel Zarembski	0:01f31e923fe2	70	/*!
Pawel Zarembski	0:01f31e923fe2	71	* @file MK20D5.h
Pawel Zarembski	0:01f31e923fe2	72	* @version 3.4
Pawel Zarembski	0:01f31e923fe2	73	* @date 2013-10-29
Pawel Zarembski	0:01f31e923fe2	74	* @brief CMSIS Peripheral Access Layer for MK20D5
Pawel Zarembski	0:01f31e923fe2	75	*
Pawel Zarembski	0:01f31e923fe2	76	* CMSIS Peripheral Access Layer for MK20D5
Pawel Zarembski	0:01f31e923fe2	77	*/
Pawel Zarembski	0:01f31e923fe2	78
Pawel Zarembski	0:01f31e923fe2	79	#ifndef _MK20D5_H_
Pawel Zarembski	0:01f31e923fe2	80	#define _MK20D5_H_ /*< Symbol preventing repeated inclusion /
Pawel Zarembski	0:01f31e923fe2	81
Pawel Zarembski	0:01f31e923fe2	82	/** Memory map major version (memory maps with equal major version number are
Pawel Zarembski	0:01f31e923fe2	83	* compatible) */
Pawel Zarembski	0:01f31e923fe2	84	#define MCU_MEM_MAP_VERSION 0x0300U
Pawel Zarembski	0:01f31e923fe2	85	/** Memory map minor version */
Pawel Zarembski	0:01f31e923fe2	86	#define MCU_MEM_MAP_VERSION_MINOR 0x0004U
Pawel Zarembski	0:01f31e923fe2	87
Pawel Zarembski	0:01f31e923fe2	88	/**
Pawel Zarembski	0:01f31e923fe2	89	* @brief Macro to calculate address of an aliased word in the peripheral
Pawel Zarembski	0:01f31e923fe2	90	* bitband area for a peripheral register and bit (bit band region 0x40000000 to
Pawel Zarembski	0:01f31e923fe2	91	* 0x400FFFFF).
Pawel Zarembski	0:01f31e923fe2	92	* @param Reg Register to access.
Pawel Zarembski	0:01f31e923fe2	93	* @param Bit Bit number to access.
Pawel Zarembski	0:01f31e923fe2	94	* @return Address of the aliased word in the peripheral bitband area.
Pawel Zarembski	0:01f31e923fe2	95	*/
Pawel Zarembski	0:01f31e923fe2	96	#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u((uint32_t)(Bit))))
Pawel Zarembski	0:01f31e923fe2	97	/**
Pawel Zarembski	0:01f31e923fe2	98	* @brief Macro to access a single bit of a peripheral register (bit band region
Pawel Zarembski	0:01f31e923fe2	99	* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Pawel Zarembski	0:01f31e923fe2	100	* be used for peripherals with 32bit access allowed.
Pawel Zarembski	0:01f31e923fe2	101	* @param Reg Register to access.
Pawel Zarembski	0:01f31e923fe2	102	* @param Bit Bit number to access.
Pawel Zarembski	0:01f31e923fe2	103	* @return Value of the targeted bit in the bit band region.
Pawel Zarembski	0:01f31e923fe2	104	*/
Pawel Zarembski	0:01f31e923fe2	105	#define BITBAND_REG32(Reg,Bit) (((uint32_t volatile)(BITBAND_REGADDR((Reg),(Bit)))))
Pawel Zarembski	0:01f31e923fe2	106	#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
Pawel Zarembski	0:01f31e923fe2	107	/**
Pawel Zarembski	0:01f31e923fe2	108	* @brief Macro to access a single bit of a peripheral register (bit band region
Pawel Zarembski	0:01f31e923fe2	109	* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Pawel Zarembski	0:01f31e923fe2	110	* be used for peripherals with 16bit access allowed.
Pawel Zarembski	0:01f31e923fe2	111	* @param Reg Register to access.
Pawel Zarembski	0:01f31e923fe2	112	* @param Bit Bit number to access.
Pawel Zarembski	0:01f31e923fe2	113	* @return Value of the targeted bit in the bit band region.
Pawel Zarembski	0:01f31e923fe2	114	*/
Pawel Zarembski	0:01f31e923fe2	115	#define BITBAND_REG16(Reg,Bit) (((uint16_t volatile)(BITBAND_REGADDR((Reg),(Bit)))))
Pawel Zarembski	0:01f31e923fe2	116	/**
Pawel Zarembski	0:01f31e923fe2	117	* @brief Macro to access a single bit of a peripheral register (bit band region
Pawel Zarembski	0:01f31e923fe2	118	* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Pawel Zarembski	0:01f31e923fe2	119	* be used for peripherals with 8bit access allowed.
Pawel Zarembski	0:01f31e923fe2	120	* @param Reg Register to access.
Pawel Zarembski	0:01f31e923fe2	121	* @param Bit Bit number to access.
Pawel Zarembski	0:01f31e923fe2	122	* @return Value of the targeted bit in the bit band region.
Pawel Zarembski	0:01f31e923fe2	123	*/
Pawel Zarembski	0:01f31e923fe2	124	#define BITBAND_REG8(Reg,Bit) (((uint8_t volatile)(BITBAND_REGADDR((Reg),(Bit)))))
Pawel Zarembski	0:01f31e923fe2	125
Pawel Zarembski	0:01f31e923fe2	126	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	127	-- Interrupt vector numbers
Pawel Zarembski	0:01f31e923fe2	128	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	129
Pawel Zarembski	0:01f31e923fe2	130	/*!
Pawel Zarembski	0:01f31e923fe2	131	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Pawel Zarembski	0:01f31e923fe2	132	* @{
Pawel Zarembski	0:01f31e923fe2	133	*/
Pawel Zarembski	0:01f31e923fe2	134
Pawel Zarembski	0:01f31e923fe2	135	/** Interrupt Number Definitions */
Pawel Zarembski	0:01f31e923fe2	136	#define NUMBER_OF_INT_VECTORS 62 /*< Number of interrupts in the Vector table /
Pawel Zarembski	0:01f31e923fe2	137
Pawel Zarembski	0:01f31e923fe2	138	typedef enum IRQn {
Pawel Zarembski	0:01f31e923fe2	139	/* Auxiliary constants */
Pawel Zarembski	0:01f31e923fe2	140	NotAvail_IRQn = -128, /*< Not available device specific interrupt /
Pawel Zarembski	0:01f31e923fe2	141
Pawel Zarembski	0:01f31e923fe2	142	/* Core interrupts */
Pawel Zarembski	0:01f31e923fe2	143	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
Pawel Zarembski	0:01f31e923fe2	144	HardFault_IRQn = -13, /*< Cortex-M4 SV Hard Fault Interrupt /
Pawel Zarembski	0:01f31e923fe2	145	MemoryManagement_IRQn = -12, /*< Cortex-M4 Memory Management Interrupt /
Pawel Zarembski	0:01f31e923fe2	146	BusFault_IRQn = -11, /*< Cortex-M4 Bus Fault Interrupt /
Pawel Zarembski	0:01f31e923fe2	147	UsageFault_IRQn = -10, /*< Cortex-M4 Usage Fault Interrupt /
Pawel Zarembski	0:01f31e923fe2	148	SVCall_IRQn = -5, /*< Cortex-M4 SV Call Interrupt /
Pawel Zarembski	0:01f31e923fe2	149	DebugMonitor_IRQn = -4, /*< Cortex-M4 Debug Monitor Interrupt /
Pawel Zarembski	0:01f31e923fe2	150	PendSV_IRQn = -2, /*< Cortex-M4 Pend SV Interrupt /
Pawel Zarembski	0:01f31e923fe2	151	SysTick_IRQn = -1, /*< Cortex-M4 System Tick Interrupt /
Pawel Zarembski	0:01f31e923fe2	152
Pawel Zarembski	0:01f31e923fe2	153	/* Device specific interrupts */
Pawel Zarembski	0:01f31e923fe2	154	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
Pawel Zarembski	0:01f31e923fe2	155	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
Pawel Zarembski	0:01f31e923fe2	156	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
Pawel Zarembski	0:01f31e923fe2	157	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
Pawel Zarembski	0:01f31e923fe2	158	DMA_Error_IRQn = 4, /*< DMA error interrupt /
Pawel Zarembski	0:01f31e923fe2	159	Reserved21_IRQn = 5, /*< Reserved interrupt 21 /
Pawel Zarembski	0:01f31e923fe2	160	FTFL_IRQn = 6, /*< FTFL interrupt /
Pawel Zarembski	0:01f31e923fe2	161	Read_Collision_IRQn = 7, /*< Read collision interrupt /
Pawel Zarembski	0:01f31e923fe2	162	LVD_LVW_IRQn = 8, /*< Low Voltage Detect, Low Voltage Warning /
Pawel Zarembski	0:01f31e923fe2	163	LLW_IRQn = 9, /*< Low Leakage Wakeup /
Pawel Zarembski	0:01f31e923fe2	164	Watchdog_IRQn = 10, /*< WDOG interrupt /
Pawel Zarembski	0:01f31e923fe2	165	I2C0_IRQn = 11, /*< I2C0 interrupt /
Pawel Zarembski	0:01f31e923fe2	166	SPI0_IRQn = 12, /*< SPI0 interrupt /
Pawel Zarembski	0:01f31e923fe2	167	I2S0_Tx_IRQn = 13, /*< I2S0 transmit interrupt /
Pawel Zarembski	0:01f31e923fe2	168	I2S0_Rx_IRQn = 14, /*< I2S0 receive interrupt /
Pawel Zarembski	0:01f31e923fe2	169	UART0_LON_IRQn = 15, /*< UART0 LON interrupt /
Pawel Zarembski	0:01f31e923fe2	170	UART0_RX_TX_IRQn = 16, /*< UART0 receive/transmit interrupt /
Pawel Zarembski	0:01f31e923fe2	171	UART0_ERR_IRQn = 17, /*< UART0 error interrupt /
Pawel Zarembski	0:01f31e923fe2	172	UART1_RX_TX_IRQn = 18, /*< UART1 receive/transmit interrupt /
Pawel Zarembski	0:01f31e923fe2	173	UART1_ERR_IRQn = 19, /*< UART1 error interrupt /
Pawel Zarembski	0:01f31e923fe2	174	UART2_RX_TX_IRQn = 20, /*< UART2 receive/transmit interrupt /
Pawel Zarembski	0:01f31e923fe2	175	UART2_ERR_IRQn = 21, /*< UART2 error interrupt /
Pawel Zarembski	0:01f31e923fe2	176	ADC0_IRQn = 22, /*< ADC0 interrupt /
Pawel Zarembski	0:01f31e923fe2	177	CMP0_IRQn = 23, /*< CMP0 interrupt /
Pawel Zarembski	0:01f31e923fe2	178	CMP1_IRQn = 24, /*< CMP1 interrupt /
Pawel Zarembski	0:01f31e923fe2	179	FTM0_IRQn = 25, /*< FTM0 fault, overflow and channels interrupt /
Pawel Zarembski	0:01f31e923fe2	180	FTM1_IRQn = 26, /*< FTM1 fault, overflow and channels interrupt /
Pawel Zarembski	0:01f31e923fe2	181	CMT_IRQn = 27, /*< CMT interrupt /
Pawel Zarembski	0:01f31e923fe2	182	RTC_IRQn = 28, /*< RTC interrupt /
Pawel Zarembski	0:01f31e923fe2	183	RTC_Seconds_IRQn = 29, /*< RTC seconds interrupt /
Pawel Zarembski	0:01f31e923fe2	184	PIT0_IRQn = 30, /*< PIT timer channel 0 interrupt /
Pawel Zarembski	0:01f31e923fe2	185	PIT1_IRQn = 31, /*< PIT timer channel 1 interrupt /
Pawel Zarembski	0:01f31e923fe2	186	PIT2_IRQn = 32, /*< PIT timer channel 2 interrupt /
Pawel Zarembski	0:01f31e923fe2	187	PIT3_IRQn = 33, /*< PIT timer channel 3 interrupt /
Pawel Zarembski	0:01f31e923fe2	188	PDB0_IRQn = 34, /*< PDB0 interrupt /
Pawel Zarembski	0:01f31e923fe2	189	USB0_IRQn = 35, /*< USB0 interrupt /
Pawel Zarembski	0:01f31e923fe2	190	USBDCD_IRQn = 36, /*< USBDCD interrupt /
Pawel Zarembski	0:01f31e923fe2	191	TSI0_IRQn = 37, /*< TSI0 interrupt /
Pawel Zarembski	0:01f31e923fe2	192	MCG_IRQn = 38, /*< MCG interrupt /
Pawel Zarembski	0:01f31e923fe2	193	LPTimer_IRQn = 39, /*< LPTimer interrupt /
Pawel Zarembski	0:01f31e923fe2	194	PORTA_IRQn = 40, /*< Port A interrupt /
Pawel Zarembski	0:01f31e923fe2	195	PORTB_IRQn = 41, /*< Port B interrupt /
Pawel Zarembski	0:01f31e923fe2	196	PORTC_IRQn = 42, /*< Port C interrupt /
Pawel Zarembski	0:01f31e923fe2	197	PORTD_IRQn = 43, /*< Port D interrupt /
Pawel Zarembski	0:01f31e923fe2	198	PORTE_IRQn = 44, /*< Port E interrupt /
Pawel Zarembski	0:01f31e923fe2	199	SWI_IRQn = 45 /*< Software interrupt /
Pawel Zarembski	0:01f31e923fe2	200	} IRQn_Type;
Pawel Zarembski	0:01f31e923fe2	201
Pawel Zarembski	0:01f31e923fe2	202	/*!
Pawel Zarembski	0:01f31e923fe2	203	* @}
Pawel Zarembski	0:01f31e923fe2	204	/ / end of group Interrupt_vector_numbers */
Pawel Zarembski	0:01f31e923fe2	205
Pawel Zarembski	0:01f31e923fe2	206
Pawel Zarembski	0:01f31e923fe2	207	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	208	-- Cortex M4 Core Configuration
Pawel Zarembski	0:01f31e923fe2	209	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	210
Pawel Zarembski	0:01f31e923fe2	211	/*!
Pawel Zarembski	0:01f31e923fe2	212	* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
Pawel Zarembski	0:01f31e923fe2	213	* @{
Pawel Zarembski	0:01f31e923fe2	214	*/
Pawel Zarembski	0:01f31e923fe2	215
Pawel Zarembski	0:01f31e923fe2	216	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
Pawel Zarembski	0:01f31e923fe2	217	#define __NVIC_PRIO_BITS 4 /*< Number of priority bits implemented in the NVIC /
Pawel Zarembski	0:01f31e923fe2	218	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
Pawel Zarembski	0:01f31e923fe2	219	#define __FPU_PRESENT 0 /*< Defines if an FPU is present or not /
Pawel Zarembski	0:01f31e923fe2	220
Pawel Zarembski	0:01f31e923fe2	221	#include "core_cm4.h" /* Core Peripheral Access Layer */
Pawel Zarembski	0:01f31e923fe2	222	#include "system_MK20D5.h" /* Device specific configuration file */
Pawel Zarembski	0:01f31e923fe2	223
Pawel Zarembski	0:01f31e923fe2	224	/*!
Pawel Zarembski	0:01f31e923fe2	225	* @}
Pawel Zarembski	0:01f31e923fe2	226	/ / end of group Cortex_Core_Configuration */
Pawel Zarembski	0:01f31e923fe2	227
Pawel Zarembski	0:01f31e923fe2	228
Pawel Zarembski	0:01f31e923fe2	229	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	230	-- Mapping Information
Pawel Zarembski	0:01f31e923fe2	231	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	232
Pawel Zarembski	0:01f31e923fe2	233	/*!
Pawel Zarembski	0:01f31e923fe2	234	* @addtogroup Mapping_Information Mapping Information
Pawel Zarembski	0:01f31e923fe2	235	* @{
Pawel Zarembski	0:01f31e923fe2	236	*/
Pawel Zarembski	0:01f31e923fe2	237
Pawel Zarembski	0:01f31e923fe2	238	/** Mapping Information */
Pawel Zarembski	0:01f31e923fe2	239	/*!
Pawel Zarembski	0:01f31e923fe2	240	* @addtogroup edma_request
Pawel Zarembski	0:01f31e923fe2	241	* @{
Pawel Zarembski	0:01f31e923fe2	242	*/
Pawel Zarembski	0:01f31e923fe2	243
Pawel Zarembski	0:01f31e923fe2	244	/*******************************************************************************
Pawel Zarembski	0:01f31e923fe2	245	* Definitions
Pawel Zarembski	0:01f31e923fe2	246	******************************************************************************/
Pawel Zarembski	0:01f31e923fe2	247
Pawel Zarembski	0:01f31e923fe2	248	/*!
Pawel Zarembski	0:01f31e923fe2	249	* @brief Structure for the DMA hardware request
Pawel Zarembski	0:01f31e923fe2	250	*
Pawel Zarembski	0:01f31e923fe2	251	* Defines the structure for the DMA hardware request collections. The user can configure the
Pawel Zarembski	0:01f31e923fe2	252	* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
Pawel Zarembski	0:01f31e923fe2	253	* of the hardware request varies according to the to SoC.
Pawel Zarembski	0:01f31e923fe2	254	*/
Pawel Zarembski	0:01f31e923fe2	255	typedef enum _dma_request_source
Pawel Zarembski	0:01f31e923fe2	256	{
Pawel Zarembski	0:01f31e923fe2	257	#if defined(CPU_MK20DX128VMP5) \|\| defined(CPU_MK20DN128VMP5) \|\| defined(CPU_MK20DX64VMP5) \|\| defined(CPU_MK20DN64VMP5) \|\| \
Pawel Zarembski	0:01f31e923fe2	258	defined(CPU_MK20DX32VMP5) \|\| defined(CPU_MK20DN32VMP5) \|\| defined(CPU_MK20DX128VLH5) \|\| defined(CPU_MK20DN128VLH5) \|\| \
Pawel Zarembski	0:01f31e923fe2	259	defined(CPU_MK20DX64VLH5) \|\| defined(CPU_MK20DN64VLH5) \|\| defined(CPU_MK20DX32VLH5) \|\| defined(CPU_MK20DN32VLH5) \|\| \
Pawel Zarembski	0:01f31e923fe2	260	defined(CPU_MK20DX128VFM5) \|\| defined(CPU_MK20DN128VFM5) \|\| defined(CPU_MK20DX64VFM5) \|\| defined(CPU_MK20DN64VFM5) \|\| \
Pawel Zarembski	0:01f31e923fe2	261	defined(CPU_MK20DX32VFM5) \|\| defined(CPU_MK20DN32VFM5) \|\| defined(CPU_MK20DX128VFT5) \|\| defined(CPU_MK20DN128VFT5) \|\| \
Pawel Zarembski	0:01f31e923fe2	262	defined(CPU_MK20DX64VFT5) \|\| defined(CPU_MK20DN64VFT5) \|\| defined(CPU_MK20DX32VFT5) \|\| defined(CPU_MK20DN32VFT5) \|\| \
Pawel Zarembski	0:01f31e923fe2	263	defined(CPU_MK20DX128VLF5) \|\| defined(CPU_MK20DN128VLF5) \|\| defined(CPU_MK20DX64VLF5) \|\| defined(CPU_MK20DN64VLF5) \|\| \
Pawel Zarembski	0:01f31e923fe2	264	defined(CPU_MK20DX32VLF5) \|\| defined(CPU_MK20DN32VLF5)
Pawel Zarembski	0:01f31e923fe2	265	kDmaRequestMux0SoftwareDMARequest = 0\|0x100U, /*< Disable /
Pawel Zarembski	0:01f31e923fe2	266	kDmaRequestMux0Reserved1 = 1\|0x100U, /*< Reserved1 /
Pawel Zarembski	0:01f31e923fe2	267	kDmaRequestMux0UART0ReceiveDMARequest = 2\|0x100U, /*< UART0 Receive. /
Pawel Zarembski	0:01f31e923fe2	268	kDmaRequestMux0UART0TransmitDMARequest = 3\|0x100U, /*< UART0 Transmit. /
Pawel Zarembski	0:01f31e923fe2	269	kDmaRequestMux0UART1ReceiveDMARequest = 4\|0x100U, /*< UART1 Receive. /
Pawel Zarembski	0:01f31e923fe2	270	kDmaRequestMux0UART1TransmitDMARequest = 5\|0x100U, /*< UART1 Transmit. /
Pawel Zarembski	0:01f31e923fe2	271	kDmaRequestMux0UART2ReceiveDMARequest = 6\|0x100U, /*< UART2 Receive. /
Pawel Zarembski	0:01f31e923fe2	272	kDmaRequestMux0UART2TransmitDMARequest = 7\|0x100U, /*< UART2 Transmit. /
Pawel Zarembski	0:01f31e923fe2	273	kDmaRequestMux0Reserved8 = 8\|0x100U, /*< Reserved8 /
Pawel Zarembski	0:01f31e923fe2	274	kDmaRequestMux0Reserved9 = 9\|0x100U, /*< Reserved9 /
Pawel Zarembski	0:01f31e923fe2	275	kDmaRequestMux0Reserved10 = 10\|0x100U, /*< Reserved10 /
Pawel Zarembski	0:01f31e923fe2	276	kDmaRequestMux0Reserved11 = 11\|0x100U, /*< Reserved11 /
Pawel Zarembski	0:01f31e923fe2	277	kDmaRequestMux0Reserved12 = 12\|0x100U, /*< Reserved12 /
Pawel Zarembski	0:01f31e923fe2	278	kDmaRequestMux0Reserved13 = 13\|0x100U, /*< Reserved13 /
Pawel Zarembski	0:01f31e923fe2	279	kDmaRequestMux0I2S0ReceiveDMARequest = 14\|0x100U, /*< I2S0 Receive. /
Pawel Zarembski	0:01f31e923fe2	280	kDmaRequestMux0I2S0TransmitDMARequest = 15\|0x100U, /*< I2S0 Transmit. /
Pawel Zarembski	0:01f31e923fe2	281	kDmaRequestMux0SPI0ReceiveDMARequest = 16\|0x100U, /*< SPI0 Receive. /
Pawel Zarembski	0:01f31e923fe2	282	kDmaRequestMux0SPI0TransmitDMARequest = 17\|0x100U, /*< SPI0 Transmit. /
Pawel Zarembski	0:01f31e923fe2	283	kDmaRequestMux0Reserved18 = 18\|0x100U, /*< Reserved18 /
Pawel Zarembski	0:01f31e923fe2	284	kDmaRequestMux0Reserved19 = 19\|0x100U, /*< Reserved19 /
Pawel Zarembski	0:01f31e923fe2	285	kDmaRequestMux0Reserved20 = 20\|0x100U, /*< Reserved20 /
Pawel Zarembski	0:01f31e923fe2	286	kDmaRequestMux0Reserved21 = 21\|0x100U, /*< Reserved21 /
Pawel Zarembski	0:01f31e923fe2	287	kDmaRequestMux0I2C0DMARequest = 22\|0x100U, /*< I2C0. /
Pawel Zarembski	0:01f31e923fe2	288	kDmaRequestMux0Reserved23 = 23\|0x100U, /*< Reserved23 /
Pawel Zarembski	0:01f31e923fe2	289	kDmaRequestMux0FTM0C0DMARequest = 24\|0x100U, /*< FTM0 channel 0. /
Pawel Zarembski	0:01f31e923fe2	290	kDmaRequestMux0FTM0C1DMARequest = 25\|0x100U, /*< FTM0 channel 1. /
Pawel Zarembski	0:01f31e923fe2	291	kDmaRequestMux0FTM0C2DMARequest = 26\|0x100U, /*< FTM0 channel 2. /
Pawel Zarembski	0:01f31e923fe2	292	kDmaRequestMux0FTM0C3DMARequest = 27\|0x100U, /*< FTM0 channel 3. /
Pawel Zarembski	0:01f31e923fe2	293	kDmaRequestMux0FTM0C4DMARequest = 28\|0x100U, /*< FTM0 channel 4. /
Pawel Zarembski	0:01f31e923fe2	294	kDmaRequestMux0FTM0C5DMARequest = 29\|0x100U, /*< FTM0 channel 5. /
Pawel Zarembski	0:01f31e923fe2	295	kDmaRequestMux0FTM0C6DMARequest = 30\|0x100U, /*< FTM0 channel 6. /
Pawel Zarembski	0:01f31e923fe2	296	kDmaRequestMux0FTM0C7DMARequest = 31\|0x100U, /*< FTM0 channel 7. /
Pawel Zarembski	0:01f31e923fe2	297	kDmaRequestMux0FTM1C0DMARequest = 32\|0x100U, /*< FTM1 channel 0. /
Pawel Zarembski	0:01f31e923fe2	298	kDmaRequestMux0FTM1C1DMARequest = 33\|0x100U, /*< FTM1 channel 1. /
Pawel Zarembski	0:01f31e923fe2	299	kDmaRequestMux0Reserved34 = 34\|0x100U, /*< Reserved34 /
Pawel Zarembski	0:01f31e923fe2	300	kDmaRequestMux0Reserved35 = 35\|0x100U, /*< Reserved35 /
Pawel Zarembski	0:01f31e923fe2	301	kDmaRequestMux0Reserved36 = 36\|0x100U, /*< Reserved36 /
Pawel Zarembski	0:01f31e923fe2	302	kDmaRequestMux0Reserved37 = 37\|0x100U, /*< Reserved37 /
Pawel Zarembski	0:01f31e923fe2	303	kDmaRequestMux0Reserved38 = 38\|0x100U, /*< Reserved38 /
Pawel Zarembski	0:01f31e923fe2	304	kDmaRequestMux0Reserved39 = 39\|0x100U, /*< Reserved39 /
Pawel Zarembski	0:01f31e923fe2	305	kDmaRequestMux0ADC0DMARequest = 40\|0x100U, /*< ADC0. /
Pawel Zarembski	0:01f31e923fe2	306	kDmaRequestMux0Reserved41 = 41\|0x100U, /*< Reserved41 /
Pawel Zarembski	0:01f31e923fe2	307	kDmaRequestMux0CMP0DMARequest = 42\|0x100U, /*< CMP0. /
Pawel Zarembski	0:01f31e923fe2	308	kDmaRequestMux0CMP1DMARequest = 43\|0x100U, /*< CMP1. /
Pawel Zarembski	0:01f31e923fe2	309	kDmaRequestMux0Reserved44 = 44\|0x100U, /*< Reserved44 /
Pawel Zarembski	0:01f31e923fe2	310	kDmaRequestMux0Reserved45 = 45\|0x100U, /*< Reserved45 /
Pawel Zarembski	0:01f31e923fe2	311	kDmaRequestMux0Reserved46 = 46\|0x100U, /*< Reserved46 /
Pawel Zarembski	0:01f31e923fe2	312	kDmaRequestMux0CMTDMARequest = 47\|0x100U, /*< CMT. /
Pawel Zarembski	0:01f31e923fe2	313	kDmaRequestMux0PDBDMARequest = 48\|0x100U, /*< PDB. /
Pawel Zarembski	0:01f31e923fe2	314	kDmaRequestMux0GPIOPortADMARequest = 49\|0x100U, /*< GPIO Port A. /
Pawel Zarembski	0:01f31e923fe2	315	kDmaRequestMux0GPIOPortBDMARequest = 50\|0x100U, /*< GPIO Port B. /
Pawel Zarembski	0:01f31e923fe2	316	kDmaRequestMux0GPIOPortCDMARequest = 51\|0x100U, /*< GPIO Port C. /
Pawel Zarembski	0:01f31e923fe2	317	kDmaRequestMux0GPIOPortDDMARequest = 52\|0x100U, /*< GPIO Port D. /
Pawel Zarembski	0:01f31e923fe2	318	kDmaRequestMux0GPIOPortEDMARequest = 53\|0x100U, /*< GPIO Port E. /
Pawel Zarembski	0:01f31e923fe2	319	kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	320	kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	321	kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	322	kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	323	kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	324	kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	325	kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	326	kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	327	kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	328	kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63\|0x100U, /*< Always enabled. /
Pawel Zarembski	0:01f31e923fe2	329	#else
Pawel Zarembski	0:01f31e923fe2	330	#error "No valid CPU defined!"
Pawel Zarembski	0:01f31e923fe2	331	#endif
Pawel Zarembski	0:01f31e923fe2	332	} dma_request_source_t;
Pawel Zarembski	0:01f31e923fe2	333
Pawel Zarembski	0:01f31e923fe2	334	/* @} */
Pawel Zarembski	0:01f31e923fe2	335
Pawel Zarembski	0:01f31e923fe2	336
Pawel Zarembski	0:01f31e923fe2	337	/*!
Pawel Zarembski	0:01f31e923fe2	338	* @}
Pawel Zarembski	0:01f31e923fe2	339	/ / end of group Mapping_Information */
Pawel Zarembski	0:01f31e923fe2	340
Pawel Zarembski	0:01f31e923fe2	341
Pawel Zarembski	0:01f31e923fe2	342	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	343	-- Device Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	344	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	345
Pawel Zarembski	0:01f31e923fe2	346	/*!
Pawel Zarembski	0:01f31e923fe2	347	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	348	* @{
Pawel Zarembski	0:01f31e923fe2	349	*/
Pawel Zarembski	0:01f31e923fe2	350
Pawel Zarembski	0:01f31e923fe2	351
Pawel Zarembski	0:01f31e923fe2	352	/*
Pawel Zarembski	0:01f31e923fe2	353	** Start of section using anonymous unions
Pawel Zarembski	0:01f31e923fe2	354	*/
Pawel Zarembski	0:01f31e923fe2	355
Pawel Zarembski	0:01f31e923fe2	356	#if defined(__ARMCC_VERSION)
Pawel Zarembski	0:01f31e923fe2	357	#pragma push
Pawel Zarembski	0:01f31e923fe2	358	#pragma anon_unions
Pawel Zarembski	0:01f31e923fe2	359	#elif defined(__CWCC__)
Pawel Zarembski	0:01f31e923fe2	360	#pragma push
Pawel Zarembski	0:01f31e923fe2	361	#pragma cpp_extensions on
Pawel Zarembski	0:01f31e923fe2	362	#elif defined(__GNUC__)
Pawel Zarembski	0:01f31e923fe2	363	/* anonymous unions are enabled by default */
Pawel Zarembski	0:01f31e923fe2	364	#elif defined(__IAR_SYSTEMS_ICC__)
Pawel Zarembski	0:01f31e923fe2	365	#pragma language=extended
Pawel Zarembski	0:01f31e923fe2	366	#else
Pawel Zarembski	0:01f31e923fe2	367	#error Not supported compiler type
Pawel Zarembski	0:01f31e923fe2	368	#endif
Pawel Zarembski	0:01f31e923fe2	369
Pawel Zarembski	0:01f31e923fe2	370	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	371	-- ADC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	372	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	373
Pawel Zarembski	0:01f31e923fe2	374	/*!
Pawel Zarembski	0:01f31e923fe2	375	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	376	* @{
Pawel Zarembski	0:01f31e923fe2	377	*/
Pawel Zarembski	0:01f31e923fe2	378
Pawel Zarembski	0:01f31e923fe2	379	/** ADC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	380	typedef struct {
Pawel Zarembski	0:01f31e923fe2	381	__IO uint32_t SC1[2]; /*< ADC status and control registers 1, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	382	__IO uint32_t CFG1; /*< ADC configuration register 1, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	383	__IO uint32_t CFG2; /*< Configuration register 2, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	384	__I uint32_t R[2]; /*< ADC data result register, array offset: 0x10, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	385	__IO uint32_t CV1; /*< Compare value registers, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	386	__IO uint32_t CV2; /*< Compare value registers, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	387	__IO uint32_t SC2; /*< Status and control register 2, offset: 0x20 /
Pawel Zarembski	0:01f31e923fe2	388	__IO uint32_t SC3; /*< Status and control register 3, offset: 0x24 /
Pawel Zarembski	0:01f31e923fe2	389	__IO uint32_t OFS; /*< ADC offset correction register, offset: 0x28 /
Pawel Zarembski	0:01f31e923fe2	390	__IO uint32_t PG; /*< ADC plus-side gain register, offset: 0x2C /
Pawel Zarembski	0:01f31e923fe2	391	__IO uint32_t MG; /*< ADC minus-side gain register, offset: 0x30 /
Pawel Zarembski	0:01f31e923fe2	392	__IO uint32_t CLPD; /*< ADC plus-side general calibration value register, offset: 0x34 /
Pawel Zarembski	0:01f31e923fe2	393	__IO uint32_t CLPS; /*< ADC plus-side general calibration value register, offset: 0x38 /
Pawel Zarembski	0:01f31e923fe2	394	__IO uint32_t CLP4; /*< ADC plus-side general calibration value register, offset: 0x3C /
Pawel Zarembski	0:01f31e923fe2	395	__IO uint32_t CLP3; /*< ADC plus-side general calibration value register, offset: 0x40 /
Pawel Zarembski	0:01f31e923fe2	396	__IO uint32_t CLP2; /*< ADC plus-side general calibration value register, offset: 0x44 /
Pawel Zarembski	0:01f31e923fe2	397	__IO uint32_t CLP1; /*< ADC plus-side general calibration value register, offset: 0x48 /
Pawel Zarembski	0:01f31e923fe2	398	__IO uint32_t CLP0; /*< ADC plus-side general calibration value register, offset: 0x4C /
Pawel Zarembski	0:01f31e923fe2	399	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	400	__IO uint32_t CLMD; /*< ADC minus-side general calibration value register, offset: 0x54 /
Pawel Zarembski	0:01f31e923fe2	401	__IO uint32_t CLMS; /*< ADC minus-side general calibration value register, offset: 0x58 /
Pawel Zarembski	0:01f31e923fe2	402	__IO uint32_t CLM4; /*< ADC minus-side general calibration value register, offset: 0x5C /
Pawel Zarembski	0:01f31e923fe2	403	__IO uint32_t CLM3; /*< ADC minus-side general calibration value register, offset: 0x60 /
Pawel Zarembski	0:01f31e923fe2	404	__IO uint32_t CLM2; /*< ADC minus-side general calibration value register, offset: 0x64 /
Pawel Zarembski	0:01f31e923fe2	405	__IO uint32_t CLM1; /*< ADC minus-side general calibration value register, offset: 0x68 /
Pawel Zarembski	0:01f31e923fe2	406	__IO uint32_t CLM0; /*< ADC minus-side general calibration value register, offset: 0x6C /
Pawel Zarembski	0:01f31e923fe2	407	} ADC_Type;
Pawel Zarembski	0:01f31e923fe2	408
Pawel Zarembski	0:01f31e923fe2	409	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	410	-- ADC Register Masks
Pawel Zarembski	0:01f31e923fe2	411	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	412
Pawel Zarembski	0:01f31e923fe2	413	/*!
Pawel Zarembski	0:01f31e923fe2	414	* @addtogroup ADC_Register_Masks ADC Register Masks
Pawel Zarembski	0:01f31e923fe2	415	* @{
Pawel Zarembski	0:01f31e923fe2	416	*/
Pawel Zarembski	0:01f31e923fe2	417
Pawel Zarembski	0:01f31e923fe2	418	/! @name SC1 - ADC status and control registers 1 /
Pawel Zarembski	0:01f31e923fe2	419	#define ADC_SC1_ADCH_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	420	#define ADC_SC1_ADCH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	421	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
Pawel Zarembski	0:01f31e923fe2	422	#define ADC_SC1_DIFF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	423	#define ADC_SC1_DIFF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	424	#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
Pawel Zarembski	0:01f31e923fe2	425	#define ADC_SC1_AIEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	426	#define ADC_SC1_AIEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	427	#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	428	#define ADC_SC1_COCO_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	429	#define ADC_SC1_COCO_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	430	#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
Pawel Zarembski	0:01f31e923fe2	431
Pawel Zarembski	0:01f31e923fe2	432	/* The count of ADC_SC1 */
Pawel Zarembski	0:01f31e923fe2	433	#define ADC_SC1_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	434
Pawel Zarembski	0:01f31e923fe2	435	/! @name CFG1 - ADC configuration register 1 /
Pawel Zarembski	0:01f31e923fe2	436	#define ADC_CFG1_ADICLK_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	437	#define ADC_CFG1_ADICLK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	438	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
Pawel Zarembski	0:01f31e923fe2	439	#define ADC_CFG1_MODE_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	440	#define ADC_CFG1_MODE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	441	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
Pawel Zarembski	0:01f31e923fe2	442	#define ADC_CFG1_ADLSMP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	443	#define ADC_CFG1_ADLSMP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	444	#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
Pawel Zarembski	0:01f31e923fe2	445	#define ADC_CFG1_ADIV_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	446	#define ADC_CFG1_ADIV_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	447	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
Pawel Zarembski	0:01f31e923fe2	448	#define ADC_CFG1_ADLPC_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	449	#define ADC_CFG1_ADLPC_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	450	#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
Pawel Zarembski	0:01f31e923fe2	451
Pawel Zarembski	0:01f31e923fe2	452	/! @name CFG2 - Configuration register 2 /
Pawel Zarembski	0:01f31e923fe2	453	#define ADC_CFG2_ADLSTS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	454	#define ADC_CFG2_ADLSTS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	455	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
Pawel Zarembski	0:01f31e923fe2	456	#define ADC_CFG2_ADHSC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	457	#define ADC_CFG2_ADHSC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	458	#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
Pawel Zarembski	0:01f31e923fe2	459	#define ADC_CFG2_ADACKEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	460	#define ADC_CFG2_ADACKEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	461	#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	462	#define ADC_CFG2_MUXSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	463	#define ADC_CFG2_MUXSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	464	#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	465
Pawel Zarembski	0:01f31e923fe2	466	/! @name R - ADC data result register /
Pawel Zarembski	0:01f31e923fe2	467	#define ADC_R_D_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	468	#define ADC_R_D_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	469	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
Pawel Zarembski	0:01f31e923fe2	470
Pawel Zarembski	0:01f31e923fe2	471	/* The count of ADC_R */
Pawel Zarembski	0:01f31e923fe2	472	#define ADC_R_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	473
Pawel Zarembski	0:01f31e923fe2	474	/! @name CV1 - Compare value registers /
Pawel Zarembski	0:01f31e923fe2	475	#define ADC_CV1_CV_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	476	#define ADC_CV1_CV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	477	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
Pawel Zarembski	0:01f31e923fe2	478
Pawel Zarembski	0:01f31e923fe2	479	/! @name CV2 - Compare value registers /
Pawel Zarembski	0:01f31e923fe2	480	#define ADC_CV2_CV_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	481	#define ADC_CV2_CV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	482	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
Pawel Zarembski	0:01f31e923fe2	483
Pawel Zarembski	0:01f31e923fe2	484	/! @name SC2 - Status and control register 2 /
Pawel Zarembski	0:01f31e923fe2	485	#define ADC_SC2_REFSEL_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	486	#define ADC_SC2_REFSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	487	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	488	#define ADC_SC2_DMAEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	489	#define ADC_SC2_DMAEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	490	#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	491	#define ADC_SC2_ACREN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	492	#define ADC_SC2_ACREN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	493	#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
Pawel Zarembski	0:01f31e923fe2	494	#define ADC_SC2_ACFGT_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	495	#define ADC_SC2_ACFGT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	496	#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
Pawel Zarembski	0:01f31e923fe2	497	#define ADC_SC2_ACFE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	498	#define ADC_SC2_ACFE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	499	#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
Pawel Zarembski	0:01f31e923fe2	500	#define ADC_SC2_ADTRG_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	501	#define ADC_SC2_ADTRG_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	502	#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
Pawel Zarembski	0:01f31e923fe2	503	#define ADC_SC2_ADACT_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	504	#define ADC_SC2_ADACT_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	505	#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
Pawel Zarembski	0:01f31e923fe2	506
Pawel Zarembski	0:01f31e923fe2	507	/! @name SC3 - Status and control register 3 /
Pawel Zarembski	0:01f31e923fe2	508	#define ADC_SC3_AVGS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	509	#define ADC_SC3_AVGS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	510	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
Pawel Zarembski	0:01f31e923fe2	511	#define ADC_SC3_AVGE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	512	#define ADC_SC3_AVGE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	513	#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
Pawel Zarembski	0:01f31e923fe2	514	#define ADC_SC3_ADCO_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	515	#define ADC_SC3_ADCO_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	516	#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
Pawel Zarembski	0:01f31e923fe2	517	#define ADC_SC3_CALF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	518	#define ADC_SC3_CALF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	519	#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
Pawel Zarembski	0:01f31e923fe2	520	#define ADC_SC3_CAL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	521	#define ADC_SC3_CAL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	522	#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
Pawel Zarembski	0:01f31e923fe2	523
Pawel Zarembski	0:01f31e923fe2	524	/! @name OFS - ADC offset correction register /
Pawel Zarembski	0:01f31e923fe2	525	#define ADC_OFS_OFS_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	526	#define ADC_OFS_OFS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	527	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
Pawel Zarembski	0:01f31e923fe2	528
Pawel Zarembski	0:01f31e923fe2	529	/! @name PG - ADC plus-side gain register /
Pawel Zarembski	0:01f31e923fe2	530	#define ADC_PG_PG_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	531	#define ADC_PG_PG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	532	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
Pawel Zarembski	0:01f31e923fe2	533
Pawel Zarembski	0:01f31e923fe2	534	/! @name MG - ADC minus-side gain register /
Pawel Zarembski	0:01f31e923fe2	535	#define ADC_MG_MG_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	536	#define ADC_MG_MG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	537	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
Pawel Zarembski	0:01f31e923fe2	538
Pawel Zarembski	0:01f31e923fe2	539	/! @name CLPD - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	540	#define ADC_CLPD_CLPD_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	541	#define ADC_CLPD_CLPD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	542	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
Pawel Zarembski	0:01f31e923fe2	543
Pawel Zarembski	0:01f31e923fe2	544	/! @name CLPS - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	545	#define ADC_CLPS_CLPS_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	546	#define ADC_CLPS_CLPS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	547	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
Pawel Zarembski	0:01f31e923fe2	548
Pawel Zarembski	0:01f31e923fe2	549	/! @name CLP4 - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	550	#define ADC_CLP4_CLP4_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	551	#define ADC_CLP4_CLP4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	552	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
Pawel Zarembski	0:01f31e923fe2	553
Pawel Zarembski	0:01f31e923fe2	554	/! @name CLP3 - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	555	#define ADC_CLP3_CLP3_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	556	#define ADC_CLP3_CLP3_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	557	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
Pawel Zarembski	0:01f31e923fe2	558
Pawel Zarembski	0:01f31e923fe2	559	/! @name CLP2 - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	560	#define ADC_CLP2_CLP2_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	561	#define ADC_CLP2_CLP2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	562	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
Pawel Zarembski	0:01f31e923fe2	563
Pawel Zarembski	0:01f31e923fe2	564	/! @name CLP1 - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	565	#define ADC_CLP1_CLP1_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	566	#define ADC_CLP1_CLP1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	567	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
Pawel Zarembski	0:01f31e923fe2	568
Pawel Zarembski	0:01f31e923fe2	569	/! @name CLP0 - ADC plus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	570	#define ADC_CLP0_CLP0_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	571	#define ADC_CLP0_CLP0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	572	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
Pawel Zarembski	0:01f31e923fe2	573
Pawel Zarembski	0:01f31e923fe2	574	/! @name CLMD - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	575	#define ADC_CLMD_CLMD_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	576	#define ADC_CLMD_CLMD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	577	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
Pawel Zarembski	0:01f31e923fe2	578
Pawel Zarembski	0:01f31e923fe2	579	/! @name CLMS - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	580	#define ADC_CLMS_CLMS_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	581	#define ADC_CLMS_CLMS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	582	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
Pawel Zarembski	0:01f31e923fe2	583
Pawel Zarembski	0:01f31e923fe2	584	/! @name CLM4 - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	585	#define ADC_CLM4_CLM4_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	586	#define ADC_CLM4_CLM4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	587	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
Pawel Zarembski	0:01f31e923fe2	588
Pawel Zarembski	0:01f31e923fe2	589	/! @name CLM3 - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	590	#define ADC_CLM3_CLM3_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	591	#define ADC_CLM3_CLM3_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	592	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
Pawel Zarembski	0:01f31e923fe2	593
Pawel Zarembski	0:01f31e923fe2	594	/! @name CLM2 - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	595	#define ADC_CLM2_CLM2_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	596	#define ADC_CLM2_CLM2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	597	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
Pawel Zarembski	0:01f31e923fe2	598
Pawel Zarembski	0:01f31e923fe2	599	/! @name CLM1 - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	600	#define ADC_CLM1_CLM1_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	601	#define ADC_CLM1_CLM1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	602	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
Pawel Zarembski	0:01f31e923fe2	603
Pawel Zarembski	0:01f31e923fe2	604	/! @name CLM0 - ADC minus-side general calibration value register /
Pawel Zarembski	0:01f31e923fe2	605	#define ADC_CLM0_CLM0_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	606	#define ADC_CLM0_CLM0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	607	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
Pawel Zarembski	0:01f31e923fe2	608
Pawel Zarembski	0:01f31e923fe2	609
Pawel Zarembski	0:01f31e923fe2	610	/*!
Pawel Zarembski	0:01f31e923fe2	611	* @}
Pawel Zarembski	0:01f31e923fe2	612	/ / end of group ADC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	613
Pawel Zarembski	0:01f31e923fe2	614
Pawel Zarembski	0:01f31e923fe2	615	/* ADC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	616	/** Peripheral ADC0 base address */
Pawel Zarembski	0:01f31e923fe2	617	#define ADC0_BASE (0x4003B000u)
Pawel Zarembski	0:01f31e923fe2	618	/** Peripheral ADC0 base pointer */
Pawel Zarembski	0:01f31e923fe2	619	#define ADC0 ((ADC_Type *)ADC0_BASE)
Pawel Zarembski	0:01f31e923fe2	620	/** Array initializer of ADC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	621	#define ADC_BASE_ADDRS { ADC0_BASE }
Pawel Zarembski	0:01f31e923fe2	622	/** Array initializer of ADC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	623	#define ADC_BASE_PTRS { ADC0 }
Pawel Zarembski	0:01f31e923fe2	624	/** Interrupt vectors for the ADC peripheral type */
Pawel Zarembski	0:01f31e923fe2	625	#define ADC_IRQS { ADC0_IRQn }
Pawel Zarembski	0:01f31e923fe2	626
Pawel Zarembski	0:01f31e923fe2	627	/*!
Pawel Zarembski	0:01f31e923fe2	628	* @}
Pawel Zarembski	0:01f31e923fe2	629	/ / end of group ADC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	630
Pawel Zarembski	0:01f31e923fe2	631
Pawel Zarembski	0:01f31e923fe2	632	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	633	-- CMP Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	634	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	635
Pawel Zarembski	0:01f31e923fe2	636	/*!
Pawel Zarembski	0:01f31e923fe2	637	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	638	* @{
Pawel Zarembski	0:01f31e923fe2	639	*/
Pawel Zarembski	0:01f31e923fe2	640
Pawel Zarembski	0:01f31e923fe2	641	/** CMP - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	642	typedef struct {
Pawel Zarembski	0:01f31e923fe2	643	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	644	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	645	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	646	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	647	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	648	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	649	} CMP_Type;
Pawel Zarembski	0:01f31e923fe2	650
Pawel Zarembski	0:01f31e923fe2	651	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	652	-- CMP Register Masks
Pawel Zarembski	0:01f31e923fe2	653	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	654
Pawel Zarembski	0:01f31e923fe2	655	/*!
Pawel Zarembski	0:01f31e923fe2	656	* @addtogroup CMP_Register_Masks CMP Register Masks
Pawel Zarembski	0:01f31e923fe2	657	* @{
Pawel Zarembski	0:01f31e923fe2	658	*/
Pawel Zarembski	0:01f31e923fe2	659
Pawel Zarembski	0:01f31e923fe2	660	/! @name CR0 - CMP Control Register 0 /
Pawel Zarembski	0:01f31e923fe2	661	#define CMP_CR0_HYSTCTR_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	662	#define CMP_CR0_HYSTCTR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	663	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
Pawel Zarembski	0:01f31e923fe2	664	#define CMP_CR0_FILTER_CNT_MASK (0x70U)
Pawel Zarembski	0:01f31e923fe2	665	#define CMP_CR0_FILTER_CNT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	666	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
Pawel Zarembski	0:01f31e923fe2	667
Pawel Zarembski	0:01f31e923fe2	668	/! @name CR1 - CMP Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	669	#define CMP_CR1_EN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	670	#define CMP_CR1_EN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	671	#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
Pawel Zarembski	0:01f31e923fe2	672	#define CMP_CR1_OPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	673	#define CMP_CR1_OPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	674	#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
Pawel Zarembski	0:01f31e923fe2	675	#define CMP_CR1_COS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	676	#define CMP_CR1_COS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	677	#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
Pawel Zarembski	0:01f31e923fe2	678	#define CMP_CR1_INV_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	679	#define CMP_CR1_INV_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	680	#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
Pawel Zarembski	0:01f31e923fe2	681	#define CMP_CR1_PMODE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	682	#define CMP_CR1_PMODE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	683	#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	684	#define CMP_CR1_WE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	685	#define CMP_CR1_WE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	686	#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
Pawel Zarembski	0:01f31e923fe2	687	#define CMP_CR1_SE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	688	#define CMP_CR1_SE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	689	#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
Pawel Zarembski	0:01f31e923fe2	690
Pawel Zarembski	0:01f31e923fe2	691	/! @name FPR - CMP Filter Period Register /
Pawel Zarembski	0:01f31e923fe2	692	#define CMP_FPR_FILT_PER_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	693	#define CMP_FPR_FILT_PER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	694	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
Pawel Zarembski	0:01f31e923fe2	695
Pawel Zarembski	0:01f31e923fe2	696	/! @name SCR - CMP Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	697	#define CMP_SCR_COUT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	698	#define CMP_SCR_COUT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	699	#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
Pawel Zarembski	0:01f31e923fe2	700	#define CMP_SCR_CFF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	701	#define CMP_SCR_CFF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	702	#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
Pawel Zarembski	0:01f31e923fe2	703	#define CMP_SCR_CFR_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	704	#define CMP_SCR_CFR_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	705	#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
Pawel Zarembski	0:01f31e923fe2	706	#define CMP_SCR_IEF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	707	#define CMP_SCR_IEF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	708	#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
Pawel Zarembski	0:01f31e923fe2	709	#define CMP_SCR_IER_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	710	#define CMP_SCR_IER_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	711	#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
Pawel Zarembski	0:01f31e923fe2	712	#define CMP_SCR_DMAEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	713	#define CMP_SCR_DMAEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	714	#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	715
Pawel Zarembski	0:01f31e923fe2	716	/! @name DACCR - DAC Control Register /
Pawel Zarembski	0:01f31e923fe2	717	#define CMP_DACCR_VOSEL_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	718	#define CMP_DACCR_VOSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	719	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	720	#define CMP_DACCR_VRSEL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	721	#define CMP_DACCR_VRSEL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	722	#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	723	#define CMP_DACCR_DACEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	724	#define CMP_DACCR_DACEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	725	#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
Pawel Zarembski	0:01f31e923fe2	726
Pawel Zarembski	0:01f31e923fe2	727	/! @name MUXCR - MUX Control Register /
Pawel Zarembski	0:01f31e923fe2	728	#define CMP_MUXCR_MSEL_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	729	#define CMP_MUXCR_MSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	730	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	731	#define CMP_MUXCR_PSEL_MASK (0x38U)
Pawel Zarembski	0:01f31e923fe2	732	#define CMP_MUXCR_PSEL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	733	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	734
Pawel Zarembski	0:01f31e923fe2	735
Pawel Zarembski	0:01f31e923fe2	736	/*!
Pawel Zarembski	0:01f31e923fe2	737	* @}
Pawel Zarembski	0:01f31e923fe2	738	/ / end of group CMP_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	739
Pawel Zarembski	0:01f31e923fe2	740
Pawel Zarembski	0:01f31e923fe2	741	/* CMP - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	742	/** Peripheral CMP0 base address */
Pawel Zarembski	0:01f31e923fe2	743	#define CMP0_BASE (0x40073000u)
Pawel Zarembski	0:01f31e923fe2	744	/** Peripheral CMP0 base pointer */
Pawel Zarembski	0:01f31e923fe2	745	#define CMP0 ((CMP_Type *)CMP0_BASE)
Pawel Zarembski	0:01f31e923fe2	746	/** Peripheral CMP1 base address */
Pawel Zarembski	0:01f31e923fe2	747	#define CMP1_BASE (0x40073008u)
Pawel Zarembski	0:01f31e923fe2	748	/** Peripheral CMP1 base pointer */
Pawel Zarembski	0:01f31e923fe2	749	#define CMP1 ((CMP_Type *)CMP1_BASE)
Pawel Zarembski	0:01f31e923fe2	750	/** Array initializer of CMP peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	751	#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
Pawel Zarembski	0:01f31e923fe2	752	/** Array initializer of CMP peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	753	#define CMP_BASE_PTRS { CMP0, CMP1 }
Pawel Zarembski	0:01f31e923fe2	754	/** Interrupt vectors for the CMP peripheral type */
Pawel Zarembski	0:01f31e923fe2	755	#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
Pawel Zarembski	0:01f31e923fe2	756
Pawel Zarembski	0:01f31e923fe2	757	/*!
Pawel Zarembski	0:01f31e923fe2	758	* @}
Pawel Zarembski	0:01f31e923fe2	759	/ / end of group CMP_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	760
Pawel Zarembski	0:01f31e923fe2	761
Pawel Zarembski	0:01f31e923fe2	762	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	763	-- CMT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	764	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	765
Pawel Zarembski	0:01f31e923fe2	766	/*!
Pawel Zarembski	0:01f31e923fe2	767	* @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	768	* @{
Pawel Zarembski	0:01f31e923fe2	769	*/
Pawel Zarembski	0:01f31e923fe2	770
Pawel Zarembski	0:01f31e923fe2	771	/** CMT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	772	typedef struct {
Pawel Zarembski	0:01f31e923fe2	773	__IO uint8_t CGH1; /*< CMT Carrier Generator High Data Register 1, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	774	__IO uint8_t CGL1; /*< CMT Carrier Generator Low Data Register 1, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	775	__IO uint8_t CGH2; /*< CMT Carrier Generator High Data Register 2, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	776	__IO uint8_t CGL2; /*< CMT Carrier Generator Low Data Register 2, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	777	__IO uint8_t OC; /*< CMT Output Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	778	__IO uint8_t MSC; /*< CMT Modulator Status and Control Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	779	__IO uint8_t CMD1; /*< CMT Modulator Data Register Mark High, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	780	__IO uint8_t CMD2; /*< CMT Modulator Data Register Mark Low, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	781	__IO uint8_t CMD3; /*< CMT Modulator Data Register Space High, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	782	__IO uint8_t CMD4; /*< CMT Modulator Data Register Space Low, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	783	__IO uint8_t PPS; /*< CMT Primary Prescaler Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	784	__IO uint8_t DMA; /*< CMT Direct Memory Access, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	785	} CMT_Type;
Pawel Zarembski	0:01f31e923fe2	786
Pawel Zarembski	0:01f31e923fe2	787	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	788	-- CMT Register Masks
Pawel Zarembski	0:01f31e923fe2	789	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	790
Pawel Zarembski	0:01f31e923fe2	791	/*!
Pawel Zarembski	0:01f31e923fe2	792	* @addtogroup CMT_Register_Masks CMT Register Masks
Pawel Zarembski	0:01f31e923fe2	793	* @{
Pawel Zarembski	0:01f31e923fe2	794	*/
Pawel Zarembski	0:01f31e923fe2	795
Pawel Zarembski	0:01f31e923fe2	796	/! @name CGH1 - CMT Carrier Generator High Data Register 1 /
Pawel Zarembski	0:01f31e923fe2	797	#define CMT_CGH1_PH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	798	#define CMT_CGH1_PH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	799	#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
Pawel Zarembski	0:01f31e923fe2	800
Pawel Zarembski	0:01f31e923fe2	801	/! @name CGL1 - CMT Carrier Generator Low Data Register 1 /
Pawel Zarembski	0:01f31e923fe2	802	#define CMT_CGL1_PL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	803	#define CMT_CGL1_PL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	804	#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
Pawel Zarembski	0:01f31e923fe2	805
Pawel Zarembski	0:01f31e923fe2	806	/! @name CGH2 - CMT Carrier Generator High Data Register 2 /
Pawel Zarembski	0:01f31e923fe2	807	#define CMT_CGH2_SH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	808	#define CMT_CGH2_SH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	809	#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
Pawel Zarembski	0:01f31e923fe2	810
Pawel Zarembski	0:01f31e923fe2	811	/! @name CGL2 - CMT Carrier Generator Low Data Register 2 /
Pawel Zarembski	0:01f31e923fe2	812	#define CMT_CGL2_SL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	813	#define CMT_CGL2_SL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	814	#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
Pawel Zarembski	0:01f31e923fe2	815
Pawel Zarembski	0:01f31e923fe2	816	/! @name OC - CMT Output Control Register /
Pawel Zarembski	0:01f31e923fe2	817	#define CMT_OC_IROPEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	818	#define CMT_OC_IROPEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	819	#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	820	#define CMT_OC_CMTPOL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	821	#define CMT_OC_CMTPOL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	822	#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	823	#define CMT_OC_IROL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	824	#define CMT_OC_IROL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	825	#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
Pawel Zarembski	0:01f31e923fe2	826
Pawel Zarembski	0:01f31e923fe2	827	/! @name MSC - CMT Modulator Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	828	#define CMT_MSC_MCGEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	829	#define CMT_MSC_MCGEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	830	#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	831	#define CMT_MSC_EOCIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	832	#define CMT_MSC_EOCIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	833	#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	834	#define CMT_MSC_FSK_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	835	#define CMT_MSC_FSK_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	836	#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
Pawel Zarembski	0:01f31e923fe2	837	#define CMT_MSC_BASE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	838	#define CMT_MSC_BASE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	839	#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
Pawel Zarembski	0:01f31e923fe2	840	#define CMT_MSC_EXSPC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	841	#define CMT_MSC_EXSPC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	842	#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
Pawel Zarembski	0:01f31e923fe2	843	#define CMT_MSC_CMTDIV_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	844	#define CMT_MSC_CMTDIV_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	845	#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	846	#define CMT_MSC_EOCF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	847	#define CMT_MSC_EOCF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	848	#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
Pawel Zarembski	0:01f31e923fe2	849
Pawel Zarembski	0:01f31e923fe2	850	/! @name CMD1 - CMT Modulator Data Register Mark High /
Pawel Zarembski	0:01f31e923fe2	851	#define CMT_CMD1_MB_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	852	#define CMT_CMD1_MB_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	853	#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
Pawel Zarembski	0:01f31e923fe2	854
Pawel Zarembski	0:01f31e923fe2	855	/! @name CMD2 - CMT Modulator Data Register Mark Low /
Pawel Zarembski	0:01f31e923fe2	856	#define CMT_CMD2_MB_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	857	#define CMT_CMD2_MB_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	858	#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
Pawel Zarembski	0:01f31e923fe2	859
Pawel Zarembski	0:01f31e923fe2	860	/! @name CMD3 - CMT Modulator Data Register Space High /
Pawel Zarembski	0:01f31e923fe2	861	#define CMT_CMD3_SB_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	862	#define CMT_CMD3_SB_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	863	#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
Pawel Zarembski	0:01f31e923fe2	864
Pawel Zarembski	0:01f31e923fe2	865	/! @name CMD4 - CMT Modulator Data Register Space Low /
Pawel Zarembski	0:01f31e923fe2	866	#define CMT_CMD4_SB_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	867	#define CMT_CMD4_SB_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	868	#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
Pawel Zarembski	0:01f31e923fe2	869
Pawel Zarembski	0:01f31e923fe2	870	/! @name PPS - CMT Primary Prescaler Register /
Pawel Zarembski	0:01f31e923fe2	871	#define CMT_PPS_PPSDIV_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	872	#define CMT_PPS_PPSDIV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	873	#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	874
Pawel Zarembski	0:01f31e923fe2	875	/! @name DMA - CMT Direct Memory Access /
Pawel Zarembski	0:01f31e923fe2	876	#define CMT_DMA_DMA_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	877	#define CMT_DMA_DMA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	878	#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	879
Pawel Zarembski	0:01f31e923fe2	880
Pawel Zarembski	0:01f31e923fe2	881	/*!
Pawel Zarembski	0:01f31e923fe2	882	* @}
Pawel Zarembski	0:01f31e923fe2	883	/ / end of group CMT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	884
Pawel Zarembski	0:01f31e923fe2	885
Pawel Zarembski	0:01f31e923fe2	886	/* CMT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	887	/** Peripheral CMT base address */
Pawel Zarembski	0:01f31e923fe2	888	#define CMT_BASE (0x40062000u)
Pawel Zarembski	0:01f31e923fe2	889	/** Peripheral CMT base pointer */
Pawel Zarembski	0:01f31e923fe2	890	#define CMT ((CMT_Type *)CMT_BASE)
Pawel Zarembski	0:01f31e923fe2	891	/** Array initializer of CMT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	892	#define CMT_BASE_ADDRS { CMT_BASE }
Pawel Zarembski	0:01f31e923fe2	893	/** Array initializer of CMT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	894	#define CMT_BASE_PTRS { CMT }
Pawel Zarembski	0:01f31e923fe2	895	/** Interrupt vectors for the CMT peripheral type */
Pawel Zarembski	0:01f31e923fe2	896	#define CMT_IRQS { CMT_IRQn }
Pawel Zarembski	0:01f31e923fe2	897
Pawel Zarembski	0:01f31e923fe2	898	/*!
Pawel Zarembski	0:01f31e923fe2	899	* @}
Pawel Zarembski	0:01f31e923fe2	900	/ / end of group CMT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	901
Pawel Zarembski	0:01f31e923fe2	902
Pawel Zarembski	0:01f31e923fe2	903	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	904	-- CRC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	905	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	906
Pawel Zarembski	0:01f31e923fe2	907	/*!
Pawel Zarembski	0:01f31e923fe2	908	* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	909	* @{
Pawel Zarembski	0:01f31e923fe2	910	*/
Pawel Zarembski	0:01f31e923fe2	911
Pawel Zarembski	0:01f31e923fe2	912	/** CRC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	913	typedef struct {
Pawel Zarembski	0:01f31e923fe2	914	union { /* offset: 0x0 */
Pawel Zarembski	0:01f31e923fe2	915	struct { /* offset: 0x0 */
Pawel Zarembski	0:01f31e923fe2	916	__IO uint16_t CRCL; /*< CRC_CRCL register., offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	917	__IO uint16_t CRCH; /*< CRC_CRCH register., offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	918	} ACCESS16BIT;
Pawel Zarembski	0:01f31e923fe2	919	__IO uint32_t CRC; /*< CRC Data Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	920	struct { /* offset: 0x0 */
Pawel Zarembski	0:01f31e923fe2	921	__IO uint8_t CRCLL; /*< CRC_CRCLL register., offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	922	__IO uint8_t CRCLU; /*< CRC_CRCLU register., offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	923	__IO uint8_t CRCHL; /*< CRC_CRCHL register., offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	924	__IO uint8_t CRCHU; /*< CRC_CRCHU register., offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	925	} ACCESS8BIT;
Pawel Zarembski	0:01f31e923fe2	926	};
Pawel Zarembski	0:01f31e923fe2	927	union { /* offset: 0x4 */
Pawel Zarembski	0:01f31e923fe2	928	struct { /* offset: 0x4 */
Pawel Zarembski	0:01f31e923fe2	929	__IO uint16_t GPOLYL; /*< CRC_GPOLYL register., offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	930	__IO uint16_t GPOLYH; /*< CRC_GPOLYH register., offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	931	} GPOLY_ACCESS16BIT;
Pawel Zarembski	0:01f31e923fe2	932	__IO uint32_t GPOLY; /*< CRC Polynomial Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	933	struct { /* offset: 0x4 */
Pawel Zarembski	0:01f31e923fe2	934	__IO uint8_t GPOLYLL; /*< CRC_GPOLYLL register., offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	935	__IO uint8_t GPOLYLU; /*< CRC_GPOLYLU register., offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	936	__IO uint8_t GPOLYHL; /*< CRC_GPOLYHL register., offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	937	__IO uint8_t GPOLYHU; /*< CRC_GPOLYHU register., offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	938	} GPOLY_ACCESS8BIT;
Pawel Zarembski	0:01f31e923fe2	939	};
Pawel Zarembski	0:01f31e923fe2	940	union { /* offset: 0x8 */
Pawel Zarembski	0:01f31e923fe2	941	__IO uint32_t CTRL; /*< CRC Control Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	942	struct { /* offset: 0x8 */
Pawel Zarembski	0:01f31e923fe2	943	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	944	__IO uint8_t CTRLHU; /*< CRC_CTRLHU register., offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	945	} CTRL_ACCESS8BIT;
Pawel Zarembski	0:01f31e923fe2	946	};
Pawel Zarembski	0:01f31e923fe2	947	} CRC_Type;
Pawel Zarembski	0:01f31e923fe2	948
Pawel Zarembski	0:01f31e923fe2	949	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	950	-- CRC Register Masks
Pawel Zarembski	0:01f31e923fe2	951	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	952
Pawel Zarembski	0:01f31e923fe2	953	/*!
Pawel Zarembski	0:01f31e923fe2	954	* @addtogroup CRC_Register_Masks CRC Register Masks
Pawel Zarembski	0:01f31e923fe2	955	* @{
Pawel Zarembski	0:01f31e923fe2	956	*/
Pawel Zarembski	0:01f31e923fe2	957
Pawel Zarembski	0:01f31e923fe2	958	/! @name CRCL - CRC_CRCL register. /
Pawel Zarembski	0:01f31e923fe2	959	#define CRC_CRCL_CRCL_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	960	#define CRC_CRCL_CRCL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	961	#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK)
Pawel Zarembski	0:01f31e923fe2	962
Pawel Zarembski	0:01f31e923fe2	963	/! @name CRCH - CRC_CRCH register. /
Pawel Zarembski	0:01f31e923fe2	964	#define CRC_CRCH_CRCH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	965	#define CRC_CRCH_CRCH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	966	#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK)
Pawel Zarembski	0:01f31e923fe2	967
Pawel Zarembski	0:01f31e923fe2	968	/! @name CRC - CRC Data Register /
Pawel Zarembski	0:01f31e923fe2	969	#define CRC_CRC_LL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	970	#define CRC_CRC_LL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	971	#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK)
Pawel Zarembski	0:01f31e923fe2	972	#define CRC_CRC_LU_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	973	#define CRC_CRC_LU_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	974	#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK)
Pawel Zarembski	0:01f31e923fe2	975	#define CRC_CRC_HL_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	976	#define CRC_CRC_HL_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	977	#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK)
Pawel Zarembski	0:01f31e923fe2	978	#define CRC_CRC_HU_MASK (0xFF000000U)
Pawel Zarembski	0:01f31e923fe2	979	#define CRC_CRC_HU_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	980	#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK)
Pawel Zarembski	0:01f31e923fe2	981
Pawel Zarembski	0:01f31e923fe2	982	/! @name CRCLL - CRC_CRCLL register. /
Pawel Zarembski	0:01f31e923fe2	983	#define CRC_CRCLL_CRCLL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	984	#define CRC_CRCLL_CRCLL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	985	#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK)
Pawel Zarembski	0:01f31e923fe2	986
Pawel Zarembski	0:01f31e923fe2	987	/! @name CRCLU - CRC_CRCLU register. /
Pawel Zarembski	0:01f31e923fe2	988	#define CRC_CRCLU_CRCLU_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	989	#define CRC_CRCLU_CRCLU_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	990	#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK)
Pawel Zarembski	0:01f31e923fe2	991
Pawel Zarembski	0:01f31e923fe2	992	/! @name CRCHL - CRC_CRCHL register. /
Pawel Zarembski	0:01f31e923fe2	993	#define CRC_CRCHL_CRCHL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	994	#define CRC_CRCHL_CRCHL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	995	#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK)
Pawel Zarembski	0:01f31e923fe2	996
Pawel Zarembski	0:01f31e923fe2	997	/! @name CRCHU - CRC_CRCHU register. /
Pawel Zarembski	0:01f31e923fe2	998	#define CRC_CRCHU_CRCHU_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	999	#define CRC_CRCHU_CRCHU_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1000	#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK)
Pawel Zarembski	0:01f31e923fe2	1001
Pawel Zarembski	0:01f31e923fe2	1002	/! @name GPOLYL - CRC_GPOLYL register. /
Pawel Zarembski	0:01f31e923fe2	1003	#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	1004	#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1005	#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
Pawel Zarembski	0:01f31e923fe2	1006
Pawel Zarembski	0:01f31e923fe2	1007	/! @name GPOLYH - CRC_GPOLYH register. /
Pawel Zarembski	0:01f31e923fe2	1008	#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	1009	#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1010	#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
Pawel Zarembski	0:01f31e923fe2	1011
Pawel Zarembski	0:01f31e923fe2	1012	/! @name GPOLY - CRC Polynomial Register /
Pawel Zarembski	0:01f31e923fe2	1013	#define CRC_GPOLY_LOW_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	1014	#define CRC_GPOLY_LOW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1015	#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
Pawel Zarembski	0:01f31e923fe2	1016	#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	1017	#define CRC_GPOLY_HIGH_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1018	#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	1019
Pawel Zarembski	0:01f31e923fe2	1020	/! @name GPOLYLL - CRC_GPOLYLL register. /
Pawel Zarembski	0:01f31e923fe2	1021	#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1022	#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1023	#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
Pawel Zarembski	0:01f31e923fe2	1024
Pawel Zarembski	0:01f31e923fe2	1025	/! @name GPOLYLU - CRC_GPOLYLU register. /
Pawel Zarembski	0:01f31e923fe2	1026	#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1027	#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1028	#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
Pawel Zarembski	0:01f31e923fe2	1029
Pawel Zarembski	0:01f31e923fe2	1030	/! @name GPOLYHL - CRC_GPOLYHL register. /
Pawel Zarembski	0:01f31e923fe2	1031	#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1032	#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1033	#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
Pawel Zarembski	0:01f31e923fe2	1034
Pawel Zarembski	0:01f31e923fe2	1035	/! @name GPOLYHU - CRC_GPOLYHU register. /
Pawel Zarembski	0:01f31e923fe2	1036	#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1037	#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1038	#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
Pawel Zarembski	0:01f31e923fe2	1039
Pawel Zarembski	0:01f31e923fe2	1040	/! @name CTRL - CRC Control Register /
Pawel Zarembski	0:01f31e923fe2	1041	#define CRC_CTRL_TCRC_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	1042	#define CRC_CTRL_TCRC_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1043	#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
Pawel Zarembski	0:01f31e923fe2	1044	#define CRC_CTRL_WAS_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	1045	#define CRC_CTRL_WAS_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	1046	#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
Pawel Zarembski	0:01f31e923fe2	1047	#define CRC_CTRL_FXOR_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	1048	#define CRC_CTRL_FXOR_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	1049	#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
Pawel Zarembski	0:01f31e923fe2	1050	#define CRC_CTRL_TOTR_MASK (0x30000000U)
Pawel Zarembski	0:01f31e923fe2	1051	#define CRC_CTRL_TOTR_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1052	#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
Pawel Zarembski	0:01f31e923fe2	1053	#define CRC_CTRL_TOT_MASK (0xC0000000U)
Pawel Zarembski	0:01f31e923fe2	1054	#define CRC_CTRL_TOT_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1055	#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
Pawel Zarembski	0:01f31e923fe2	1056
Pawel Zarembski	0:01f31e923fe2	1057	/! @name CTRLHU - CRC_CTRLHU register. /
Pawel Zarembski	0:01f31e923fe2	1058	#define CRC_CTRLHU_TCRC_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1059	#define CRC_CTRLHU_TCRC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1060	#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
Pawel Zarembski	0:01f31e923fe2	1061	#define CRC_CTRLHU_WAS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1062	#define CRC_CTRLHU_WAS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1063	#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
Pawel Zarembski	0:01f31e923fe2	1064	#define CRC_CTRLHU_FXOR_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1065	#define CRC_CTRLHU_FXOR_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1066	#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
Pawel Zarembski	0:01f31e923fe2	1067	#define CRC_CTRLHU_TOTR_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	1068	#define CRC_CTRLHU_TOTR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1069	#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
Pawel Zarembski	0:01f31e923fe2	1070	#define CRC_CTRLHU_TOT_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	1071	#define CRC_CTRLHU_TOT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1072	#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
Pawel Zarembski	0:01f31e923fe2	1073
Pawel Zarembski	0:01f31e923fe2	1074
Pawel Zarembski	0:01f31e923fe2	1075	/*!
Pawel Zarembski	0:01f31e923fe2	1076	* @}
Pawel Zarembski	0:01f31e923fe2	1077	/ / end of group CRC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1078
Pawel Zarembski	0:01f31e923fe2	1079
Pawel Zarembski	0:01f31e923fe2	1080	/* CRC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1081	/** Peripheral CRC base address */
Pawel Zarembski	0:01f31e923fe2	1082	#define CRC_BASE (0x40032000u)
Pawel Zarembski	0:01f31e923fe2	1083	/** Peripheral CRC base pointer */
Pawel Zarembski	0:01f31e923fe2	1084	#define CRC0 ((CRC_Type *)CRC_BASE)
Pawel Zarembski	0:01f31e923fe2	1085	/** Array initializer of CRC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1086	#define CRC_BASE_ADDRS { CRC_BASE }
Pawel Zarembski	0:01f31e923fe2	1087	/** Array initializer of CRC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1088	#define CRC_BASE_PTRS { CRC0 }
Pawel Zarembski	0:01f31e923fe2	1089
Pawel Zarembski	0:01f31e923fe2	1090	/*!
Pawel Zarembski	0:01f31e923fe2	1091	* @}
Pawel Zarembski	0:01f31e923fe2	1092	/ / end of group CRC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1093
Pawel Zarembski	0:01f31e923fe2	1094
Pawel Zarembski	0:01f31e923fe2	1095	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1096	-- DMA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1097	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1098
Pawel Zarembski	0:01f31e923fe2	1099	/*!
Pawel Zarembski	0:01f31e923fe2	1100	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1101	* @{
Pawel Zarembski	0:01f31e923fe2	1102	*/
Pawel Zarembski	0:01f31e923fe2	1103
Pawel Zarembski	0:01f31e923fe2	1104	/** DMA - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1105	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1106	__IO uint32_t CR; /*< Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1107	__I uint32_t ES; /*< Error Status Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1108	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1109	__IO uint32_t ERQ; /*< Enable Request Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1110	uint8_t RESERVED_1[4];
Pawel Zarembski	0:01f31e923fe2	1111	__IO uint32_t EEI; /*< Enable Error Interrupt Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	1112	__O uint8_t CEEI; /*< Clear Enable Error Interrupt Register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	1113	__O uint8_t SEEI; /*< Set Enable Error Interrupt Register, offset: 0x19 /
Pawel Zarembski	0:01f31e923fe2	1114	__O uint8_t CERQ; /*< Clear Enable Request Register, offset: 0x1A /
Pawel Zarembski	0:01f31e923fe2	1115	__O uint8_t SERQ; /*< Set Enable Request Register, offset: 0x1B /
Pawel Zarembski	0:01f31e923fe2	1116	__O uint8_t CDNE; /*< Clear DONE Status Bit Register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	1117	__O uint8_t SSRT; /*< Set START Bit Register, offset: 0x1D /
Pawel Zarembski	0:01f31e923fe2	1118	__O uint8_t CERR; /*< Clear Error Register, offset: 0x1E /
Pawel Zarembski	0:01f31e923fe2	1119	__O uint8_t CINT; /*< Clear Interrupt Request Register, offset: 0x1F /
Pawel Zarembski	0:01f31e923fe2	1120	uint8_t RESERVED_2[4];
Pawel Zarembski	0:01f31e923fe2	1121	__IO uint32_t INT; /*< Interrupt Request Register, offset: 0x24 /
Pawel Zarembski	0:01f31e923fe2	1122	uint8_t RESERVED_3[4];
Pawel Zarembski	0:01f31e923fe2	1123	__IO uint32_t ERR; /*< Error Register, offset: 0x2C /
Pawel Zarembski	0:01f31e923fe2	1124	uint8_t RESERVED_4[4];
Pawel Zarembski	0:01f31e923fe2	1125	__IO uint32_t HRS; /*< Hardware Request Status Register, offset: 0x34 /
Pawel Zarembski	0:01f31e923fe2	1126	uint8_t RESERVED_5[200];
Pawel Zarembski	0:01f31e923fe2	1127	__IO uint8_t DCHPRI3; /*< Channel n Priority Register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	1128	__IO uint8_t DCHPRI2; /*< Channel n Priority Register, offset: 0x101 /
Pawel Zarembski	0:01f31e923fe2	1129	__IO uint8_t DCHPRI1; /*< Channel n Priority Register, offset: 0x102 /
Pawel Zarembski	0:01f31e923fe2	1130	__IO uint8_t DCHPRI0; /*< Channel n Priority Register, offset: 0x103 /
Pawel Zarembski	0:01f31e923fe2	1131	uint8_t RESERVED_6[3836];
Pawel Zarembski	0:01f31e923fe2	1132	struct { /* offset: 0x1000, array step: 0x20 */
Pawel Zarembski	0:01f31e923fe2	1133	__IO uint32_t SADDR; /*< TCD Source Address, array offset: 0x1000, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1134	__IO uint16_t SOFF; /*< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1135	__IO uint16_t ATTR; /*< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1136	union { /* offset: 0x1008, array step: 0x20 */
Pawel Zarembski	0:01f31e923fe2	1137	__IO uint32_t NBYTES_MLNO; /*< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1138	__IO uint32_t NBYTES_MLOFFNO; /*< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1139	__IO uint32_t NBYTES_MLOFFYES; /*< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1140	};
Pawel Zarembski	0:01f31e923fe2	1141	__IO uint32_t SLAST; /*< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1142	__IO uint32_t DADDR; /*< TCD Destination Address, array offset: 0x1010, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1143	__IO uint16_t DOFF; /*< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1144	union { /* offset: 0x1016, array step: 0x20 */
Pawel Zarembski	0:01f31e923fe2	1145	__IO uint16_t CITER_ELINKNO; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1146	__IO uint16_t CITER_ELINKYES; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1147	};
Pawel Zarembski	0:01f31e923fe2	1148	__IO uint32_t DLAST_SGA; /*< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1149	__IO uint16_t CSR; /*< TCD Control and Status, array offset: 0x101C, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1150	union { /* offset: 0x101E, array step: 0x20 */
Pawel Zarembski	0:01f31e923fe2	1151	__IO uint16_t BITER_ELINKNO; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1152	__IO uint16_t BITER_ELINKYES; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 /
Pawel Zarembski	0:01f31e923fe2	1153	};
Pawel Zarembski	0:01f31e923fe2	1154	} TCD[4];
Pawel Zarembski	0:01f31e923fe2	1155	} DMA_Type;
Pawel Zarembski	0:01f31e923fe2	1156
Pawel Zarembski	0:01f31e923fe2	1157	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1158	-- DMA Register Masks
Pawel Zarembski	0:01f31e923fe2	1159	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1160
Pawel Zarembski	0:01f31e923fe2	1161	/*!
Pawel Zarembski	0:01f31e923fe2	1162	* @addtogroup DMA_Register_Masks DMA Register Masks
Pawel Zarembski	0:01f31e923fe2	1163	* @{
Pawel Zarembski	0:01f31e923fe2	1164	*/
Pawel Zarembski	0:01f31e923fe2	1165
Pawel Zarembski	0:01f31e923fe2	1166	/! @name CR - Control Register /
Pawel Zarembski	0:01f31e923fe2	1167	#define DMA_CR_EDBG_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1168	#define DMA_CR_EDBG_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1169	#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
Pawel Zarembski	0:01f31e923fe2	1170	#define DMA_CR_ERCA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1171	#define DMA_CR_ERCA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1172	#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
Pawel Zarembski	0:01f31e923fe2	1173	#define DMA_CR_HOE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1174	#define DMA_CR_HOE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1175	#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1176	#define DMA_CR_HALT_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1177	#define DMA_CR_HALT_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1178	#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
Pawel Zarembski	0:01f31e923fe2	1179	#define DMA_CR_CLM_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1180	#define DMA_CR_CLM_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1181	#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
Pawel Zarembski	0:01f31e923fe2	1182	#define DMA_CR_EMLM_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1183	#define DMA_CR_EMLM_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1184	#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
Pawel Zarembski	0:01f31e923fe2	1185	#define DMA_CR_ECX_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1186	#define DMA_CR_ECX_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1187	#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
Pawel Zarembski	0:01f31e923fe2	1188	#define DMA_CR_CX_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	1189	#define DMA_CR_CX_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	1190	#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
Pawel Zarembski	0:01f31e923fe2	1191
Pawel Zarembski	0:01f31e923fe2	1192	/! @name ES - Error Status Register /
Pawel Zarembski	0:01f31e923fe2	1193	#define DMA_ES_DBE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1194	#define DMA_ES_DBE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1195	#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
Pawel Zarembski	0:01f31e923fe2	1196	#define DMA_ES_SBE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1197	#define DMA_ES_SBE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1198	#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
Pawel Zarembski	0:01f31e923fe2	1199	#define DMA_ES_SGE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1200	#define DMA_ES_SGE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1201	#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
Pawel Zarembski	0:01f31e923fe2	1202	#define DMA_ES_NCE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1203	#define DMA_ES_NCE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1204	#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1205	#define DMA_ES_DOE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1206	#define DMA_ES_DOE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1207	#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1208	#define DMA_ES_DAE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1209	#define DMA_ES_DAE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1210	#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
Pawel Zarembski	0:01f31e923fe2	1211	#define DMA_ES_SOE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1212	#define DMA_ES_SOE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1213	#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1214	#define DMA_ES_SAE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1215	#define DMA_ES_SAE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1216	#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
Pawel Zarembski	0:01f31e923fe2	1217	#define DMA_ES_ERRCHN_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	1218	#define DMA_ES_ERRCHN_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1219	#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
Pawel Zarembski	0:01f31e923fe2	1220	#define DMA_ES_CPE_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	1221	#define DMA_ES_CPE_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	1222	#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
Pawel Zarembski	0:01f31e923fe2	1223	#define DMA_ES_ECX_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1224	#define DMA_ES_ECX_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1225	#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
Pawel Zarembski	0:01f31e923fe2	1226	#define DMA_ES_VLD_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1227	#define DMA_ES_VLD_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1228	#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
Pawel Zarembski	0:01f31e923fe2	1229
Pawel Zarembski	0:01f31e923fe2	1230	/! @name ERQ - Enable Request Register /
Pawel Zarembski	0:01f31e923fe2	1231	#define DMA_ERQ_ERQ0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1232	#define DMA_ERQ_ERQ0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1233	#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
Pawel Zarembski	0:01f31e923fe2	1234	#define DMA_ERQ_ERQ1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1235	#define DMA_ERQ_ERQ1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1236	#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
Pawel Zarembski	0:01f31e923fe2	1237	#define DMA_ERQ_ERQ2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1238	#define DMA_ERQ_ERQ2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1239	#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
Pawel Zarembski	0:01f31e923fe2	1240	#define DMA_ERQ_ERQ3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1241	#define DMA_ERQ_ERQ3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1242	#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
Pawel Zarembski	0:01f31e923fe2	1243
Pawel Zarembski	0:01f31e923fe2	1244	/! @name EEI - Enable Error Interrupt Register /
Pawel Zarembski	0:01f31e923fe2	1245	#define DMA_EEI_EEI0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1246	#define DMA_EEI_EEI0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1247	#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
Pawel Zarembski	0:01f31e923fe2	1248	#define DMA_EEI_EEI1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1249	#define DMA_EEI_EEI1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1250	#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
Pawel Zarembski	0:01f31e923fe2	1251	#define DMA_EEI_EEI2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1252	#define DMA_EEI_EEI2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1253	#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
Pawel Zarembski	0:01f31e923fe2	1254	#define DMA_EEI_EEI3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1255	#define DMA_EEI_EEI3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1256	#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
Pawel Zarembski	0:01f31e923fe2	1257
Pawel Zarembski	0:01f31e923fe2	1258	/! @name CEEI - Clear Enable Error Interrupt Register /
Pawel Zarembski	0:01f31e923fe2	1259	#define DMA_CEEI_CEEI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1260	#define DMA_CEEI_CEEI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1261	#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
Pawel Zarembski	0:01f31e923fe2	1262	#define DMA_CEEI_CAEE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1263	#define DMA_CEEI_CAEE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1264	#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
Pawel Zarembski	0:01f31e923fe2	1265	#define DMA_CEEI_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1266	#define DMA_CEEI_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1267	#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1268
Pawel Zarembski	0:01f31e923fe2	1269	/! @name SEEI - Set Enable Error Interrupt Register /
Pawel Zarembski	0:01f31e923fe2	1270	#define DMA_SEEI_SEEI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1271	#define DMA_SEEI_SEEI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1272	#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
Pawel Zarembski	0:01f31e923fe2	1273	#define DMA_SEEI_SAEE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1274	#define DMA_SEEI_SAEE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1275	#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
Pawel Zarembski	0:01f31e923fe2	1276	#define DMA_SEEI_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1277	#define DMA_SEEI_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1278	#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1279
Pawel Zarembski	0:01f31e923fe2	1280	/! @name CERQ - Clear Enable Request Register /
Pawel Zarembski	0:01f31e923fe2	1281	#define DMA_CERQ_CERQ_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1282	#define DMA_CERQ_CERQ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1283	#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
Pawel Zarembski	0:01f31e923fe2	1284	#define DMA_CERQ_CAER_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1285	#define DMA_CERQ_CAER_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1286	#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
Pawel Zarembski	0:01f31e923fe2	1287	#define DMA_CERQ_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1288	#define DMA_CERQ_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1289	#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1290
Pawel Zarembski	0:01f31e923fe2	1291	/! @name SERQ - Set Enable Request Register /
Pawel Zarembski	0:01f31e923fe2	1292	#define DMA_SERQ_SERQ_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1293	#define DMA_SERQ_SERQ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1294	#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
Pawel Zarembski	0:01f31e923fe2	1295	#define DMA_SERQ_SAER_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1296	#define DMA_SERQ_SAER_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1297	#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
Pawel Zarembski	0:01f31e923fe2	1298	#define DMA_SERQ_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1299	#define DMA_SERQ_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1300	#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1301
Pawel Zarembski	0:01f31e923fe2	1302	/! @name CDNE - Clear DONE Status Bit Register /
Pawel Zarembski	0:01f31e923fe2	1303	#define DMA_CDNE_CDNE_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1304	#define DMA_CDNE_CDNE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1305	#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
Pawel Zarembski	0:01f31e923fe2	1306	#define DMA_CDNE_CADN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1307	#define DMA_CDNE_CADN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1308	#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
Pawel Zarembski	0:01f31e923fe2	1309	#define DMA_CDNE_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1310	#define DMA_CDNE_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1311	#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1312
Pawel Zarembski	0:01f31e923fe2	1313	/! @name SSRT - Set START Bit Register /
Pawel Zarembski	0:01f31e923fe2	1314	#define DMA_SSRT_SSRT_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1315	#define DMA_SSRT_SSRT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1316	#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
Pawel Zarembski	0:01f31e923fe2	1317	#define DMA_SSRT_SAST_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1318	#define DMA_SSRT_SAST_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1319	#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
Pawel Zarembski	0:01f31e923fe2	1320	#define DMA_SSRT_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1321	#define DMA_SSRT_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1322	#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1323
Pawel Zarembski	0:01f31e923fe2	1324	/! @name CERR - Clear Error Register /
Pawel Zarembski	0:01f31e923fe2	1325	#define DMA_CERR_CERR_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1326	#define DMA_CERR_CERR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1327	#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
Pawel Zarembski	0:01f31e923fe2	1328	#define DMA_CERR_CAEI_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1329	#define DMA_CERR_CAEI_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1330	#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
Pawel Zarembski	0:01f31e923fe2	1331	#define DMA_CERR_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1332	#define DMA_CERR_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1333	#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1334
Pawel Zarembski	0:01f31e923fe2	1335	/! @name CINT - Clear Interrupt Request Register /
Pawel Zarembski	0:01f31e923fe2	1336	#define DMA_CINT_CINT_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1337	#define DMA_CINT_CINT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1338	#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
Pawel Zarembski	0:01f31e923fe2	1339	#define DMA_CINT_CAIR_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1340	#define DMA_CINT_CAIR_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1341	#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
Pawel Zarembski	0:01f31e923fe2	1342	#define DMA_CINT_NOP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1343	#define DMA_CINT_NOP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1344	#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
Pawel Zarembski	0:01f31e923fe2	1345
Pawel Zarembski	0:01f31e923fe2	1346	/! @name INT - Interrupt Request Register /
Pawel Zarembski	0:01f31e923fe2	1347	#define DMA_INT_INT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1348	#define DMA_INT_INT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1349	#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
Pawel Zarembski	0:01f31e923fe2	1350	#define DMA_INT_INT1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1351	#define DMA_INT_INT1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1352	#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
Pawel Zarembski	0:01f31e923fe2	1353	#define DMA_INT_INT2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1354	#define DMA_INT_INT2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1355	#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
Pawel Zarembski	0:01f31e923fe2	1356	#define DMA_INT_INT3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1357	#define DMA_INT_INT3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1358	#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
Pawel Zarembski	0:01f31e923fe2	1359
Pawel Zarembski	0:01f31e923fe2	1360	/! @name ERR - Error Register /
Pawel Zarembski	0:01f31e923fe2	1361	#define DMA_ERR_ERR0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1362	#define DMA_ERR_ERR0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1363	#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
Pawel Zarembski	0:01f31e923fe2	1364	#define DMA_ERR_ERR1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1365	#define DMA_ERR_ERR1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1366	#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
Pawel Zarembski	0:01f31e923fe2	1367	#define DMA_ERR_ERR2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1368	#define DMA_ERR_ERR2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1369	#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
Pawel Zarembski	0:01f31e923fe2	1370	#define DMA_ERR_ERR3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1371	#define DMA_ERR_ERR3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1372	#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
Pawel Zarembski	0:01f31e923fe2	1373
Pawel Zarembski	0:01f31e923fe2	1374	/! @name HRS - Hardware Request Status Register /
Pawel Zarembski	0:01f31e923fe2	1375	#define DMA_HRS_HRS0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1376	#define DMA_HRS_HRS0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1377	#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
Pawel Zarembski	0:01f31e923fe2	1378	#define DMA_HRS_HRS1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1379	#define DMA_HRS_HRS1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1380	#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
Pawel Zarembski	0:01f31e923fe2	1381	#define DMA_HRS_HRS2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1382	#define DMA_HRS_HRS2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1383	#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
Pawel Zarembski	0:01f31e923fe2	1384	#define DMA_HRS_HRS3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1385	#define DMA_HRS_HRS3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1386	#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
Pawel Zarembski	0:01f31e923fe2	1387
Pawel Zarembski	0:01f31e923fe2	1388	/! @name DCHPRI3 - Channel n Priority Register /
Pawel Zarembski	0:01f31e923fe2	1389	#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1390	#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1391	#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
Pawel Zarembski	0:01f31e923fe2	1392	#define DMA_DCHPRI3_DPA_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1393	#define DMA_DCHPRI3_DPA_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1394	#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
Pawel Zarembski	0:01f31e923fe2	1395	#define DMA_DCHPRI3_ECP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1396	#define DMA_DCHPRI3_ECP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1397	#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
Pawel Zarembski	0:01f31e923fe2	1398
Pawel Zarembski	0:01f31e923fe2	1399	/! @name DCHPRI2 - Channel n Priority Register /
Pawel Zarembski	0:01f31e923fe2	1400	#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1401	#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1402	#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
Pawel Zarembski	0:01f31e923fe2	1403	#define DMA_DCHPRI2_DPA_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1404	#define DMA_DCHPRI2_DPA_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1405	#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
Pawel Zarembski	0:01f31e923fe2	1406	#define DMA_DCHPRI2_ECP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1407	#define DMA_DCHPRI2_ECP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1408	#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
Pawel Zarembski	0:01f31e923fe2	1409
Pawel Zarembski	0:01f31e923fe2	1410	/! @name DCHPRI1 - Channel n Priority Register /
Pawel Zarembski	0:01f31e923fe2	1411	#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1412	#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1413	#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
Pawel Zarembski	0:01f31e923fe2	1414	#define DMA_DCHPRI1_DPA_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1415	#define DMA_DCHPRI1_DPA_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1416	#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
Pawel Zarembski	0:01f31e923fe2	1417	#define DMA_DCHPRI1_ECP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1418	#define DMA_DCHPRI1_ECP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1419	#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
Pawel Zarembski	0:01f31e923fe2	1420
Pawel Zarembski	0:01f31e923fe2	1421	/! @name DCHPRI0 - Channel n Priority Register /
Pawel Zarembski	0:01f31e923fe2	1422	#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1423	#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1424	#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
Pawel Zarembski	0:01f31e923fe2	1425	#define DMA_DCHPRI0_DPA_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1426	#define DMA_DCHPRI0_DPA_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1427	#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
Pawel Zarembski	0:01f31e923fe2	1428	#define DMA_DCHPRI0_ECP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1429	#define DMA_DCHPRI0_ECP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1430	#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
Pawel Zarembski	0:01f31e923fe2	1431
Pawel Zarembski	0:01f31e923fe2	1432	/! @name SADDR - TCD Source Address /
Pawel Zarembski	0:01f31e923fe2	1433	#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1434	#define DMA_SADDR_SADDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1435	#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
Pawel Zarembski	0:01f31e923fe2	1436
Pawel Zarembski	0:01f31e923fe2	1437	/* The count of DMA_SADDR */
Pawel Zarembski	0:01f31e923fe2	1438	#define DMA_SADDR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1439
Pawel Zarembski	0:01f31e923fe2	1440	/! @name SOFF - TCD Signed Source Address Offset /
Pawel Zarembski	0:01f31e923fe2	1441	#define DMA_SOFF_SOFF_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	1442	#define DMA_SOFF_SOFF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1443	#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
Pawel Zarembski	0:01f31e923fe2	1444
Pawel Zarembski	0:01f31e923fe2	1445	/* The count of DMA_SOFF */
Pawel Zarembski	0:01f31e923fe2	1446	#define DMA_SOFF_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1447
Pawel Zarembski	0:01f31e923fe2	1448	/! @name ATTR - TCD Transfer Attributes /
Pawel Zarembski	0:01f31e923fe2	1449	#define DMA_ATTR_DSIZE_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	1450	#define DMA_ATTR_DSIZE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1451	#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	1452	#define DMA_ATTR_DMOD_MASK (0xF8U)
Pawel Zarembski	0:01f31e923fe2	1453	#define DMA_ATTR_DMOD_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1454	#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	1455	#define DMA_ATTR_SSIZE_MASK (0x700U)
Pawel Zarembski	0:01f31e923fe2	1456	#define DMA_ATTR_SSIZE_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1457	#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	1458	#define DMA_ATTR_SMOD_MASK (0xF800U)
Pawel Zarembski	0:01f31e923fe2	1459	#define DMA_ATTR_SMOD_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	1460	#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	1461
Pawel Zarembski	0:01f31e923fe2	1462	/* The count of DMA_ATTR */
Pawel Zarembski	0:01f31e923fe2	1463	#define DMA_ATTR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1464
Pawel Zarembski	0:01f31e923fe2	1465	/! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) /
Pawel Zarembski	0:01f31e923fe2	1466	#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1467	#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1468	#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
Pawel Zarembski	0:01f31e923fe2	1469
Pawel Zarembski	0:01f31e923fe2	1470	/* The count of DMA_NBYTES_MLNO */
Pawel Zarembski	0:01f31e923fe2	1471	#define DMA_NBYTES_MLNO_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1472
Pawel Zarembski	0:01f31e923fe2	1473	/! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) /
Pawel Zarembski	0:01f31e923fe2	1474	#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1475	#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1476	#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
Pawel Zarembski	0:01f31e923fe2	1477	#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	1478	#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1479	#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1480	#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1481	#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1482	#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1483
Pawel Zarembski	0:01f31e923fe2	1484	/* The count of DMA_NBYTES_MLOFFNO */
Pawel Zarembski	0:01f31e923fe2	1485	#define DMA_NBYTES_MLOFFNO_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1486
Pawel Zarembski	0:01f31e923fe2	1487	/! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) /
Pawel Zarembski	0:01f31e923fe2	1488	#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	1489	#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1490	#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
Pawel Zarembski	0:01f31e923fe2	1491	#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
Pawel Zarembski	0:01f31e923fe2	1492	#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	1493	#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
Pawel Zarembski	0:01f31e923fe2	1494	#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	1495	#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1496	#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1497	#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1498	#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1499	#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1500
Pawel Zarembski	0:01f31e923fe2	1501	/* The count of DMA_NBYTES_MLOFFYES */
Pawel Zarembski	0:01f31e923fe2	1502	#define DMA_NBYTES_MLOFFYES_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1503
Pawel Zarembski	0:01f31e923fe2	1504	/! @name SLAST - TCD Last Source Address Adjustment /
Pawel Zarembski	0:01f31e923fe2	1505	#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1506	#define DMA_SLAST_SLAST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1507	#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
Pawel Zarembski	0:01f31e923fe2	1508
Pawel Zarembski	0:01f31e923fe2	1509	/* The count of DMA_SLAST */
Pawel Zarembski	0:01f31e923fe2	1510	#define DMA_SLAST_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1511
Pawel Zarembski	0:01f31e923fe2	1512	/! @name DADDR - TCD Destination Address /
Pawel Zarembski	0:01f31e923fe2	1513	#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1514	#define DMA_DADDR_DADDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1515	#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
Pawel Zarembski	0:01f31e923fe2	1516
Pawel Zarembski	0:01f31e923fe2	1517	/* The count of DMA_DADDR */
Pawel Zarembski	0:01f31e923fe2	1518	#define DMA_DADDR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1519
Pawel Zarembski	0:01f31e923fe2	1520	/! @name DOFF - TCD Signed Destination Address Offset /
Pawel Zarembski	0:01f31e923fe2	1521	#define DMA_DOFF_DOFF_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	1522	#define DMA_DOFF_DOFF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1523	#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
Pawel Zarembski	0:01f31e923fe2	1524
Pawel Zarembski	0:01f31e923fe2	1525	/* The count of DMA_DOFF */
Pawel Zarembski	0:01f31e923fe2	1526	#define DMA_DOFF_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1527
Pawel Zarembski	0:01f31e923fe2	1528	/! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) /
Pawel Zarembski	0:01f31e923fe2	1529	#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
Pawel Zarembski	0:01f31e923fe2	1530	#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1531	#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
Pawel Zarembski	0:01f31e923fe2	1532	#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	1533	#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	1534	#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
Pawel Zarembski	0:01f31e923fe2	1535
Pawel Zarembski	0:01f31e923fe2	1536	/* The count of DMA_CITER_ELINKNO */
Pawel Zarembski	0:01f31e923fe2	1537	#define DMA_CITER_ELINKNO_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1538
Pawel Zarembski	0:01f31e923fe2	1539	/! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) /
Pawel Zarembski	0:01f31e923fe2	1540	#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	1541	#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1542	#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
Pawel Zarembski	0:01f31e923fe2	1543	#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
Pawel Zarembski	0:01f31e923fe2	1544	#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	1545	#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
Pawel Zarembski	0:01f31e923fe2	1546	#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	1547	#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	1548	#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
Pawel Zarembski	0:01f31e923fe2	1549
Pawel Zarembski	0:01f31e923fe2	1550	/* The count of DMA_CITER_ELINKYES */
Pawel Zarembski	0:01f31e923fe2	1551	#define DMA_CITER_ELINKYES_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1552
Pawel Zarembski	0:01f31e923fe2	1553	/! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address /
Pawel Zarembski	0:01f31e923fe2	1554	#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1555	#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1556	#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
Pawel Zarembski	0:01f31e923fe2	1557
Pawel Zarembski	0:01f31e923fe2	1558	/* The count of DMA_DLAST_SGA */
Pawel Zarembski	0:01f31e923fe2	1559	#define DMA_DLAST_SGA_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1560
Pawel Zarembski	0:01f31e923fe2	1561	/! @name CSR - TCD Control and Status /
Pawel Zarembski	0:01f31e923fe2	1562	#define DMA_CSR_START_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1563	#define DMA_CSR_START_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1564	#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
Pawel Zarembski	0:01f31e923fe2	1565	#define DMA_CSR_INTMAJOR_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1566	#define DMA_CSR_INTMAJOR_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1567	#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
Pawel Zarembski	0:01f31e923fe2	1568	#define DMA_CSR_INTHALF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1569	#define DMA_CSR_INTHALF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1570	#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
Pawel Zarembski	0:01f31e923fe2	1571	#define DMA_CSR_DREQ_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1572	#define DMA_CSR_DREQ_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1573	#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	1574	#define DMA_CSR_ESG_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1575	#define DMA_CSR_ESG_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1576	#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
Pawel Zarembski	0:01f31e923fe2	1577	#define DMA_CSR_MAJORELINK_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1578	#define DMA_CSR_MAJORELINK_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1579	#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
Pawel Zarembski	0:01f31e923fe2	1580	#define DMA_CSR_ACTIVE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1581	#define DMA_CSR_ACTIVE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1582	#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
Pawel Zarembski	0:01f31e923fe2	1583	#define DMA_CSR_DONE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1584	#define DMA_CSR_DONE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1585	#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
Pawel Zarembski	0:01f31e923fe2	1586	#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	1587	#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1588	#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
Pawel Zarembski	0:01f31e923fe2	1589	#define DMA_CSR_BWC_MASK (0xC000U)
Pawel Zarembski	0:01f31e923fe2	1590	#define DMA_CSR_BWC_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	1591	#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
Pawel Zarembski	0:01f31e923fe2	1592
Pawel Zarembski	0:01f31e923fe2	1593	/* The count of DMA_CSR */
Pawel Zarembski	0:01f31e923fe2	1594	#define DMA_CSR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1595
Pawel Zarembski	0:01f31e923fe2	1596	/! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) /
Pawel Zarembski	0:01f31e923fe2	1597	#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
Pawel Zarembski	0:01f31e923fe2	1598	#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1599	#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
Pawel Zarembski	0:01f31e923fe2	1600	#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	1601	#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	1602	#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
Pawel Zarembski	0:01f31e923fe2	1603
Pawel Zarembski	0:01f31e923fe2	1604	/* The count of DMA_BITER_ELINKNO */
Pawel Zarembski	0:01f31e923fe2	1605	#define DMA_BITER_ELINKNO_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1606
Pawel Zarembski	0:01f31e923fe2	1607	/! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) /
Pawel Zarembski	0:01f31e923fe2	1608	#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	1609	#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1610	#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
Pawel Zarembski	0:01f31e923fe2	1611	#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
Pawel Zarembski	0:01f31e923fe2	1612	#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	1613	#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
Pawel Zarembski	0:01f31e923fe2	1614	#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	1615	#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	1616	#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
Pawel Zarembski	0:01f31e923fe2	1617
Pawel Zarembski	0:01f31e923fe2	1618	/* The count of DMA_BITER_ELINKYES */
Pawel Zarembski	0:01f31e923fe2	1619	#define DMA_BITER_ELINKYES_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1620
Pawel Zarembski	0:01f31e923fe2	1621
Pawel Zarembski	0:01f31e923fe2	1622	/*!
Pawel Zarembski	0:01f31e923fe2	1623	* @}
Pawel Zarembski	0:01f31e923fe2	1624	/ / end of group DMA_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1625
Pawel Zarembski	0:01f31e923fe2	1626
Pawel Zarembski	0:01f31e923fe2	1627	/* DMA - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1628	/** Peripheral DMA base address */
Pawel Zarembski	0:01f31e923fe2	1629	#define DMA_BASE (0x40008000u)
Pawel Zarembski	0:01f31e923fe2	1630	/** Peripheral DMA base pointer */
Pawel Zarembski	0:01f31e923fe2	1631	#define DMA0 ((DMA_Type *)DMA_BASE)
Pawel Zarembski	0:01f31e923fe2	1632	/** Array initializer of DMA peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1633	#define DMA_BASE_ADDRS { DMA_BASE }
Pawel Zarembski	0:01f31e923fe2	1634	/** Array initializer of DMA peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1635	#define DMA_BASE_PTRS { DMA0 }
Pawel Zarembski	0:01f31e923fe2	1636	/** Interrupt vectors for the DMA peripheral type */
Pawel Zarembski	0:01f31e923fe2	1637	#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
Pawel Zarembski	0:01f31e923fe2	1638	#define DMA_ERROR_IRQS { DMA_Error_IRQn }
Pawel Zarembski	0:01f31e923fe2	1639
Pawel Zarembski	0:01f31e923fe2	1640	/*!
Pawel Zarembski	0:01f31e923fe2	1641	* @}
Pawel Zarembski	0:01f31e923fe2	1642	/ / end of group DMA_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1643
Pawel Zarembski	0:01f31e923fe2	1644
Pawel Zarembski	0:01f31e923fe2	1645	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1646	-- DMAMUX Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1647	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1648
Pawel Zarembski	0:01f31e923fe2	1649	/*!
Pawel Zarembski	0:01f31e923fe2	1650	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1651	* @{
Pawel Zarembski	0:01f31e923fe2	1652	*/
Pawel Zarembski	0:01f31e923fe2	1653
Pawel Zarembski	0:01f31e923fe2	1654	/** DMAMUX - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1655	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1656	__IO uint8_t CHCFG[4]; /*< Channel Configuration Register, array offset: 0x0, array step: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1657	} DMAMUX_Type;
Pawel Zarembski	0:01f31e923fe2	1658
Pawel Zarembski	0:01f31e923fe2	1659	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1660	-- DMAMUX Register Masks
Pawel Zarembski	0:01f31e923fe2	1661	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1662
Pawel Zarembski	0:01f31e923fe2	1663	/*!
Pawel Zarembski	0:01f31e923fe2	1664	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Pawel Zarembski	0:01f31e923fe2	1665	* @{
Pawel Zarembski	0:01f31e923fe2	1666	*/
Pawel Zarembski	0:01f31e923fe2	1667
Pawel Zarembski	0:01f31e923fe2	1668	/! @name CHCFG - Channel Configuration Register /
Pawel Zarembski	0:01f31e923fe2	1669	#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	1670	#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1671	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1672	#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1673	#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1674	#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	1675	#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1676	#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1677	#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
Pawel Zarembski	0:01f31e923fe2	1678
Pawel Zarembski	0:01f31e923fe2	1679	/* The count of DMAMUX_CHCFG */
Pawel Zarembski	0:01f31e923fe2	1680	#define DMAMUX_CHCFG_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1681
Pawel Zarembski	0:01f31e923fe2	1682
Pawel Zarembski	0:01f31e923fe2	1683	/*!
Pawel Zarembski	0:01f31e923fe2	1684	* @}
Pawel Zarembski	0:01f31e923fe2	1685	/ / end of group DMAMUX_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1686
Pawel Zarembski	0:01f31e923fe2	1687
Pawel Zarembski	0:01f31e923fe2	1688	/* DMAMUX - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1689	/** Peripheral DMAMUX base address */
Pawel Zarembski	0:01f31e923fe2	1690	#define DMAMUX_BASE (0x40021000u)
Pawel Zarembski	0:01f31e923fe2	1691	/** Peripheral DMAMUX base pointer */
Pawel Zarembski	0:01f31e923fe2	1692	#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
Pawel Zarembski	0:01f31e923fe2	1693	/** Array initializer of DMAMUX peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1694	#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
Pawel Zarembski	0:01f31e923fe2	1695	/** Array initializer of DMAMUX peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1696	#define DMAMUX_BASE_PTRS { DMAMUX }
Pawel Zarembski	0:01f31e923fe2	1697
Pawel Zarembski	0:01f31e923fe2	1698	/*!
Pawel Zarembski	0:01f31e923fe2	1699	* @}
Pawel Zarembski	0:01f31e923fe2	1700	/ / end of group DMAMUX_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1701
Pawel Zarembski	0:01f31e923fe2	1702
Pawel Zarembski	0:01f31e923fe2	1703	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1704	-- EWM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1705	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1706
Pawel Zarembski	0:01f31e923fe2	1707	/*!
Pawel Zarembski	0:01f31e923fe2	1708	* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1709	* @{
Pawel Zarembski	0:01f31e923fe2	1710	*/
Pawel Zarembski	0:01f31e923fe2	1711
Pawel Zarembski	0:01f31e923fe2	1712	/** EWM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1713	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1714	__IO uint8_t CTRL; /*< Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1715	__O uint8_t SERV; /*< Service Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1716	__IO uint8_t CMPL; /*< Compare Low Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	1717	__IO uint8_t CMPH; /*< Compare High Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	1718	} EWM_Type;
Pawel Zarembski	0:01f31e923fe2	1719
Pawel Zarembski	0:01f31e923fe2	1720	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1721	-- EWM Register Masks
Pawel Zarembski	0:01f31e923fe2	1722	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1723
Pawel Zarembski	0:01f31e923fe2	1724	/*!
Pawel Zarembski	0:01f31e923fe2	1725	* @addtogroup EWM_Register_Masks EWM Register Masks
Pawel Zarembski	0:01f31e923fe2	1726	* @{
Pawel Zarembski	0:01f31e923fe2	1727	*/
Pawel Zarembski	0:01f31e923fe2	1728
Pawel Zarembski	0:01f31e923fe2	1729	/! @name CTRL - Control Register /
Pawel Zarembski	0:01f31e923fe2	1730	#define EWM_CTRL_EWMEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1731	#define EWM_CTRL_EWMEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1732	#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1733	#define EWM_CTRL_ASSIN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1734	#define EWM_CTRL_ASSIN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1735	#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
Pawel Zarembski	0:01f31e923fe2	1736	#define EWM_CTRL_INEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1737	#define EWM_CTRL_INEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1738	#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1739	#define EWM_CTRL_INTEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1740	#define EWM_CTRL_INTEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1741	#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1742
Pawel Zarembski	0:01f31e923fe2	1743	/! @name SERV - Service Register /
Pawel Zarembski	0:01f31e923fe2	1744	#define EWM_SERV_SERVICE_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1745	#define EWM_SERV_SERVICE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1746	#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
Pawel Zarembski	0:01f31e923fe2	1747
Pawel Zarembski	0:01f31e923fe2	1748	/! @name CMPL - Compare Low Register /
Pawel Zarembski	0:01f31e923fe2	1749	#define EWM_CMPL_COMPAREL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1750	#define EWM_CMPL_COMPAREL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1751	#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
Pawel Zarembski	0:01f31e923fe2	1752
Pawel Zarembski	0:01f31e923fe2	1753	/! @name CMPH - Compare High Register /
Pawel Zarembski	0:01f31e923fe2	1754	#define EWM_CMPH_COMPAREH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1755	#define EWM_CMPH_COMPAREH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1756	#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
Pawel Zarembski	0:01f31e923fe2	1757
Pawel Zarembski	0:01f31e923fe2	1758
Pawel Zarembski	0:01f31e923fe2	1759	/*!
Pawel Zarembski	0:01f31e923fe2	1760	* @}
Pawel Zarembski	0:01f31e923fe2	1761	/ / end of group EWM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1762
Pawel Zarembski	0:01f31e923fe2	1763
Pawel Zarembski	0:01f31e923fe2	1764	/* EWM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1765	/** Peripheral EWM base address */
Pawel Zarembski	0:01f31e923fe2	1766	#define EWM_BASE (0x40061000u)
Pawel Zarembski	0:01f31e923fe2	1767	/** Peripheral EWM base pointer */
Pawel Zarembski	0:01f31e923fe2	1768	#define EWM ((EWM_Type *)EWM_BASE)
Pawel Zarembski	0:01f31e923fe2	1769	/** Array initializer of EWM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1770	#define EWM_BASE_ADDRS { EWM_BASE }
Pawel Zarembski	0:01f31e923fe2	1771	/** Array initializer of EWM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1772	#define EWM_BASE_PTRS { EWM }
Pawel Zarembski	0:01f31e923fe2	1773	/** Interrupt vectors for the EWM peripheral type */
Pawel Zarembski	0:01f31e923fe2	1774	#define EWM_IRQS { Watchdog_IRQn }
Pawel Zarembski	0:01f31e923fe2	1775
Pawel Zarembski	0:01f31e923fe2	1776	/*!
Pawel Zarembski	0:01f31e923fe2	1777	* @}
Pawel Zarembski	0:01f31e923fe2	1778	/ / end of group EWM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1779
Pawel Zarembski	0:01f31e923fe2	1780
Pawel Zarembski	0:01f31e923fe2	1781	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1782	-- FMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1783	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1784
Pawel Zarembski	0:01f31e923fe2	1785	/*!
Pawel Zarembski	0:01f31e923fe2	1786	* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1787	* @{
Pawel Zarembski	0:01f31e923fe2	1788	*/
Pawel Zarembski	0:01f31e923fe2	1789
Pawel Zarembski	0:01f31e923fe2	1790	/** FMC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1791	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1792	__IO uint32_t PFAPR; /*< Flash Access Protection Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1793	__IO uint32_t PFB0CR; /*< Flash Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1794	uint8_t RESERVED_0[248];
Pawel Zarembski	0:01f31e923fe2	1795	struct { /* offset: 0x100, array step: 0x20 */
Pawel Zarembski	0:01f31e923fe2	1796	__IO uint32_t TAGVD[2]; /*< Cache Tag Storage, array offset: 0x100, array step: index0x20, index20x4 /
Pawel Zarembski	0:01f31e923fe2	1797	uint8_t RESERVED_0[24];
Pawel Zarembski	0:01f31e923fe2	1798	} TAG_WAY[4];
Pawel Zarembski	0:01f31e923fe2	1799	uint8_t RESERVED_1[132];
Pawel Zarembski	0:01f31e923fe2	1800	struct { /* offset: 0x204, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	1801	__IO uint32_t DATAW0S; /*< Cache Data Storage, array offset: 0x204, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1802	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1803	} DATAW0S[2];
Pawel Zarembski	0:01f31e923fe2	1804	uint8_t RESERVED_2[48];
Pawel Zarembski	0:01f31e923fe2	1805	struct { /* offset: 0x244, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	1806	__IO uint32_t DATAW1S; /*< Cache Data Storage, array offset: 0x244, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1807	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1808	} DATAW1S[2];
Pawel Zarembski	0:01f31e923fe2	1809	uint8_t RESERVED_3[48];
Pawel Zarembski	0:01f31e923fe2	1810	struct { /* offset: 0x284, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	1811	__IO uint32_t DATAW2S; /*< Cache Data Storage, array offset: 0x284, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1812	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1813	} DATAW2S[2];
Pawel Zarembski	0:01f31e923fe2	1814	uint8_t RESERVED_4[48];
Pawel Zarembski	0:01f31e923fe2	1815	struct { /* offset: 0x2C4, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	1816	__IO uint32_t DATAW3S; /*< Cache Data Storage, array offset: 0x2C4, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1817	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1818	} DATAW3S[2];
Pawel Zarembski	0:01f31e923fe2	1819	} FMC_Type;
Pawel Zarembski	0:01f31e923fe2	1820
Pawel Zarembski	0:01f31e923fe2	1821	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1822	-- FMC Register Masks
Pawel Zarembski	0:01f31e923fe2	1823	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1824
Pawel Zarembski	0:01f31e923fe2	1825	/*!
Pawel Zarembski	0:01f31e923fe2	1826	* @addtogroup FMC_Register_Masks FMC Register Masks
Pawel Zarembski	0:01f31e923fe2	1827	* @{
Pawel Zarembski	0:01f31e923fe2	1828	*/
Pawel Zarembski	0:01f31e923fe2	1829
Pawel Zarembski	0:01f31e923fe2	1830	/! @name PFAPR - Flash Access Protection Register /
Pawel Zarembski	0:01f31e923fe2	1831	#define FMC_PFAPR_M0AP_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	1832	#define FMC_PFAPR_M0AP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1833	#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
Pawel Zarembski	0:01f31e923fe2	1834	#define FMC_PFAPR_M1AP_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	1835	#define FMC_PFAPR_M1AP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1836	#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
Pawel Zarembski	0:01f31e923fe2	1837	#define FMC_PFAPR_M2AP_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	1838	#define FMC_PFAPR_M2AP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1839	#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
Pawel Zarembski	0:01f31e923fe2	1840	#define FMC_PFAPR_M3AP_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	1841	#define FMC_PFAPR_M3AP_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1842	#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
Pawel Zarembski	0:01f31e923fe2	1843	#define FMC_PFAPR_M0PFD_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1844	#define FMC_PFAPR_M0PFD_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1845	#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
Pawel Zarembski	0:01f31e923fe2	1846	#define FMC_PFAPR_M1PFD_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	1847	#define FMC_PFAPR_M1PFD_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	1848	#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
Pawel Zarembski	0:01f31e923fe2	1849	#define FMC_PFAPR_M2PFD_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	1850	#define FMC_PFAPR_M2PFD_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	1851	#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
Pawel Zarembski	0:01f31e923fe2	1852	#define FMC_PFAPR_M3PFD_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	1853	#define FMC_PFAPR_M3PFD_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	1854	#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
Pawel Zarembski	0:01f31e923fe2	1855
Pawel Zarembski	0:01f31e923fe2	1856	/! @name PFB0CR - Flash Control Register /
Pawel Zarembski	0:01f31e923fe2	1857	#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1858	#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1859	#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
Pawel Zarembski	0:01f31e923fe2	1860	#define FMC_PFB0CR_B0IPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1861	#define FMC_PFB0CR_B0IPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1862	#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
Pawel Zarembski	0:01f31e923fe2	1863	#define FMC_PFB0CR_B0DPE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1864	#define FMC_PFB0CR_B0DPE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1865	#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
Pawel Zarembski	0:01f31e923fe2	1866	#define FMC_PFB0CR_B0ICE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1867	#define FMC_PFB0CR_B0ICE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1868	#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
Pawel Zarembski	0:01f31e923fe2	1869	#define FMC_PFB0CR_B0DCE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1870	#define FMC_PFB0CR_B0DCE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1871	#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1872	#define FMC_PFB0CR_CRC_MASK (0xE0U)
Pawel Zarembski	0:01f31e923fe2	1873	#define FMC_PFB0CR_CRC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1874	#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
Pawel Zarembski	0:01f31e923fe2	1875	#define FMC_PFB0CR_B0MW_MASK (0x60000U)
Pawel Zarembski	0:01f31e923fe2	1876	#define FMC_PFB0CR_B0MW_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	1877	#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
Pawel Zarembski	0:01f31e923fe2	1878	#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	1879	#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	1880	#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
Pawel Zarembski	0:01f31e923fe2	1881	#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
Pawel Zarembski	0:01f31e923fe2	1882	#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	1883	#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
Pawel Zarembski	0:01f31e923fe2	1884	#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	1885	#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1886	#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
Pawel Zarembski	0:01f31e923fe2	1887	#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	1888	#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1889	#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
Pawel Zarembski	0:01f31e923fe2	1890
Pawel Zarembski	0:01f31e923fe2	1891	/! @name TAGVD - Cache Tag Storage /
Pawel Zarembski	0:01f31e923fe2	1892	#define FMC_TAGVD_valid_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1893	#define FMC_TAGVD_valid_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1894	#define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
Pawel Zarembski	0:01f31e923fe2	1895	#define FMC_TAGVD_tag_MASK (0x7FFC0U)
Pawel Zarembski	0:01f31e923fe2	1896	#define FMC_TAGVD_tag_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1897	#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
Pawel Zarembski	0:01f31e923fe2	1898
Pawel Zarembski	0:01f31e923fe2	1899	/* The count of FMC_TAGVD */
Pawel Zarembski	0:01f31e923fe2	1900	#define FMC_TAGVD_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1901
Pawel Zarembski	0:01f31e923fe2	1902	/* The count of FMC_TAGVD */
Pawel Zarembski	0:01f31e923fe2	1903	#define FMC_TAGVD_COUNT2 (2U)
Pawel Zarembski	0:01f31e923fe2	1904
Pawel Zarembski	0:01f31e923fe2	1905	/! @name DATAW0S - Cache Data Storage /
Pawel Zarembski	0:01f31e923fe2	1906	#define FMC_DATAW0S_data_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1907	#define FMC_DATAW0S_data_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1908	#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW0S_data_SHIFT)) & FMC_DATAW0S_data_MASK)
Pawel Zarembski	0:01f31e923fe2	1909
Pawel Zarembski	0:01f31e923fe2	1910	/* The count of FMC_DATAW0S */
Pawel Zarembski	0:01f31e923fe2	1911	#define FMC_DATAW0S_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	1912
Pawel Zarembski	0:01f31e923fe2	1913	/! @name DATAW1S - Cache Data Storage /
Pawel Zarembski	0:01f31e923fe2	1914	#define FMC_DATAW1S_data_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1915	#define FMC_DATAW1S_data_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1916	#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW1S_data_SHIFT)) & FMC_DATAW1S_data_MASK)
Pawel Zarembski	0:01f31e923fe2	1917
Pawel Zarembski	0:01f31e923fe2	1918	/* The count of FMC_DATAW1S */
Pawel Zarembski	0:01f31e923fe2	1919	#define FMC_DATAW1S_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	1920
Pawel Zarembski	0:01f31e923fe2	1921	/! @name DATAW2S - Cache Data Storage /
Pawel Zarembski	0:01f31e923fe2	1922	#define FMC_DATAW2S_data_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1923	#define FMC_DATAW2S_data_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1924	#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW2S_data_SHIFT)) & FMC_DATAW2S_data_MASK)
Pawel Zarembski	0:01f31e923fe2	1925
Pawel Zarembski	0:01f31e923fe2	1926	/* The count of FMC_DATAW2S */
Pawel Zarembski	0:01f31e923fe2	1927	#define FMC_DATAW2S_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	1928
Pawel Zarembski	0:01f31e923fe2	1929	/! @name DATAW3S - Cache Data Storage /
Pawel Zarembski	0:01f31e923fe2	1930	#define FMC_DATAW3S_data_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1931	#define FMC_DATAW3S_data_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1932	#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW3S_data_SHIFT)) & FMC_DATAW3S_data_MASK)
Pawel Zarembski	0:01f31e923fe2	1933
Pawel Zarembski	0:01f31e923fe2	1934	/* The count of FMC_DATAW3S */
Pawel Zarembski	0:01f31e923fe2	1935	#define FMC_DATAW3S_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	1936
Pawel Zarembski	0:01f31e923fe2	1937
Pawel Zarembski	0:01f31e923fe2	1938	/*!
Pawel Zarembski	0:01f31e923fe2	1939	* @}
Pawel Zarembski	0:01f31e923fe2	1940	/ / end of group FMC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1941
Pawel Zarembski	0:01f31e923fe2	1942
Pawel Zarembski	0:01f31e923fe2	1943	/* FMC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1944	/** Peripheral FMC base address */
Pawel Zarembski	0:01f31e923fe2	1945	#define FMC_BASE (0x4001F000u)
Pawel Zarembski	0:01f31e923fe2	1946	/** Peripheral FMC base pointer */
Pawel Zarembski	0:01f31e923fe2	1947	#define FMC ((FMC_Type *)FMC_BASE)
Pawel Zarembski	0:01f31e923fe2	1948	/** Array initializer of FMC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1949	#define FMC_BASE_ADDRS { FMC_BASE }
Pawel Zarembski	0:01f31e923fe2	1950	/** Array initializer of FMC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1951	#define FMC_BASE_PTRS { FMC }
Pawel Zarembski	0:01f31e923fe2	1952
Pawel Zarembski	0:01f31e923fe2	1953	/*!
Pawel Zarembski	0:01f31e923fe2	1954	* @}
Pawel Zarembski	0:01f31e923fe2	1955	/ / end of group FMC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1956
Pawel Zarembski	0:01f31e923fe2	1957
Pawel Zarembski	0:01f31e923fe2	1958	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1959	-- FTFL Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1960	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1961
Pawel Zarembski	0:01f31e923fe2	1962	/*!
Pawel Zarembski	0:01f31e923fe2	1963	* @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1964	* @{
Pawel Zarembski	0:01f31e923fe2	1965	*/
Pawel Zarembski	0:01f31e923fe2	1966
Pawel Zarembski	0:01f31e923fe2	1967	/** FTFL - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1968	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1969	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1970	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1971	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	1972	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	1973	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1974	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	1975	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	1976	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	1977	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1978	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	1979	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	1980	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	1981	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1982	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	1983	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	1984	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
Pawel Zarembski	0:01f31e923fe2	1985	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	1986	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
Pawel Zarembski	0:01f31e923fe2	1987	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
Pawel Zarembski	0:01f31e923fe2	1988	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
Pawel Zarembski	0:01f31e923fe2	1989	uint8_t RESERVED_0[2];
Pawel Zarembski	0:01f31e923fe2	1990	__IO uint8_t FEPROT; /*< EEPROM Protection Register, offset: 0x16 /
Pawel Zarembski	0:01f31e923fe2	1991	__IO uint8_t FDPROT; /*< Data Flash Protection Register, offset: 0x17 /
Pawel Zarembski	0:01f31e923fe2	1992	} FTFL_Type;
Pawel Zarembski	0:01f31e923fe2	1993
Pawel Zarembski	0:01f31e923fe2	1994	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1995	-- FTFL Register Masks
Pawel Zarembski	0:01f31e923fe2	1996	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1997
Pawel Zarembski	0:01f31e923fe2	1998	/*!
Pawel Zarembski	0:01f31e923fe2	1999	* @addtogroup FTFL_Register_Masks FTFL Register Masks
Pawel Zarembski	0:01f31e923fe2	2000	* @{
Pawel Zarembski	0:01f31e923fe2	2001	*/
Pawel Zarembski	0:01f31e923fe2	2002
Pawel Zarembski	0:01f31e923fe2	2003	/! @name FSTAT - Flash Status Register /
Pawel Zarembski	0:01f31e923fe2	2004	#define FTFL_FSTAT_MGSTAT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2005	#define FTFL_FSTAT_MGSTAT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2006	#define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK)
Pawel Zarembski	0:01f31e923fe2	2007	#define FTFL_FSTAT_FPVIOL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2008	#define FTFL_FSTAT_FPVIOL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2009	#define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK)
Pawel Zarembski	0:01f31e923fe2	2010	#define FTFL_FSTAT_ACCERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2011	#define FTFL_FSTAT_ACCERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2012	#define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK)
Pawel Zarembski	0:01f31e923fe2	2013	#define FTFL_FSTAT_RDCOLERR_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2014	#define FTFL_FSTAT_RDCOLERR_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2015	#define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK)
Pawel Zarembski	0:01f31e923fe2	2016	#define FTFL_FSTAT_CCIF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2017	#define FTFL_FSTAT_CCIF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2018	#define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK)
Pawel Zarembski	0:01f31e923fe2	2019
Pawel Zarembski	0:01f31e923fe2	2020	/! @name FCNFG - Flash Configuration Register /
Pawel Zarembski	0:01f31e923fe2	2021	#define FTFL_FCNFG_EEERDY_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2022	#define FTFL_FCNFG_EEERDY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2023	#define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK)
Pawel Zarembski	0:01f31e923fe2	2024	#define FTFL_FCNFG_RAMRDY_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2025	#define FTFL_FCNFG_RAMRDY_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2026	#define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK)
Pawel Zarembski	0:01f31e923fe2	2027	#define FTFL_FCNFG_PFLSH_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2028	#define FTFL_FCNFG_PFLSH_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2029	#define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK)
Pawel Zarembski	0:01f31e923fe2	2030	#define FTFL_FCNFG_ERSSUSP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2031	#define FTFL_FCNFG_ERSSUSP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2032	#define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK)
Pawel Zarembski	0:01f31e923fe2	2033	#define FTFL_FCNFG_ERSAREQ_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2034	#define FTFL_FCNFG_ERSAREQ_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2035	#define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	2036	#define FTFL_FCNFG_RDCOLLIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2037	#define FTFL_FCNFG_RDCOLLIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2038	#define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2039	#define FTFL_FCNFG_CCIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2040	#define FTFL_FCNFG_CCIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2041	#define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2042
Pawel Zarembski	0:01f31e923fe2	2043	/! @name FSEC - Flash Security Register /
Pawel Zarembski	0:01f31e923fe2	2044	#define FTFL_FSEC_SEC_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2045	#define FTFL_FSEC_SEC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2046	#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK)
Pawel Zarembski	0:01f31e923fe2	2047	#define FTFL_FSEC_FSLACC_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2048	#define FTFL_FSEC_FSLACC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2049	#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK)
Pawel Zarembski	0:01f31e923fe2	2050	#define FTFL_FSEC_MEEN_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2051	#define FTFL_FSEC_MEEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2052	#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2053	#define FTFL_FSEC_KEYEN_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2054	#define FTFL_FSEC_KEYEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2055	#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2056
Pawel Zarembski	0:01f31e923fe2	2057	/! @name FOPT - Flash Option Register /
Pawel Zarembski	0:01f31e923fe2	2058	#define FTFL_FOPT_OPT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2059	#define FTFL_FOPT_OPT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2060	#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK)
Pawel Zarembski	0:01f31e923fe2	2061
Pawel Zarembski	0:01f31e923fe2	2062	/! @name FCCOB3 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2063	#define FTFL_FCCOB3_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2064	#define FTFL_FCCOB3_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2065	#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2066
Pawel Zarembski	0:01f31e923fe2	2067	/! @name FCCOB2 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2068	#define FTFL_FCCOB2_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2069	#define FTFL_FCCOB2_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2070	#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2071
Pawel Zarembski	0:01f31e923fe2	2072	/! @name FCCOB1 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2073	#define FTFL_FCCOB1_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2074	#define FTFL_FCCOB1_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2075	#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2076
Pawel Zarembski	0:01f31e923fe2	2077	/! @name FCCOB0 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2078	#define FTFL_FCCOB0_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2079	#define FTFL_FCCOB0_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2080	#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2081
Pawel Zarembski	0:01f31e923fe2	2082	/! @name FCCOB7 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2083	#define FTFL_FCCOB7_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2084	#define FTFL_FCCOB7_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2085	#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2086
Pawel Zarembski	0:01f31e923fe2	2087	/! @name FCCOB6 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2088	#define FTFL_FCCOB6_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2089	#define FTFL_FCCOB6_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2090	#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2091
Pawel Zarembski	0:01f31e923fe2	2092	/! @name FCCOB5 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2093	#define FTFL_FCCOB5_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2094	#define FTFL_FCCOB5_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2095	#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2096
Pawel Zarembski	0:01f31e923fe2	2097	/! @name FCCOB4 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2098	#define FTFL_FCCOB4_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2099	#define FTFL_FCCOB4_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2100	#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2101
Pawel Zarembski	0:01f31e923fe2	2102	/! @name FCCOBB - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2103	#define FTFL_FCCOBB_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2104	#define FTFL_FCCOBB_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2105	#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2106
Pawel Zarembski	0:01f31e923fe2	2107	/! @name FCCOBA - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2108	#define FTFL_FCCOBA_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2109	#define FTFL_FCCOBA_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2110	#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2111
Pawel Zarembski	0:01f31e923fe2	2112	/! @name FCCOB9 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2113	#define FTFL_FCCOB9_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2114	#define FTFL_FCCOB9_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2115	#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2116
Pawel Zarembski	0:01f31e923fe2	2117	/! @name FCCOB8 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	2118	#define FTFL_FCCOB8_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2119	#define FTFL_FCCOB8_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2120	#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	2121
Pawel Zarembski	0:01f31e923fe2	2122	/! @name FPROT3 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	2123	#define FTFL_FPROT3_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2124	#define FTFL_FPROT3_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2125	#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2126
Pawel Zarembski	0:01f31e923fe2	2127	/! @name FPROT2 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	2128	#define FTFL_FPROT2_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2129	#define FTFL_FPROT2_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2130	#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2131
Pawel Zarembski	0:01f31e923fe2	2132	/! @name FPROT1 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	2133	#define FTFL_FPROT1_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2134	#define FTFL_FPROT1_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2135	#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2136
Pawel Zarembski	0:01f31e923fe2	2137	/! @name FPROT0 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	2138	#define FTFL_FPROT0_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2139	#define FTFL_FPROT0_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2140	#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2141
Pawel Zarembski	0:01f31e923fe2	2142	/! @name FEPROT - EEPROM Protection Register /
Pawel Zarembski	0:01f31e923fe2	2143	#define FTFL_FEPROT_EPROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2144	#define FTFL_FEPROT_EPROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2145	#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2146
Pawel Zarembski	0:01f31e923fe2	2147	/! @name FDPROT - Data Flash Protection Register /
Pawel Zarembski	0:01f31e923fe2	2148	#define FTFL_FDPROT_DPROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2149	#define FTFL_FDPROT_DPROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2150	#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK)
Pawel Zarembski	0:01f31e923fe2	2151
Pawel Zarembski	0:01f31e923fe2	2152
Pawel Zarembski	0:01f31e923fe2	2153	/*!
Pawel Zarembski	0:01f31e923fe2	2154	* @}
Pawel Zarembski	0:01f31e923fe2	2155	/ / end of group FTFL_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2156
Pawel Zarembski	0:01f31e923fe2	2157
Pawel Zarembski	0:01f31e923fe2	2158	/* FTFL - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2159	/** Peripheral FTFL base address */
Pawel Zarembski	0:01f31e923fe2	2160	#define FTFL_BASE (0x40020000u)
Pawel Zarembski	0:01f31e923fe2	2161	/** Peripheral FTFL base pointer */
Pawel Zarembski	0:01f31e923fe2	2162	#define FTFL ((FTFL_Type *)FTFL_BASE)
Pawel Zarembski	0:01f31e923fe2	2163	/** Array initializer of FTFL peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2164	#define FTFL_BASE_ADDRS { FTFL_BASE }
Pawel Zarembski	0:01f31e923fe2	2165	/** Array initializer of FTFL peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2166	#define FTFL_BASE_PTRS { FTFL }
Pawel Zarembski	0:01f31e923fe2	2167	/** Interrupt vectors for the FTFL peripheral type */
Pawel Zarembski	0:01f31e923fe2	2168	#define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn }
Pawel Zarembski	0:01f31e923fe2	2169	#define FTFL_READ_COLLISION_IRQS { Read_Collision_IRQn }
Pawel Zarembski	0:01f31e923fe2	2170
Pawel Zarembski	0:01f31e923fe2	2171	/*!
Pawel Zarembski	0:01f31e923fe2	2172	* @}
Pawel Zarembski	0:01f31e923fe2	2173	/ / end of group FTFL_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2174
Pawel Zarembski	0:01f31e923fe2	2175
Pawel Zarembski	0:01f31e923fe2	2176	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2177	-- FTM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2178	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2179
Pawel Zarembski	0:01f31e923fe2	2180	/*!
Pawel Zarembski	0:01f31e923fe2	2181	* @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2182	* @{
Pawel Zarembski	0:01f31e923fe2	2183	*/
Pawel Zarembski	0:01f31e923fe2	2184
Pawel Zarembski	0:01f31e923fe2	2185	/** FTM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2186	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2187	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2188	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2189	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2190	struct { /* offset: 0xC, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	2191	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2192	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2193	} CONTROLS[8];
Pawel Zarembski	0:01f31e923fe2	2194	__IO uint32_t CNTIN; /*< Counter Initial Value, offset: 0x4C /
Pawel Zarembski	0:01f31e923fe2	2195	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
Pawel Zarembski	0:01f31e923fe2	2196	__IO uint32_t MODE; /*< Features Mode Selection, offset: 0x54 /
Pawel Zarembski	0:01f31e923fe2	2197	__IO uint32_t SYNC; /*< Synchronization, offset: 0x58 /
Pawel Zarembski	0:01f31e923fe2	2198	__IO uint32_t OUTINIT; /*< Initial State for Channels Output, offset: 0x5C /
Pawel Zarembski	0:01f31e923fe2	2199	__IO uint32_t OUTMASK; /*< Output Mask, offset: 0x60 /
Pawel Zarembski	0:01f31e923fe2	2200	__IO uint32_t COMBINE; /*< Function for Linked Channels, offset: 0x64 /
Pawel Zarembski	0:01f31e923fe2	2201	__IO uint32_t DEADTIME; /*< Deadtime Insertion Control, offset: 0x68 /
Pawel Zarembski	0:01f31e923fe2	2202	__IO uint32_t EXTTRIG; /*< FTM External Trigger, offset: 0x6C /
Pawel Zarembski	0:01f31e923fe2	2203	__IO uint32_t POL; /*< Channels Polarity, offset: 0x70 /
Pawel Zarembski	0:01f31e923fe2	2204	__IO uint32_t FMS; /*< Fault Mode Status, offset: 0x74 /
Pawel Zarembski	0:01f31e923fe2	2205	__IO uint32_t FILTER; /*< Input Capture Filter Control, offset: 0x78 /
Pawel Zarembski	0:01f31e923fe2	2206	__IO uint32_t FLTCTRL; /*< Fault Control, offset: 0x7C /
Pawel Zarembski	0:01f31e923fe2	2207	__IO uint32_t QDCTRL; /*< Quadrature Decoder Control and Status, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	2208	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	2209	__IO uint32_t FLTPOL; /*< FTM Fault Input Polarity, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	2210	__IO uint32_t SYNCONF; /*< Synchronization Configuration, offset: 0x8C /
Pawel Zarembski	0:01f31e923fe2	2211	__IO uint32_t INVCTRL; /*< FTM Inverting Control, offset: 0x90 /
Pawel Zarembski	0:01f31e923fe2	2212	__IO uint32_t SWOCTRL; /*< FTM Software Output Control, offset: 0x94 /
Pawel Zarembski	0:01f31e923fe2	2213	__IO uint32_t PWMLOAD; /*< FTM PWM Load, offset: 0x98 /
Pawel Zarembski	0:01f31e923fe2	2214	} FTM_Type;
Pawel Zarembski	0:01f31e923fe2	2215
Pawel Zarembski	0:01f31e923fe2	2216	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2217	-- FTM Register Masks
Pawel Zarembski	0:01f31e923fe2	2218	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2219
Pawel Zarembski	0:01f31e923fe2	2220	/*!
Pawel Zarembski	0:01f31e923fe2	2221	* @addtogroup FTM_Register_Masks FTM Register Masks
Pawel Zarembski	0:01f31e923fe2	2222	* @{
Pawel Zarembski	0:01f31e923fe2	2223	*/
Pawel Zarembski	0:01f31e923fe2	2224
Pawel Zarembski	0:01f31e923fe2	2225	/! @name SC - Status and Control /
Pawel Zarembski	0:01f31e923fe2	2226	#define FTM_SC_PS_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	2227	#define FTM_SC_PS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2228	#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	2229	#define FTM_SC_CLKS_MASK (0x18U)
Pawel Zarembski	0:01f31e923fe2	2230	#define FTM_SC_CLKS_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2231	#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	2232	#define FTM_SC_CPWMS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2233	#define FTM_SC_CPWMS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2234	#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
Pawel Zarembski	0:01f31e923fe2	2235	#define FTM_SC_TOIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2236	#define FTM_SC_TOIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2237	#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2238	#define FTM_SC_TOF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2239	#define FTM_SC_TOF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2240	#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
Pawel Zarembski	0:01f31e923fe2	2241
Pawel Zarembski	0:01f31e923fe2	2242	/! @name CNT - Counter /
Pawel Zarembski	0:01f31e923fe2	2243	#define FTM_CNT_COUNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2244	#define FTM_CNT_COUNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2245	#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
Pawel Zarembski	0:01f31e923fe2	2246
Pawel Zarembski	0:01f31e923fe2	2247	/! @name MOD - Modulo /
Pawel Zarembski	0:01f31e923fe2	2248	#define FTM_MOD_MOD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2249	#define FTM_MOD_MOD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2250	#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
Pawel Zarembski	0:01f31e923fe2	2251
Pawel Zarembski	0:01f31e923fe2	2252	/! @name CnSC - Channel (n) Status and Control /
Pawel Zarembski	0:01f31e923fe2	2253	#define FTM_CnSC_DMA_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2254	#define FTM_CnSC_DMA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2255	#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	2256	#define FTM_CnSC_ELSA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2257	#define FTM_CnSC_ELSA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2258	#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
Pawel Zarembski	0:01f31e923fe2	2259	#define FTM_CnSC_ELSB_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2260	#define FTM_CnSC_ELSB_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2261	#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
Pawel Zarembski	0:01f31e923fe2	2262	#define FTM_CnSC_MSA_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2263	#define FTM_CnSC_MSA_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2264	#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
Pawel Zarembski	0:01f31e923fe2	2265	#define FTM_CnSC_MSB_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2266	#define FTM_CnSC_MSB_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2267	#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
Pawel Zarembski	0:01f31e923fe2	2268	#define FTM_CnSC_CHIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2269	#define FTM_CnSC_CHIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2270	#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2271	#define FTM_CnSC_CHF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2272	#define FTM_CnSC_CHF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2273	#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
Pawel Zarembski	0:01f31e923fe2	2274
Pawel Zarembski	0:01f31e923fe2	2275	/* The count of FTM_CnSC */
Pawel Zarembski	0:01f31e923fe2	2276	#define FTM_CnSC_COUNT (8U)
Pawel Zarembski	0:01f31e923fe2	2277
Pawel Zarembski	0:01f31e923fe2	2278	/! @name CnV - Channel (n) Value /
Pawel Zarembski	0:01f31e923fe2	2279	#define FTM_CnV_VAL_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2280	#define FTM_CnV_VAL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2281	#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2282
Pawel Zarembski	0:01f31e923fe2	2283	/* The count of FTM_CnV */
Pawel Zarembski	0:01f31e923fe2	2284	#define FTM_CnV_COUNT (8U)
Pawel Zarembski	0:01f31e923fe2	2285
Pawel Zarembski	0:01f31e923fe2	2286	/! @name CNTIN - Counter Initial Value /
Pawel Zarembski	0:01f31e923fe2	2287	#define FTM_CNTIN_INIT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2288	#define FTM_CNTIN_INIT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2289	#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
Pawel Zarembski	0:01f31e923fe2	2290
Pawel Zarembski	0:01f31e923fe2	2291	/! @name STATUS - Capture and Compare Status /
Pawel Zarembski	0:01f31e923fe2	2292	#define FTM_STATUS_CH0F_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2293	#define FTM_STATUS_CH0F_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2294	#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
Pawel Zarembski	0:01f31e923fe2	2295	#define FTM_STATUS_CH1F_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2296	#define FTM_STATUS_CH1F_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2297	#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
Pawel Zarembski	0:01f31e923fe2	2298	#define FTM_STATUS_CH2F_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2299	#define FTM_STATUS_CH2F_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2300	#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
Pawel Zarembski	0:01f31e923fe2	2301	#define FTM_STATUS_CH3F_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2302	#define FTM_STATUS_CH3F_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2303	#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
Pawel Zarembski	0:01f31e923fe2	2304	#define FTM_STATUS_CH4F_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2305	#define FTM_STATUS_CH4F_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2306	#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
Pawel Zarembski	0:01f31e923fe2	2307	#define FTM_STATUS_CH5F_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2308	#define FTM_STATUS_CH5F_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2309	#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
Pawel Zarembski	0:01f31e923fe2	2310	#define FTM_STATUS_CH6F_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2311	#define FTM_STATUS_CH6F_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2312	#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
Pawel Zarembski	0:01f31e923fe2	2313	#define FTM_STATUS_CH7F_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2314	#define FTM_STATUS_CH7F_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2315	#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
Pawel Zarembski	0:01f31e923fe2	2316
Pawel Zarembski	0:01f31e923fe2	2317	/! @name MODE - Features Mode Selection /
Pawel Zarembski	0:01f31e923fe2	2318	#define FTM_MODE_FTMEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2319	#define FTM_MODE_FTMEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2320	#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2321	#define FTM_MODE_INIT_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2322	#define FTM_MODE_INIT_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2323	#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
Pawel Zarembski	0:01f31e923fe2	2324	#define FTM_MODE_WPDIS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2325	#define FTM_MODE_WPDIS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2326	#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	2327	#define FTM_MODE_PWMSYNC_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2328	#define FTM_MODE_PWMSYNC_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2329	#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	2330	#define FTM_MODE_CAPTEST_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2331	#define FTM_MODE_CAPTEST_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2332	#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
Pawel Zarembski	0:01f31e923fe2	2333	#define FTM_MODE_FAULTM_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	2334	#define FTM_MODE_FAULTM_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2335	#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
Pawel Zarembski	0:01f31e923fe2	2336	#define FTM_MODE_FAULTIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2337	#define FTM_MODE_FAULTIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2338	#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2339
Pawel Zarembski	0:01f31e923fe2	2340	/! @name SYNC - Synchronization /
Pawel Zarembski	0:01f31e923fe2	2341	#define FTM_SYNC_CNTMIN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2342	#define FTM_SYNC_CNTMIN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2343	#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
Pawel Zarembski	0:01f31e923fe2	2344	#define FTM_SYNC_CNTMAX_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2345	#define FTM_SYNC_CNTMAX_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2346	#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
Pawel Zarembski	0:01f31e923fe2	2347	#define FTM_SYNC_REINIT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2348	#define FTM_SYNC_REINIT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2349	#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
Pawel Zarembski	0:01f31e923fe2	2350	#define FTM_SYNC_SYNCHOM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2351	#define FTM_SYNC_SYNCHOM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2352	#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
Pawel Zarembski	0:01f31e923fe2	2353	#define FTM_SYNC_TRIG0_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2354	#define FTM_SYNC_TRIG0_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2355	#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
Pawel Zarembski	0:01f31e923fe2	2356	#define FTM_SYNC_TRIG1_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2357	#define FTM_SYNC_TRIG1_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2358	#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
Pawel Zarembski	0:01f31e923fe2	2359	#define FTM_SYNC_TRIG2_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2360	#define FTM_SYNC_TRIG2_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2361	#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
Pawel Zarembski	0:01f31e923fe2	2362	#define FTM_SYNC_SWSYNC_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2363	#define FTM_SYNC_SWSYNC_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2364	#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	2365
Pawel Zarembski	0:01f31e923fe2	2366	/! @name OUTINIT - Initial State for Channels Output /
Pawel Zarembski	0:01f31e923fe2	2367	#define FTM_OUTINIT_CH0OI_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2368	#define FTM_OUTINIT_CH0OI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2369	#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2370	#define FTM_OUTINIT_CH1OI_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2371	#define FTM_OUTINIT_CH1OI_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2372	#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2373	#define FTM_OUTINIT_CH2OI_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2374	#define FTM_OUTINIT_CH2OI_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2375	#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2376	#define FTM_OUTINIT_CH3OI_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2377	#define FTM_OUTINIT_CH3OI_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2378	#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2379	#define FTM_OUTINIT_CH4OI_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2380	#define FTM_OUTINIT_CH4OI_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2381	#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2382	#define FTM_OUTINIT_CH5OI_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2383	#define FTM_OUTINIT_CH5OI_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2384	#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2385	#define FTM_OUTINIT_CH6OI_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2386	#define FTM_OUTINIT_CH6OI_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2387	#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2388	#define FTM_OUTINIT_CH7OI_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2389	#define FTM_OUTINIT_CH7OI_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2390	#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
Pawel Zarembski	0:01f31e923fe2	2391
Pawel Zarembski	0:01f31e923fe2	2392	/! @name OUTMASK - Output Mask /
Pawel Zarembski	0:01f31e923fe2	2393	#define FTM_OUTMASK_CH0OM_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2394	#define FTM_OUTMASK_CH0OM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2395	#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2396	#define FTM_OUTMASK_CH1OM_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2397	#define FTM_OUTMASK_CH1OM_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2398	#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2399	#define FTM_OUTMASK_CH2OM_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2400	#define FTM_OUTMASK_CH2OM_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2401	#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2402	#define FTM_OUTMASK_CH3OM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2403	#define FTM_OUTMASK_CH3OM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2404	#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2405	#define FTM_OUTMASK_CH4OM_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2406	#define FTM_OUTMASK_CH4OM_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2407	#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2408	#define FTM_OUTMASK_CH5OM_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2409	#define FTM_OUTMASK_CH5OM_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2410	#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2411	#define FTM_OUTMASK_CH6OM_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2412	#define FTM_OUTMASK_CH6OM_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2413	#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2414	#define FTM_OUTMASK_CH7OM_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2415	#define FTM_OUTMASK_CH7OM_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2416	#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
Pawel Zarembski	0:01f31e923fe2	2417
Pawel Zarembski	0:01f31e923fe2	2418	/! @name COMBINE - Function for Linked Channels /
Pawel Zarembski	0:01f31e923fe2	2419	#define FTM_COMBINE_COMBINE0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2420	#define FTM_COMBINE_COMBINE0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2421	#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2422	#define FTM_COMBINE_COMP0_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2423	#define FTM_COMBINE_COMP0_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2424	#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
Pawel Zarembski	0:01f31e923fe2	2425	#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2426	#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2427	#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2428	#define FTM_COMBINE_DECAP0_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2429	#define FTM_COMBINE_DECAP0_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2430	#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
Pawel Zarembski	0:01f31e923fe2	2431	#define FTM_COMBINE_DTEN0_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2432	#define FTM_COMBINE_DTEN0_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2433	#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2434	#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2435	#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2436	#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2437	#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2438	#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2439	#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2440	#define FTM_COMBINE_COMBINE1_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	2441	#define FTM_COMBINE_COMBINE1_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2442	#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
Pawel Zarembski	0:01f31e923fe2	2443	#define FTM_COMBINE_COMP1_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2444	#define FTM_COMBINE_COMP1_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2445	#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
Pawel Zarembski	0:01f31e923fe2	2446	#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	2447	#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2448	#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	2449	#define FTM_COMBINE_DECAP1_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	2450	#define FTM_COMBINE_DECAP1_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	2451	#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
Pawel Zarembski	0:01f31e923fe2	2452	#define FTM_COMBINE_DTEN1_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	2453	#define FTM_COMBINE_DTEN1_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2454	#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	2455	#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	2456	#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	2457	#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	2458	#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	2459	#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	2460	#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	2461	#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	2462	#define FTM_COMBINE_COMBINE2_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	2463	#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
Pawel Zarembski	0:01f31e923fe2	2464	#define FTM_COMBINE_COMP2_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	2465	#define FTM_COMBINE_COMP2_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	2466	#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
Pawel Zarembski	0:01f31e923fe2	2467	#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	2468	#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	2469	#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	2470	#define FTM_COMBINE_DECAP2_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	2471	#define FTM_COMBINE_DECAP2_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	2472	#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
Pawel Zarembski	0:01f31e923fe2	2473	#define FTM_COMBINE_DTEN2_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	2474	#define FTM_COMBINE_DTEN2_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	2475	#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	2476	#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
Pawel Zarembski	0:01f31e923fe2	2477	#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
Pawel Zarembski	0:01f31e923fe2	2478	#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	2479	#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	2480	#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	2481	#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	2482	#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	2483	#define FTM_COMBINE_COMBINE3_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	2484	#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
Pawel Zarembski	0:01f31e923fe2	2485	#define FTM_COMBINE_COMP3_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	2486	#define FTM_COMBINE_COMP3_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	2487	#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
Pawel Zarembski	0:01f31e923fe2	2488	#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	2489	#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	2490	#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
Pawel Zarembski	0:01f31e923fe2	2491	#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	2492	#define FTM_COMBINE_DECAP3_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	2493	#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
Pawel Zarembski	0:01f31e923fe2	2494	#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	2495	#define FTM_COMBINE_DTEN3_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	2496	#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
Pawel Zarembski	0:01f31e923fe2	2497	#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	2498	#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	2499	#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
Pawel Zarembski	0:01f31e923fe2	2500	#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	2501	#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	2502	#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
Pawel Zarembski	0:01f31e923fe2	2503
Pawel Zarembski	0:01f31e923fe2	2504	/! @name DEADTIME - Deadtime Insertion Control /
Pawel Zarembski	0:01f31e923fe2	2505	#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	2506	#define FTM_DEADTIME_DTVAL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2507	#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2508	#define FTM_DEADTIME_DTPS_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2509	#define FTM_DEADTIME_DTPS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2510	#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
Pawel Zarembski	0:01f31e923fe2	2511
Pawel Zarembski	0:01f31e923fe2	2512	/! @name EXTTRIG - FTM External Trigger /
Pawel Zarembski	0:01f31e923fe2	2513	#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2514	#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2515	#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2516	#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2517	#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2518	#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2519	#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2520	#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2521	#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2522	#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2523	#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2524	#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2525	#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2526	#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2527	#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2528	#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2529	#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2530	#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	2531	#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2532	#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2533	#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2534	#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2535	#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2536	#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
Pawel Zarembski	0:01f31e923fe2	2537
Pawel Zarembski	0:01f31e923fe2	2538	/! @name POL - Channels Polarity /
Pawel Zarembski	0:01f31e923fe2	2539	#define FTM_POL_POL0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2540	#define FTM_POL_POL0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2541	#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
Pawel Zarembski	0:01f31e923fe2	2542	#define FTM_POL_POL1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2543	#define FTM_POL_POL1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2544	#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
Pawel Zarembski	0:01f31e923fe2	2545	#define FTM_POL_POL2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2546	#define FTM_POL_POL2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2547	#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
Pawel Zarembski	0:01f31e923fe2	2548	#define FTM_POL_POL3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2549	#define FTM_POL_POL3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2550	#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
Pawel Zarembski	0:01f31e923fe2	2551	#define FTM_POL_POL4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2552	#define FTM_POL_POL4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2553	#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
Pawel Zarembski	0:01f31e923fe2	2554	#define FTM_POL_POL5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2555	#define FTM_POL_POL5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2556	#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
Pawel Zarembski	0:01f31e923fe2	2557	#define FTM_POL_POL6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2558	#define FTM_POL_POL6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2559	#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
Pawel Zarembski	0:01f31e923fe2	2560	#define FTM_POL_POL7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2561	#define FTM_POL_POL7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2562	#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
Pawel Zarembski	0:01f31e923fe2	2563
Pawel Zarembski	0:01f31e923fe2	2564	/! @name FMS - Fault Mode Status /
Pawel Zarembski	0:01f31e923fe2	2565	#define FTM_FMS_FAULTF0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2566	#define FTM_FMS_FAULTF0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2567	#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
Pawel Zarembski	0:01f31e923fe2	2568	#define FTM_FMS_FAULTF1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2569	#define FTM_FMS_FAULTF1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2570	#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
Pawel Zarembski	0:01f31e923fe2	2571	#define FTM_FMS_FAULTF2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2572	#define FTM_FMS_FAULTF2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2573	#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
Pawel Zarembski	0:01f31e923fe2	2574	#define FTM_FMS_FAULTF3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2575	#define FTM_FMS_FAULTF3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2576	#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
Pawel Zarembski	0:01f31e923fe2	2577	#define FTM_FMS_FAULTIN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2578	#define FTM_FMS_FAULTIN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2579	#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
Pawel Zarembski	0:01f31e923fe2	2580	#define FTM_FMS_WPEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2581	#define FTM_FMS_WPEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2582	#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2583	#define FTM_FMS_FAULTF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2584	#define FTM_FMS_FAULTF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2585	#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
Pawel Zarembski	0:01f31e923fe2	2586
Pawel Zarembski	0:01f31e923fe2	2587	/! @name FILTER - Input Capture Filter Control /
Pawel Zarembski	0:01f31e923fe2	2588	#define FTM_FILTER_CH0FVAL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	2589	#define FTM_FILTER_CH0FVAL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2590	#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2591	#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	2592	#define FTM_FILTER_CH1FVAL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2593	#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2594	#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	2595	#define FTM_FILTER_CH2FVAL_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2596	#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2597	#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	2598	#define FTM_FILTER_CH3FVAL_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2599	#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2600
Pawel Zarembski	0:01f31e923fe2	2601	/! @name FLTCTRL - Fault Control /
Pawel Zarembski	0:01f31e923fe2	2602	#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2603	#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2604	#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2605	#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2606	#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2607	#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2608	#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2609	#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2610	#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2611	#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2612	#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2613	#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2614	#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2615	#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2616	#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2617	#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2618	#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2619	#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2620	#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2621	#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2622	#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2623	#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2624	#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2625	#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2626	#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	2627	#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2628	#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	2629
Pawel Zarembski	0:01f31e923fe2	2630	/! @name QDCTRL - Quadrature Decoder Control and Status /
Pawel Zarembski	0:01f31e923fe2	2631	#define FTM_QDCTRL_QUADEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2632	#define FTM_QDCTRL_QUADEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2633	#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2634	#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2635	#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2636	#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
Pawel Zarembski	0:01f31e923fe2	2637	#define FTM_QDCTRL_QUADIR_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2638	#define FTM_QDCTRL_QUADIR_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2639	#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
Pawel Zarembski	0:01f31e923fe2	2640	#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2641	#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2642	#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	2643	#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2644	#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2645	#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	2646	#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2647	#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2648	#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	2649	#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2650	#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2651	#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
Pawel Zarembski	0:01f31e923fe2	2652	#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2653	#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2654	#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
Pawel Zarembski	0:01f31e923fe2	2655
Pawel Zarembski	0:01f31e923fe2	2656	/! @name CONF - Configuration /
Pawel Zarembski	0:01f31e923fe2	2657	#define FTM_CONF_NUMTOF_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	2658	#define FTM_CONF_NUMTOF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2659	#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
Pawel Zarembski	0:01f31e923fe2	2660	#define FTM_CONF_BDMMODE_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2661	#define FTM_CONF_BDMMODE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2662	#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	2663	#define FTM_CONF_GTBEEN_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2664	#define FTM_CONF_GTBEEN_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2665	#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2666	#define FTM_CONF_GTBEOUT_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	2667	#define FTM_CONF_GTBEOUT_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2668	#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
Pawel Zarembski	0:01f31e923fe2	2669
Pawel Zarembski	0:01f31e923fe2	2670	/! @name FLTPOL - FTM Fault Input Polarity /
Pawel Zarembski	0:01f31e923fe2	2671	#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2672	#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2673	#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
Pawel Zarembski	0:01f31e923fe2	2674	#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2675	#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2676	#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
Pawel Zarembski	0:01f31e923fe2	2677	#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2678	#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2679	#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
Pawel Zarembski	0:01f31e923fe2	2680	#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2681	#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2682	#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
Pawel Zarembski	0:01f31e923fe2	2683
Pawel Zarembski	0:01f31e923fe2	2684	/! @name SYNCONF - Synchronization Configuration /
Pawel Zarembski	0:01f31e923fe2	2685	#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2686	#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2687	#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	2688	#define FTM_SYNCONF_CNTINC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2689	#define FTM_SYNCONF_CNTINC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2690	#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
Pawel Zarembski	0:01f31e923fe2	2691	#define FTM_SYNCONF_INVC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2692	#define FTM_SYNCONF_INVC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2693	#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
Pawel Zarembski	0:01f31e923fe2	2694	#define FTM_SYNCONF_SWOC_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2695	#define FTM_SYNCONF_SWOC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2696	#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
Pawel Zarembski	0:01f31e923fe2	2697	#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2698	#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2699	#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	2700	#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	2701	#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2702	#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	2703	#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2704	#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2705	#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
Pawel Zarembski	0:01f31e923fe2	2706	#define FTM_SYNCONF_SWOM_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	2707	#define FTM_SYNCONF_SWOM_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2708	#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
Pawel Zarembski	0:01f31e923fe2	2709	#define FTM_SYNCONF_SWINVC_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	2710	#define FTM_SYNCONF_SWINVC_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	2711	#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
Pawel Zarembski	0:01f31e923fe2	2712	#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	2713	#define FTM_SYNCONF_SWSOC_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2714	#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
Pawel Zarembski	0:01f31e923fe2	2715	#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	2716	#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	2717	#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	2718	#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	2719	#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	2720	#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
Pawel Zarembski	0:01f31e923fe2	2721	#define FTM_SYNCONF_HWOM_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	2722	#define FTM_SYNCONF_HWOM_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	2723	#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
Pawel Zarembski	0:01f31e923fe2	2724	#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	2725	#define FTM_SYNCONF_HWINVC_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	2726	#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
Pawel Zarembski	0:01f31e923fe2	2727	#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	2728	#define FTM_SYNCONF_HWSOC_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	2729	#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
Pawel Zarembski	0:01f31e923fe2	2730
Pawel Zarembski	0:01f31e923fe2	2731	/! @name INVCTRL - FTM Inverting Control /
Pawel Zarembski	0:01f31e923fe2	2732	#define FTM_INVCTRL_INV0EN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2733	#define FTM_INVCTRL_INV0EN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2734	#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2735	#define FTM_INVCTRL_INV1EN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2736	#define FTM_INVCTRL_INV1EN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2737	#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2738	#define FTM_INVCTRL_INV2EN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2739	#define FTM_INVCTRL_INV2EN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2740	#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2741	#define FTM_INVCTRL_INV3EN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2742	#define FTM_INVCTRL_INV3EN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2743	#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2744
Pawel Zarembski	0:01f31e923fe2	2745	/! @name SWOCTRL - FTM Software Output Control /
Pawel Zarembski	0:01f31e923fe2	2746	#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2747	#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2748	#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2749	#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2750	#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2751	#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2752	#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2753	#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2754	#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2755	#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2756	#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2757	#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2758	#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2759	#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2760	#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2761	#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2762	#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2763	#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2764	#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2765	#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2766	#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2767	#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2768	#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2769	#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
Pawel Zarembski	0:01f31e923fe2	2770	#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	2771	#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2772	#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2773	#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2774	#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2775	#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2776	#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	2777	#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2778	#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2779	#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	2780	#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	2781	#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2782	#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	2783	#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2784	#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2785	#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	2786	#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	2787	#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2788	#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	2789	#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	2790	#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2791	#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	2792	#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	2793	#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
Pawel Zarembski	0:01f31e923fe2	2794
Pawel Zarembski	0:01f31e923fe2	2795	/! @name PWMLOAD - FTM PWM Load /
Pawel Zarembski	0:01f31e923fe2	2796	#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2797	#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2798	#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2799	#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2800	#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2801	#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2802	#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2803	#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2804	#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2805	#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2806	#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2807	#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2808	#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2809	#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2810	#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2811	#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2812	#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2813	#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2814	#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2815	#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2816	#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2817	#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2818	#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2819	#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2820	#define FTM_PWMLOAD_LDOK_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2821	#define FTM_PWMLOAD_LDOK_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2822	#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
Pawel Zarembski	0:01f31e923fe2	2823
Pawel Zarembski	0:01f31e923fe2	2824
Pawel Zarembski	0:01f31e923fe2	2825	/*!
Pawel Zarembski	0:01f31e923fe2	2826	* @}
Pawel Zarembski	0:01f31e923fe2	2827	/ / end of group FTM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2828
Pawel Zarembski	0:01f31e923fe2	2829
Pawel Zarembski	0:01f31e923fe2	2830	/* FTM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2831	/** Peripheral FTM0 base address */
Pawel Zarembski	0:01f31e923fe2	2832	#define FTM0_BASE (0x40038000u)
Pawel Zarembski	0:01f31e923fe2	2833	/** Peripheral FTM0 base pointer */
Pawel Zarembski	0:01f31e923fe2	2834	#define FTM0 ((FTM_Type *)FTM0_BASE)
Pawel Zarembski	0:01f31e923fe2	2835	/** Peripheral FTM1 base address */
Pawel Zarembski	0:01f31e923fe2	2836	#define FTM1_BASE (0x40039000u)
Pawel Zarembski	0:01f31e923fe2	2837	/** Peripheral FTM1 base pointer */
Pawel Zarembski	0:01f31e923fe2	2838	#define FTM1 ((FTM_Type *)FTM1_BASE)
Pawel Zarembski	0:01f31e923fe2	2839	/** Array initializer of FTM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2840	#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE }
Pawel Zarembski	0:01f31e923fe2	2841	/** Array initializer of FTM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2842	#define FTM_BASE_PTRS { FTM0, FTM1 }
Pawel Zarembski	0:01f31e923fe2	2843	/** Interrupt vectors for the FTM peripheral type */
Pawel Zarembski	0:01f31e923fe2	2844	#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn }
Pawel Zarembski	0:01f31e923fe2	2845
Pawel Zarembski	0:01f31e923fe2	2846	/*!
Pawel Zarembski	0:01f31e923fe2	2847	* @}
Pawel Zarembski	0:01f31e923fe2	2848	/ / end of group FTM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2849
Pawel Zarembski	0:01f31e923fe2	2850
Pawel Zarembski	0:01f31e923fe2	2851	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2852	-- GPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2853	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2854
Pawel Zarembski	0:01f31e923fe2	2855	/*!
Pawel Zarembski	0:01f31e923fe2	2856	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2857	* @{
Pawel Zarembski	0:01f31e923fe2	2858	*/
Pawel Zarembski	0:01f31e923fe2	2859
Pawel Zarembski	0:01f31e923fe2	2860	/** GPIO - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2861	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2862	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2863	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2864	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2865	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	2866	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	2867	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	2868	} GPIO_Type;
Pawel Zarembski	0:01f31e923fe2	2869
Pawel Zarembski	0:01f31e923fe2	2870	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2871	-- GPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	2872	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2873
Pawel Zarembski	0:01f31e923fe2	2874	/*!
Pawel Zarembski	0:01f31e923fe2	2875	* @addtogroup GPIO_Register_Masks GPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	2876	* @{
Pawel Zarembski	0:01f31e923fe2	2877	*/
Pawel Zarembski	0:01f31e923fe2	2878
Pawel Zarembski	0:01f31e923fe2	2879	/! @name PDOR - Port Data Output Register /
Pawel Zarembski	0:01f31e923fe2	2880	#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2881	#define GPIO_PDOR_PDO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2882	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
Pawel Zarembski	0:01f31e923fe2	2883
Pawel Zarembski	0:01f31e923fe2	2884	/! @name PSOR - Port Set Output Register /
Pawel Zarembski	0:01f31e923fe2	2885	#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2886	#define GPIO_PSOR_PTSO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2887	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
Pawel Zarembski	0:01f31e923fe2	2888
Pawel Zarembski	0:01f31e923fe2	2889	/! @name PCOR - Port Clear Output Register /
Pawel Zarembski	0:01f31e923fe2	2890	#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2891	#define GPIO_PCOR_PTCO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2892	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
Pawel Zarembski	0:01f31e923fe2	2893
Pawel Zarembski	0:01f31e923fe2	2894	/! @name PTOR - Port Toggle Output Register /
Pawel Zarembski	0:01f31e923fe2	2895	#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2896	#define GPIO_PTOR_PTTO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2897	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
Pawel Zarembski	0:01f31e923fe2	2898
Pawel Zarembski	0:01f31e923fe2	2899	/! @name PDIR - Port Data Input Register /
Pawel Zarembski	0:01f31e923fe2	2900	#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2901	#define GPIO_PDIR_PDI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2902	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
Pawel Zarembski	0:01f31e923fe2	2903
Pawel Zarembski	0:01f31e923fe2	2904	/! @name PDDR - Port Data Direction Register /
Pawel Zarembski	0:01f31e923fe2	2905	#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2906	#define GPIO_PDDR_PDD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2907	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
Pawel Zarembski	0:01f31e923fe2	2908
Pawel Zarembski	0:01f31e923fe2	2909
Pawel Zarembski	0:01f31e923fe2	2910	/*!
Pawel Zarembski	0:01f31e923fe2	2911	* @}
Pawel Zarembski	0:01f31e923fe2	2912	/ / end of group GPIO_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2913
Pawel Zarembski	0:01f31e923fe2	2914
Pawel Zarembski	0:01f31e923fe2	2915	/* GPIO - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2916	/** Peripheral PTA base address */
Pawel Zarembski	0:01f31e923fe2	2917	#define PTA_BASE (0x400FF000u)
Pawel Zarembski	0:01f31e923fe2	2918	/** Peripheral PTA base pointer */
Pawel Zarembski	0:01f31e923fe2	2919	#define PTA ((GPIO_Type *)PTA_BASE)
Pawel Zarembski	0:01f31e923fe2	2920	/** Peripheral PTB base address */
Pawel Zarembski	0:01f31e923fe2	2921	#define PTB_BASE (0x400FF040u)
Pawel Zarembski	0:01f31e923fe2	2922	/** Peripheral PTB base pointer */
Pawel Zarembski	0:01f31e923fe2	2923	#define PTB ((GPIO_Type *)PTB_BASE)
Pawel Zarembski	0:01f31e923fe2	2924	/** Peripheral PTC base address */
Pawel Zarembski	0:01f31e923fe2	2925	#define PTC_BASE (0x400FF080u)
Pawel Zarembski	0:01f31e923fe2	2926	/** Peripheral PTC base pointer */
Pawel Zarembski	0:01f31e923fe2	2927	#define PTC ((GPIO_Type *)PTC_BASE)
Pawel Zarembski	0:01f31e923fe2	2928	/** Peripheral PTD base address */
Pawel Zarembski	0:01f31e923fe2	2929	#define PTD_BASE (0x400FF0C0u)
Pawel Zarembski	0:01f31e923fe2	2930	/** Peripheral PTD base pointer */
Pawel Zarembski	0:01f31e923fe2	2931	#define PTD ((GPIO_Type *)PTD_BASE)
Pawel Zarembski	0:01f31e923fe2	2932	/** Peripheral PTE base address */
Pawel Zarembski	0:01f31e923fe2	2933	#define PTE_BASE (0x400FF100u)
Pawel Zarembski	0:01f31e923fe2	2934	/** Peripheral PTE base pointer */
Pawel Zarembski	0:01f31e923fe2	2935	#define PTE ((GPIO_Type *)PTE_BASE)
Pawel Zarembski	0:01f31e923fe2	2936	/** Array initializer of GPIO peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2937	#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
Pawel Zarembski	0:01f31e923fe2	2938	/** Array initializer of GPIO peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2939	#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
Pawel Zarembski	0:01f31e923fe2	2940
Pawel Zarembski	0:01f31e923fe2	2941	/*!
Pawel Zarembski	0:01f31e923fe2	2942	* @}
Pawel Zarembski	0:01f31e923fe2	2943	/ / end of group GPIO_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2944
Pawel Zarembski	0:01f31e923fe2	2945
Pawel Zarembski	0:01f31e923fe2	2946	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2947	-- I2C Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2948	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2949
Pawel Zarembski	0:01f31e923fe2	2950	/*!
Pawel Zarembski	0:01f31e923fe2	2951	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2952	* @{
Pawel Zarembski	0:01f31e923fe2	2953	*/
Pawel Zarembski	0:01f31e923fe2	2954
Pawel Zarembski	0:01f31e923fe2	2955	/** I2C - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2956	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2957	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2958	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	2959	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	2960	__IO uint8_t S; /*< I2C Status Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	2961	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2962	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	2963	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	2964	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	2965	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2966	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	2967	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	2968	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	2969	} I2C_Type;
Pawel Zarembski	0:01f31e923fe2	2970
Pawel Zarembski	0:01f31e923fe2	2971	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2972	-- I2C Register Masks
Pawel Zarembski	0:01f31e923fe2	2973	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2974
Pawel Zarembski	0:01f31e923fe2	2975	/*!
Pawel Zarembski	0:01f31e923fe2	2976	* @addtogroup I2C_Register_Masks I2C Register Masks
Pawel Zarembski	0:01f31e923fe2	2977	* @{
Pawel Zarembski	0:01f31e923fe2	2978	*/
Pawel Zarembski	0:01f31e923fe2	2979
Pawel Zarembski	0:01f31e923fe2	2980	/! @name A1 - I2C Address Register 1 /
Pawel Zarembski	0:01f31e923fe2	2981	#define I2C_A1_AD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	2982	#define I2C_A1_AD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2983	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
Pawel Zarembski	0:01f31e923fe2	2984
Pawel Zarembski	0:01f31e923fe2	2985	/! @name F - I2C Frequency Divider register /
Pawel Zarembski	0:01f31e923fe2	2986	#define I2C_F_ICR_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	2987	#define I2C_F_ICR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2988	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
Pawel Zarembski	0:01f31e923fe2	2989	#define I2C_F_MULT_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2990	#define I2C_F_MULT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2991	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
Pawel Zarembski	0:01f31e923fe2	2992
Pawel Zarembski	0:01f31e923fe2	2993	/! @name C1 - I2C Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	2994	#define I2C_C1_DMAEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2995	#define I2C_C1_DMAEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2996	#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2997	#define I2C_C1_WUEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2998	#define I2C_C1_WUEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2999	#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3000	#define I2C_C1_RSTA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3001	#define I2C_C1_RSTA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3002	#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
Pawel Zarembski	0:01f31e923fe2	3003	#define I2C_C1_TXAK_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3004	#define I2C_C1_TXAK_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3005	#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
Pawel Zarembski	0:01f31e923fe2	3006	#define I2C_C1_TX_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3007	#define I2C_C1_TX_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3008	#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
Pawel Zarembski	0:01f31e923fe2	3009	#define I2C_C1_MST_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3010	#define I2C_C1_MST_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3011	#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
Pawel Zarembski	0:01f31e923fe2	3012	#define I2C_C1_IICIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3013	#define I2C_C1_IICIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3014	#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3015	#define I2C_C1_IICEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3016	#define I2C_C1_IICEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3017	#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3018
Pawel Zarembski	0:01f31e923fe2	3019	/! @name S - I2C Status Register /
Pawel Zarembski	0:01f31e923fe2	3020	#define I2C_S_RXAK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3021	#define I2C_S_RXAK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3022	#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
Pawel Zarembski	0:01f31e923fe2	3023	#define I2C_S_IICIF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3024	#define I2C_S_IICIF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3025	#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
Pawel Zarembski	0:01f31e923fe2	3026	#define I2C_S_SRW_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3027	#define I2C_S_SRW_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3028	#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
Pawel Zarembski	0:01f31e923fe2	3029	#define I2C_S_RAM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3030	#define I2C_S_RAM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3031	#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
Pawel Zarembski	0:01f31e923fe2	3032	#define I2C_S_ARBL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3033	#define I2C_S_ARBL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3034	#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
Pawel Zarembski	0:01f31e923fe2	3035	#define I2C_S_BUSY_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3036	#define I2C_S_BUSY_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3037	#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
Pawel Zarembski	0:01f31e923fe2	3038	#define I2C_S_IAAS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3039	#define I2C_S_IAAS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3040	#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
Pawel Zarembski	0:01f31e923fe2	3041	#define I2C_S_TCF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3042	#define I2C_S_TCF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3043	#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
Pawel Zarembski	0:01f31e923fe2	3044
Pawel Zarembski	0:01f31e923fe2	3045	/! @name D - I2C Data I/O register /
Pawel Zarembski	0:01f31e923fe2	3046	#define I2C_D_DATA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3047	#define I2C_D_DATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3048	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
Pawel Zarembski	0:01f31e923fe2	3049
Pawel Zarembski	0:01f31e923fe2	3050	/! @name C2 - I2C Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	3051	#define I2C_C2_AD_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	3052	#define I2C_C2_AD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3053	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
Pawel Zarembski	0:01f31e923fe2	3054	#define I2C_C2_RMEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3055	#define I2C_C2_RMEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3056	#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3057	#define I2C_C2_SBRC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3058	#define I2C_C2_SBRC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3059	#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
Pawel Zarembski	0:01f31e923fe2	3060	#define I2C_C2_HDRS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3061	#define I2C_C2_HDRS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3062	#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
Pawel Zarembski	0:01f31e923fe2	3063	#define I2C_C2_ADEXT_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3064	#define I2C_C2_ADEXT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3065	#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
Pawel Zarembski	0:01f31e923fe2	3066	#define I2C_C2_GCAEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3067	#define I2C_C2_GCAEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3068	#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3069
Pawel Zarembski	0:01f31e923fe2	3070	/! @name FLT - I2C Programmable Input Glitch Filter register /
Pawel Zarembski	0:01f31e923fe2	3071	#define I2C_FLT_FLT_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3072	#define I2C_FLT_FLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3073	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
Pawel Zarembski	0:01f31e923fe2	3074
Pawel Zarembski	0:01f31e923fe2	3075	/! @name RA - I2C Range Address register /
Pawel Zarembski	0:01f31e923fe2	3076	#define I2C_RA_RAD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	3077	#define I2C_RA_RAD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3078	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
Pawel Zarembski	0:01f31e923fe2	3079
Pawel Zarembski	0:01f31e923fe2	3080	/! @name SMB - I2C SMBus Control and Status register /
Pawel Zarembski	0:01f31e923fe2	3081	#define I2C_SMB_SHTF2IE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3082	#define I2C_SMB_SHTF2IE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3083	#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
Pawel Zarembski	0:01f31e923fe2	3084	#define I2C_SMB_SHTF2_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3085	#define I2C_SMB_SHTF2_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3086	#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
Pawel Zarembski	0:01f31e923fe2	3087	#define I2C_SMB_SHTF1_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3088	#define I2C_SMB_SHTF1_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3089	#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
Pawel Zarembski	0:01f31e923fe2	3090	#define I2C_SMB_SLTF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3091	#define I2C_SMB_SLTF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3092	#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
Pawel Zarembski	0:01f31e923fe2	3093	#define I2C_SMB_TCKSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3094	#define I2C_SMB_TCKSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3095	#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3096	#define I2C_SMB_SIICAEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3097	#define I2C_SMB_SIICAEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3098	#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3099	#define I2C_SMB_ALERTEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3100	#define I2C_SMB_ALERTEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3101	#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3102	#define I2C_SMB_FACK_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3103	#define I2C_SMB_FACK_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3104	#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
Pawel Zarembski	0:01f31e923fe2	3105
Pawel Zarembski	0:01f31e923fe2	3106	/! @name A2 - I2C Address Register 2 /
Pawel Zarembski	0:01f31e923fe2	3107	#define I2C_A2_SAD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	3108	#define I2C_A2_SAD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3109	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
Pawel Zarembski	0:01f31e923fe2	3110
Pawel Zarembski	0:01f31e923fe2	3111	/! @name SLTH - I2C SCL Low Timeout Register High /
Pawel Zarembski	0:01f31e923fe2	3112	#define I2C_SLTH_SSLT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3113	#define I2C_SLTH_SSLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3114	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
Pawel Zarembski	0:01f31e923fe2	3115
Pawel Zarembski	0:01f31e923fe2	3116	/! @name SLTL - I2C SCL Low Timeout Register Low /
Pawel Zarembski	0:01f31e923fe2	3117	#define I2C_SLTL_SSLT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3118	#define I2C_SLTL_SSLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3119	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
Pawel Zarembski	0:01f31e923fe2	3120
Pawel Zarembski	0:01f31e923fe2	3121
Pawel Zarembski	0:01f31e923fe2	3122	/*!
Pawel Zarembski	0:01f31e923fe2	3123	* @}
Pawel Zarembski	0:01f31e923fe2	3124	/ / end of group I2C_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3125
Pawel Zarembski	0:01f31e923fe2	3126
Pawel Zarembski	0:01f31e923fe2	3127	/* I2C - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3128	/** Peripheral I2C0 base address */
Pawel Zarembski	0:01f31e923fe2	3129	#define I2C0_BASE (0x40066000u)
Pawel Zarembski	0:01f31e923fe2	3130	/** Peripheral I2C0 base pointer */
Pawel Zarembski	0:01f31e923fe2	3131	#define I2C0 ((I2C_Type *)I2C0_BASE)
Pawel Zarembski	0:01f31e923fe2	3132	/** Array initializer of I2C peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3133	#define I2C_BASE_ADDRS { I2C0_BASE }
Pawel Zarembski	0:01f31e923fe2	3134	/** Array initializer of I2C peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3135	#define I2C_BASE_PTRS { I2C0 }
Pawel Zarembski	0:01f31e923fe2	3136	/** Interrupt vectors for the I2C peripheral type */
Pawel Zarembski	0:01f31e923fe2	3137	#define I2C_IRQS { I2C0_IRQn }
Pawel Zarembski	0:01f31e923fe2	3138
Pawel Zarembski	0:01f31e923fe2	3139	/*!
Pawel Zarembski	0:01f31e923fe2	3140	* @}
Pawel Zarembski	0:01f31e923fe2	3141	/ / end of group I2C_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3142
Pawel Zarembski	0:01f31e923fe2	3143
Pawel Zarembski	0:01f31e923fe2	3144	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3145	-- I2S Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3146	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3147
Pawel Zarembski	0:01f31e923fe2	3148	/*!
Pawel Zarembski	0:01f31e923fe2	3149	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3150	* @{
Pawel Zarembski	0:01f31e923fe2	3151	*/
Pawel Zarembski	0:01f31e923fe2	3152
Pawel Zarembski	0:01f31e923fe2	3153	/** I2S - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3154	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3155	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3156	__IO uint32_t TCR1; /*< SAI Transmit Configuration 1 Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3157	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3158	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3159	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3160	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	3161	uint8_t RESERVED_0[8];
Pawel Zarembski	0:01f31e923fe2	3162	__O uint32_t TDR[2]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3163	uint8_t RESERVED_1[24];
Pawel Zarembski	0:01f31e923fe2	3164	__I uint32_t TFR[2]; /*< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3165	uint8_t RESERVED_2[24];
Pawel Zarembski	0:01f31e923fe2	3166	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
Pawel Zarembski	0:01f31e923fe2	3167	uint8_t RESERVED_3[28];
Pawel Zarembski	0:01f31e923fe2	3168	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	3169	__IO uint32_t RCR1; /*< SAI Receive Configuration 1 Register, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	3170	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	3171	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
Pawel Zarembski	0:01f31e923fe2	3172	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
Pawel Zarembski	0:01f31e923fe2	3173	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
Pawel Zarembski	0:01f31e923fe2	3174	uint8_t RESERVED_4[8];
Pawel Zarembski	0:01f31e923fe2	3175	__I uint32_t RDR[2]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3176	uint8_t RESERVED_5[24];
Pawel Zarembski	0:01f31e923fe2	3177	__I uint32_t RFR[2]; /*< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3178	uint8_t RESERVED_6[24];
Pawel Zarembski	0:01f31e923fe2	3179	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
Pawel Zarembski	0:01f31e923fe2	3180	uint8_t RESERVED_7[28];
Pawel Zarembski	0:01f31e923fe2	3181	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	3182	__IO uint32_t MDR; /*< MCLK Divide Register, offset: 0x104 /
Pawel Zarembski	0:01f31e923fe2	3183	} I2S_Type;
Pawel Zarembski	0:01f31e923fe2	3184
Pawel Zarembski	0:01f31e923fe2	3185	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3186	-- I2S Register Masks
Pawel Zarembski	0:01f31e923fe2	3187	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3188
Pawel Zarembski	0:01f31e923fe2	3189	/*!
Pawel Zarembski	0:01f31e923fe2	3190	* @addtogroup I2S_Register_Masks I2S Register Masks
Pawel Zarembski	0:01f31e923fe2	3191	* @{
Pawel Zarembski	0:01f31e923fe2	3192	*/
Pawel Zarembski	0:01f31e923fe2	3193
Pawel Zarembski	0:01f31e923fe2	3194	/! @name TCSR - SAI Transmit Control Register /
Pawel Zarembski	0:01f31e923fe2	3195	#define I2S_TCSR_FRDE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3196	#define I2S_TCSR_FRDE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3197	#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
Pawel Zarembski	0:01f31e923fe2	3198	#define I2S_TCSR_FWDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3199	#define I2S_TCSR_FWDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3200	#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
Pawel Zarembski	0:01f31e923fe2	3201	#define I2S_TCSR_FRIE_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	3202	#define I2S_TCSR_FRIE_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3203	#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3204	#define I2S_TCSR_FWIE_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	3205	#define I2S_TCSR_FWIE_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	3206	#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3207	#define I2S_TCSR_FEIE_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	3208	#define I2S_TCSR_FEIE_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	3209	#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3210	#define I2S_TCSR_SEIE_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	3211	#define I2S_TCSR_SEIE_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	3212	#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3213	#define I2S_TCSR_WSIE_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	3214	#define I2S_TCSR_WSIE_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	3215	#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3216	#define I2S_TCSR_FRF_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	3217	#define I2S_TCSR_FRF_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3218	#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
Pawel Zarembski	0:01f31e923fe2	3219	#define I2S_TCSR_FWF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	3220	#define I2S_TCSR_FWF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	3221	#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
Pawel Zarembski	0:01f31e923fe2	3222	#define I2S_TCSR_FEF_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	3223	#define I2S_TCSR_FEF_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	3224	#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
Pawel Zarembski	0:01f31e923fe2	3225	#define I2S_TCSR_SEF_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	3226	#define I2S_TCSR_SEF_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	3227	#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
Pawel Zarembski	0:01f31e923fe2	3228	#define I2S_TCSR_WSF_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	3229	#define I2S_TCSR_WSF_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	3230	#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
Pawel Zarembski	0:01f31e923fe2	3231	#define I2S_TCSR_SR_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	3232	#define I2S_TCSR_SR_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3233	#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
Pawel Zarembski	0:01f31e923fe2	3234	#define I2S_TCSR_FR_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	3235	#define I2S_TCSR_FR_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	3236	#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
Pawel Zarembski	0:01f31e923fe2	3237	#define I2S_TCSR_BCE_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	3238	#define I2S_TCSR_BCE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	3239	#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3240	#define I2S_TCSR_DBGE_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	3241	#define I2S_TCSR_DBGE_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	3242	#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
Pawel Zarembski	0:01f31e923fe2	3243	#define I2S_TCSR_STOPE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	3244	#define I2S_TCSR_STOPE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	3245	#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
Pawel Zarembski	0:01f31e923fe2	3246	#define I2S_TCSR_TE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	3247	#define I2S_TCSR_TE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	3248	#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
Pawel Zarembski	0:01f31e923fe2	3249
Pawel Zarembski	0:01f31e923fe2	3250	/! @name TCR1 - SAI Transmit Configuration 1 Register /
Pawel Zarembski	0:01f31e923fe2	3251	#define I2S_TCR1_TFW_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	3252	#define I2S_TCR1_TFW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3253	#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
Pawel Zarembski	0:01f31e923fe2	3254
Pawel Zarembski	0:01f31e923fe2	3255	/! @name TCR2 - SAI Transmit Configuration 2 Register /
Pawel Zarembski	0:01f31e923fe2	3256	#define I2S_TCR2_DIV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3257	#define I2S_TCR2_DIV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3258	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
Pawel Zarembski	0:01f31e923fe2	3259	#define I2S_TCR2_BCD_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	3260	#define I2S_TCR2_BCD_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3261	#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
Pawel Zarembski	0:01f31e923fe2	3262	#define I2S_TCR2_BCP_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	3263	#define I2S_TCR2_BCP_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	3264	#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
Pawel Zarembski	0:01f31e923fe2	3265	#define I2S_TCR2_MSEL_MASK (0xC000000U)
Pawel Zarembski	0:01f31e923fe2	3266	#define I2S_TCR2_MSEL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	3267	#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3268	#define I2S_TCR2_BCI_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	3269	#define I2S_TCR2_BCI_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	3270	#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
Pawel Zarembski	0:01f31e923fe2	3271	#define I2S_TCR2_BCS_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	3272	#define I2S_TCR2_BCS_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	3273	#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
Pawel Zarembski	0:01f31e923fe2	3274	#define I2S_TCR2_SYNC_MASK (0xC0000000U)
Pawel Zarembski	0:01f31e923fe2	3275	#define I2S_TCR2_SYNC_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	3276	#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	3277
Pawel Zarembski	0:01f31e923fe2	3278	/! @name TCR3 - SAI Transmit Configuration 3 Register /
Pawel Zarembski	0:01f31e923fe2	3279	#define I2S_TCR3_WDFL_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3280	#define I2S_TCR3_WDFL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3281	#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
Pawel Zarembski	0:01f31e923fe2	3282	#define I2S_TCR3_TCE_MASK (0x30000U)
Pawel Zarembski	0:01f31e923fe2	3283	#define I2S_TCR3_TCE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3284	#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3285
Pawel Zarembski	0:01f31e923fe2	3286	/! @name TCR4 - SAI Transmit Configuration 4 Register /
Pawel Zarembski	0:01f31e923fe2	3287	#define I2S_TCR4_FSD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3288	#define I2S_TCR4_FSD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3289	#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
Pawel Zarembski	0:01f31e923fe2	3290	#define I2S_TCR4_FSP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3291	#define I2S_TCR4_FSP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3292	#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
Pawel Zarembski	0:01f31e923fe2	3293	#define I2S_TCR4_FSE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3294	#define I2S_TCR4_FSE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3295	#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
Pawel Zarembski	0:01f31e923fe2	3296	#define I2S_TCR4_MF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3297	#define I2S_TCR4_MF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3298	#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
Pawel Zarembski	0:01f31e923fe2	3299	#define I2S_TCR4_SYWD_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	3300	#define I2S_TCR4_SYWD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3301	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
Pawel Zarembski	0:01f31e923fe2	3302	#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	3303	#define I2S_TCR4_FRSZ_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3304	#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	3305
Pawel Zarembski	0:01f31e923fe2	3306	/! @name TCR5 - SAI Transmit Configuration 5 Register /
Pawel Zarembski	0:01f31e923fe2	3307	#define I2S_TCR5_FBT_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	3308	#define I2S_TCR5_FBT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3309	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
Pawel Zarembski	0:01f31e923fe2	3310	#define I2S_TCR5_W0W_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	3311	#define I2S_TCR5_W0W_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3312	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
Pawel Zarembski	0:01f31e923fe2	3313	#define I2S_TCR5_WNW_MASK (0x1F000000U)
Pawel Zarembski	0:01f31e923fe2	3314	#define I2S_TCR5_WNW_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3315	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
Pawel Zarembski	0:01f31e923fe2	3316
Pawel Zarembski	0:01f31e923fe2	3317	/! @name TDR - SAI Transmit Data Register /
Pawel Zarembski	0:01f31e923fe2	3318	#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3319	#define I2S_TDR_TDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3320	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
Pawel Zarembski	0:01f31e923fe2	3321
Pawel Zarembski	0:01f31e923fe2	3322	/* The count of I2S_TDR */
Pawel Zarembski	0:01f31e923fe2	3323	#define I2S_TDR_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3324
Pawel Zarembski	0:01f31e923fe2	3325	/! @name TFR - SAI Transmit FIFO Register /
Pawel Zarembski	0:01f31e923fe2	3326	#define I2S_TFR_RFP_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	3327	#define I2S_TFR_RFP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3328	#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
Pawel Zarembski	0:01f31e923fe2	3329	#define I2S_TFR_WFP_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	3330	#define I2S_TFR_WFP_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3331	#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
Pawel Zarembski	0:01f31e923fe2	3332
Pawel Zarembski	0:01f31e923fe2	3333	/* The count of I2S_TFR */
Pawel Zarembski	0:01f31e923fe2	3334	#define I2S_TFR_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3335
Pawel Zarembski	0:01f31e923fe2	3336	/! @name TMR - SAI Transmit Mask Register /
Pawel Zarembski	0:01f31e923fe2	3337	#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3338	#define I2S_TMR_TWM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3339	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
Pawel Zarembski	0:01f31e923fe2	3340
Pawel Zarembski	0:01f31e923fe2	3341	/! @name RCSR - SAI Receive Control Register /
Pawel Zarembski	0:01f31e923fe2	3342	#define I2S_RCSR_FRDE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3343	#define I2S_RCSR_FRDE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3344	#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
Pawel Zarembski	0:01f31e923fe2	3345	#define I2S_RCSR_FWDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3346	#define I2S_RCSR_FWDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3347	#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
Pawel Zarembski	0:01f31e923fe2	3348	#define I2S_RCSR_FRIE_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	3349	#define I2S_RCSR_FRIE_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3350	#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3351	#define I2S_RCSR_FWIE_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	3352	#define I2S_RCSR_FWIE_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	3353	#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3354	#define I2S_RCSR_FEIE_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	3355	#define I2S_RCSR_FEIE_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	3356	#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3357	#define I2S_RCSR_SEIE_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	3358	#define I2S_RCSR_SEIE_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	3359	#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3360	#define I2S_RCSR_WSIE_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	3361	#define I2S_RCSR_WSIE_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	3362	#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3363	#define I2S_RCSR_FRF_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	3364	#define I2S_RCSR_FRF_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3365	#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
Pawel Zarembski	0:01f31e923fe2	3366	#define I2S_RCSR_FWF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	3367	#define I2S_RCSR_FWF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	3368	#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
Pawel Zarembski	0:01f31e923fe2	3369	#define I2S_RCSR_FEF_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	3370	#define I2S_RCSR_FEF_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	3371	#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
Pawel Zarembski	0:01f31e923fe2	3372	#define I2S_RCSR_SEF_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	3373	#define I2S_RCSR_SEF_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	3374	#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
Pawel Zarembski	0:01f31e923fe2	3375	#define I2S_RCSR_WSF_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	3376	#define I2S_RCSR_WSF_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	3377	#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
Pawel Zarembski	0:01f31e923fe2	3378	#define I2S_RCSR_SR_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	3379	#define I2S_RCSR_SR_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3380	#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
Pawel Zarembski	0:01f31e923fe2	3381	#define I2S_RCSR_FR_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	3382	#define I2S_RCSR_FR_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	3383	#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
Pawel Zarembski	0:01f31e923fe2	3384	#define I2S_RCSR_BCE_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	3385	#define I2S_RCSR_BCE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	3386	#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3387	#define I2S_RCSR_DBGE_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	3388	#define I2S_RCSR_DBGE_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	3389	#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
Pawel Zarembski	0:01f31e923fe2	3390	#define I2S_RCSR_STOPE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	3391	#define I2S_RCSR_STOPE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	3392	#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
Pawel Zarembski	0:01f31e923fe2	3393	#define I2S_RCSR_RE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	3394	#define I2S_RCSR_RE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	3395	#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	3396
Pawel Zarembski	0:01f31e923fe2	3397	/! @name RCR1 - SAI Receive Configuration 1 Register /
Pawel Zarembski	0:01f31e923fe2	3398	#define I2S_RCR1_RFW_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	3399	#define I2S_RCR1_RFW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3400	#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
Pawel Zarembski	0:01f31e923fe2	3401
Pawel Zarembski	0:01f31e923fe2	3402	/! @name RCR2 - SAI Receive Configuration 2 Register /
Pawel Zarembski	0:01f31e923fe2	3403	#define I2S_RCR2_DIV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3404	#define I2S_RCR2_DIV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3405	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
Pawel Zarembski	0:01f31e923fe2	3406	#define I2S_RCR2_BCD_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	3407	#define I2S_RCR2_BCD_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3408	#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
Pawel Zarembski	0:01f31e923fe2	3409	#define I2S_RCR2_BCP_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	3410	#define I2S_RCR2_BCP_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	3411	#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
Pawel Zarembski	0:01f31e923fe2	3412	#define I2S_RCR2_MSEL_MASK (0xC000000U)
Pawel Zarembski	0:01f31e923fe2	3413	#define I2S_RCR2_MSEL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	3414	#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3415	#define I2S_RCR2_BCI_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	3416	#define I2S_RCR2_BCI_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	3417	#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
Pawel Zarembski	0:01f31e923fe2	3418	#define I2S_RCR2_BCS_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	3419	#define I2S_RCR2_BCS_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	3420	#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
Pawel Zarembski	0:01f31e923fe2	3421	#define I2S_RCR2_SYNC_MASK (0xC0000000U)
Pawel Zarembski	0:01f31e923fe2	3422	#define I2S_RCR2_SYNC_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	3423	#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	3424
Pawel Zarembski	0:01f31e923fe2	3425	/! @name RCR3 - SAI Receive Configuration 3 Register /
Pawel Zarembski	0:01f31e923fe2	3426	#define I2S_RCR3_WDFL_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3427	#define I2S_RCR3_WDFL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3428	#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
Pawel Zarembski	0:01f31e923fe2	3429	#define I2S_RCR3_RCE_MASK (0x30000U)
Pawel Zarembski	0:01f31e923fe2	3430	#define I2S_RCR3_RCE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3431	#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3432
Pawel Zarembski	0:01f31e923fe2	3433	/! @name RCR4 - SAI Receive Configuration 4 Register /
Pawel Zarembski	0:01f31e923fe2	3434	#define I2S_RCR4_FSD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3435	#define I2S_RCR4_FSD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3436	#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
Pawel Zarembski	0:01f31e923fe2	3437	#define I2S_RCR4_FSP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3438	#define I2S_RCR4_FSP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3439	#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
Pawel Zarembski	0:01f31e923fe2	3440	#define I2S_RCR4_FSE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3441	#define I2S_RCR4_FSE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3442	#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
Pawel Zarembski	0:01f31e923fe2	3443	#define I2S_RCR4_MF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3444	#define I2S_RCR4_MF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3445	#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
Pawel Zarembski	0:01f31e923fe2	3446	#define I2S_RCR4_SYWD_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	3447	#define I2S_RCR4_SYWD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3448	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
Pawel Zarembski	0:01f31e923fe2	3449	#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	3450	#define I2S_RCR4_FRSZ_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3451	#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	3452
Pawel Zarembski	0:01f31e923fe2	3453	/! @name RCR5 - SAI Receive Configuration 5 Register /
Pawel Zarembski	0:01f31e923fe2	3454	#define I2S_RCR5_FBT_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	3455	#define I2S_RCR5_FBT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3456	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
Pawel Zarembski	0:01f31e923fe2	3457	#define I2S_RCR5_W0W_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	3458	#define I2S_RCR5_W0W_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3459	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
Pawel Zarembski	0:01f31e923fe2	3460	#define I2S_RCR5_WNW_MASK (0x1F000000U)
Pawel Zarembski	0:01f31e923fe2	3461	#define I2S_RCR5_WNW_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3462	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
Pawel Zarembski	0:01f31e923fe2	3463
Pawel Zarembski	0:01f31e923fe2	3464	/! @name RDR - SAI Receive Data Register /
Pawel Zarembski	0:01f31e923fe2	3465	#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3466	#define I2S_RDR_RDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3467	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
Pawel Zarembski	0:01f31e923fe2	3468
Pawel Zarembski	0:01f31e923fe2	3469	/* The count of I2S_RDR */
Pawel Zarembski	0:01f31e923fe2	3470	#define I2S_RDR_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3471
Pawel Zarembski	0:01f31e923fe2	3472	/! @name RFR - SAI Receive FIFO Register /
Pawel Zarembski	0:01f31e923fe2	3473	#define I2S_RFR_RFP_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	3474	#define I2S_RFR_RFP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3475	#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
Pawel Zarembski	0:01f31e923fe2	3476	#define I2S_RFR_WFP_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	3477	#define I2S_RFR_WFP_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3478	#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
Pawel Zarembski	0:01f31e923fe2	3479
Pawel Zarembski	0:01f31e923fe2	3480	/* The count of I2S_RFR */
Pawel Zarembski	0:01f31e923fe2	3481	#define I2S_RFR_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3482
Pawel Zarembski	0:01f31e923fe2	3483	/! @name RMR - SAI Receive Mask Register /
Pawel Zarembski	0:01f31e923fe2	3484	#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3485	#define I2S_RMR_RWM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3486	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
Pawel Zarembski	0:01f31e923fe2	3487
Pawel Zarembski	0:01f31e923fe2	3488	/! @name MCR - SAI MCLK Control Register /
Pawel Zarembski	0:01f31e923fe2	3489	#define I2S_MCR_MICS_MASK (0x3000000U)
Pawel Zarembski	0:01f31e923fe2	3490	#define I2S_MCR_MICS_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3491	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
Pawel Zarembski	0:01f31e923fe2	3492	#define I2S_MCR_MOE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	3493	#define I2S_MCR_MOE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	3494	#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
Pawel Zarembski	0:01f31e923fe2	3495	#define I2S_MCR_DUF_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	3496	#define I2S_MCR_DUF_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	3497	#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
Pawel Zarembski	0:01f31e923fe2	3498
Pawel Zarembski	0:01f31e923fe2	3499	/! @name MDR - MCLK Divide Register /
Pawel Zarembski	0:01f31e923fe2	3500	#define I2S_MDR_DIVIDE_MASK (0xFFFU)
Pawel Zarembski	0:01f31e923fe2	3501	#define I2S_MDR_DIVIDE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3502	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
Pawel Zarembski	0:01f31e923fe2	3503	#define I2S_MDR_FRACT_MASK (0xFF000U)
Pawel Zarembski	0:01f31e923fe2	3504	#define I2S_MDR_FRACT_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	3505	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
Pawel Zarembski	0:01f31e923fe2	3506
Pawel Zarembski	0:01f31e923fe2	3507
Pawel Zarembski	0:01f31e923fe2	3508	/*!
Pawel Zarembski	0:01f31e923fe2	3509	* @}
Pawel Zarembski	0:01f31e923fe2	3510	/ / end of group I2S_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3511
Pawel Zarembski	0:01f31e923fe2	3512
Pawel Zarembski	0:01f31e923fe2	3513	/* I2S - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3514	/** Peripheral I2S0 base address */
Pawel Zarembski	0:01f31e923fe2	3515	#define I2S0_BASE (0x4002F000u)
Pawel Zarembski	0:01f31e923fe2	3516	/** Peripheral I2S0 base pointer */
Pawel Zarembski	0:01f31e923fe2	3517	#define I2S0 ((I2S_Type *)I2S0_BASE)
Pawel Zarembski	0:01f31e923fe2	3518	/** Array initializer of I2S peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3519	#define I2S_BASE_ADDRS { I2S0_BASE }
Pawel Zarembski	0:01f31e923fe2	3520	/** Array initializer of I2S peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3521	#define I2S_BASE_PTRS { I2S0 }
Pawel Zarembski	0:01f31e923fe2	3522	/** Interrupt vectors for the I2S peripheral type */
Pawel Zarembski	0:01f31e923fe2	3523	#define I2S_RX_IRQS { I2S0_Rx_IRQn }
Pawel Zarembski	0:01f31e923fe2	3524	#define I2S_TX_IRQS { I2S0_Tx_IRQn }
Pawel Zarembski	0:01f31e923fe2	3525
Pawel Zarembski	0:01f31e923fe2	3526	/*!
Pawel Zarembski	0:01f31e923fe2	3527	* @}
Pawel Zarembski	0:01f31e923fe2	3528	/ / end of group I2S_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3529
Pawel Zarembski	0:01f31e923fe2	3530
Pawel Zarembski	0:01f31e923fe2	3531	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3532	-- LLWU Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3533	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3534
Pawel Zarembski	0:01f31e923fe2	3535	/*!
Pawel Zarembski	0:01f31e923fe2	3536	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3537	* @{
Pawel Zarembski	0:01f31e923fe2	3538	*/
Pawel Zarembski	0:01f31e923fe2	3539
Pawel Zarembski	0:01f31e923fe2	3540	/** LLWU - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3541	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3542	__IO uint8_t PE1; /*< LLWU Pin Enable 1 Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3543	__IO uint8_t PE2; /*< LLWU Pin Enable 2 Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	3544	__IO uint8_t PE3; /*< LLWU Pin Enable 3 Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	3545	__IO uint8_t PE4; /*< LLWU Pin Enable 4 Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	3546	__IO uint8_t ME; /*< LLWU Module Enable Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3547	__IO uint8_t F1; /*< LLWU Flag 1 Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	3548	__IO uint8_t F2; /*< LLWU Flag 2 Register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	3549	__I uint8_t F3; /*< LLWU Flag 3 Register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	3550	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3551	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 Register, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	3552	__IO uint8_t RST; /*< LLWU Reset Enable Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	3553	} LLWU_Type;
Pawel Zarembski	0:01f31e923fe2	3554
Pawel Zarembski	0:01f31e923fe2	3555	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3556	-- LLWU Register Masks
Pawel Zarembski	0:01f31e923fe2	3557	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3558
Pawel Zarembski	0:01f31e923fe2	3559	/*!
Pawel Zarembski	0:01f31e923fe2	3560	* @addtogroup LLWU_Register_Masks LLWU Register Masks
Pawel Zarembski	0:01f31e923fe2	3561	* @{
Pawel Zarembski	0:01f31e923fe2	3562	*/
Pawel Zarembski	0:01f31e923fe2	3563
Pawel Zarembski	0:01f31e923fe2	3564	/! @name PE1 - LLWU Pin Enable 1 Register /
Pawel Zarembski	0:01f31e923fe2	3565	#define LLWU_PE1_WUPE0_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3566	#define LLWU_PE1_WUPE0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3567	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
Pawel Zarembski	0:01f31e923fe2	3568	#define LLWU_PE1_WUPE1_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3569	#define LLWU_PE1_WUPE1_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3570	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
Pawel Zarembski	0:01f31e923fe2	3571	#define LLWU_PE1_WUPE2_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3572	#define LLWU_PE1_WUPE2_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3573	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
Pawel Zarembski	0:01f31e923fe2	3574	#define LLWU_PE1_WUPE3_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3575	#define LLWU_PE1_WUPE3_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3576	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
Pawel Zarembski	0:01f31e923fe2	3577
Pawel Zarembski	0:01f31e923fe2	3578	/! @name PE2 - LLWU Pin Enable 2 Register /
Pawel Zarembski	0:01f31e923fe2	3579	#define LLWU_PE2_WUPE4_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3580	#define LLWU_PE2_WUPE4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3581	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
Pawel Zarembski	0:01f31e923fe2	3582	#define LLWU_PE2_WUPE5_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3583	#define LLWU_PE2_WUPE5_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3584	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
Pawel Zarembski	0:01f31e923fe2	3585	#define LLWU_PE2_WUPE6_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3586	#define LLWU_PE2_WUPE6_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3587	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
Pawel Zarembski	0:01f31e923fe2	3588	#define LLWU_PE2_WUPE7_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3589	#define LLWU_PE2_WUPE7_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3590	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
Pawel Zarembski	0:01f31e923fe2	3591
Pawel Zarembski	0:01f31e923fe2	3592	/! @name PE3 - LLWU Pin Enable 3 Register /
Pawel Zarembski	0:01f31e923fe2	3593	#define LLWU_PE3_WUPE8_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3594	#define LLWU_PE3_WUPE8_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3595	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
Pawel Zarembski	0:01f31e923fe2	3596	#define LLWU_PE3_WUPE9_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3597	#define LLWU_PE3_WUPE9_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3598	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
Pawel Zarembski	0:01f31e923fe2	3599	#define LLWU_PE3_WUPE10_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3600	#define LLWU_PE3_WUPE10_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3601	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
Pawel Zarembski	0:01f31e923fe2	3602	#define LLWU_PE3_WUPE11_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3603	#define LLWU_PE3_WUPE11_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3604	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
Pawel Zarembski	0:01f31e923fe2	3605
Pawel Zarembski	0:01f31e923fe2	3606	/! @name PE4 - LLWU Pin Enable 4 Register /
Pawel Zarembski	0:01f31e923fe2	3607	#define LLWU_PE4_WUPE12_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3608	#define LLWU_PE4_WUPE12_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3609	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
Pawel Zarembski	0:01f31e923fe2	3610	#define LLWU_PE4_WUPE13_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3611	#define LLWU_PE4_WUPE13_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3612	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
Pawel Zarembski	0:01f31e923fe2	3613	#define LLWU_PE4_WUPE14_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3614	#define LLWU_PE4_WUPE14_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3615	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
Pawel Zarembski	0:01f31e923fe2	3616	#define LLWU_PE4_WUPE15_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3617	#define LLWU_PE4_WUPE15_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3618	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
Pawel Zarembski	0:01f31e923fe2	3619
Pawel Zarembski	0:01f31e923fe2	3620	/! @name ME - LLWU Module Enable Register /
Pawel Zarembski	0:01f31e923fe2	3621	#define LLWU_ME_WUME0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3622	#define LLWU_ME_WUME0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3623	#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
Pawel Zarembski	0:01f31e923fe2	3624	#define LLWU_ME_WUME1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3625	#define LLWU_ME_WUME1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3626	#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
Pawel Zarembski	0:01f31e923fe2	3627	#define LLWU_ME_WUME2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3628	#define LLWU_ME_WUME2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3629	#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
Pawel Zarembski	0:01f31e923fe2	3630	#define LLWU_ME_WUME3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3631	#define LLWU_ME_WUME3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3632	#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
Pawel Zarembski	0:01f31e923fe2	3633	#define LLWU_ME_WUME4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3634	#define LLWU_ME_WUME4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3635	#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
Pawel Zarembski	0:01f31e923fe2	3636	#define LLWU_ME_WUME5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3637	#define LLWU_ME_WUME5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3638	#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
Pawel Zarembski	0:01f31e923fe2	3639	#define LLWU_ME_WUME6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3640	#define LLWU_ME_WUME6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3641	#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
Pawel Zarembski	0:01f31e923fe2	3642	#define LLWU_ME_WUME7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3643	#define LLWU_ME_WUME7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3644	#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
Pawel Zarembski	0:01f31e923fe2	3645
Pawel Zarembski	0:01f31e923fe2	3646	/! @name F1 - LLWU Flag 1 Register /
Pawel Zarembski	0:01f31e923fe2	3647	#define LLWU_F1_WUF0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3648	#define LLWU_F1_WUF0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3649	#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
Pawel Zarembski	0:01f31e923fe2	3650	#define LLWU_F1_WUF1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3651	#define LLWU_F1_WUF1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3652	#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
Pawel Zarembski	0:01f31e923fe2	3653	#define LLWU_F1_WUF2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3654	#define LLWU_F1_WUF2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3655	#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
Pawel Zarembski	0:01f31e923fe2	3656	#define LLWU_F1_WUF3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3657	#define LLWU_F1_WUF3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3658	#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
Pawel Zarembski	0:01f31e923fe2	3659	#define LLWU_F1_WUF4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3660	#define LLWU_F1_WUF4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3661	#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
Pawel Zarembski	0:01f31e923fe2	3662	#define LLWU_F1_WUF5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3663	#define LLWU_F1_WUF5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3664	#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
Pawel Zarembski	0:01f31e923fe2	3665	#define LLWU_F1_WUF6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3666	#define LLWU_F1_WUF6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3667	#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
Pawel Zarembski	0:01f31e923fe2	3668	#define LLWU_F1_WUF7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3669	#define LLWU_F1_WUF7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3670	#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
Pawel Zarembski	0:01f31e923fe2	3671
Pawel Zarembski	0:01f31e923fe2	3672	/! @name F2 - LLWU Flag 2 Register /
Pawel Zarembski	0:01f31e923fe2	3673	#define LLWU_F2_WUF8_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3674	#define LLWU_F2_WUF8_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3675	#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
Pawel Zarembski	0:01f31e923fe2	3676	#define LLWU_F2_WUF9_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3677	#define LLWU_F2_WUF9_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3678	#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
Pawel Zarembski	0:01f31e923fe2	3679	#define LLWU_F2_WUF10_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3680	#define LLWU_F2_WUF10_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3681	#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
Pawel Zarembski	0:01f31e923fe2	3682	#define LLWU_F2_WUF11_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3683	#define LLWU_F2_WUF11_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3684	#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
Pawel Zarembski	0:01f31e923fe2	3685	#define LLWU_F2_WUF12_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3686	#define LLWU_F2_WUF12_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3687	#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
Pawel Zarembski	0:01f31e923fe2	3688	#define LLWU_F2_WUF13_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3689	#define LLWU_F2_WUF13_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3690	#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
Pawel Zarembski	0:01f31e923fe2	3691	#define LLWU_F2_WUF14_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3692	#define LLWU_F2_WUF14_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3693	#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
Pawel Zarembski	0:01f31e923fe2	3694	#define LLWU_F2_WUF15_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3695	#define LLWU_F2_WUF15_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3696	#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
Pawel Zarembski	0:01f31e923fe2	3697
Pawel Zarembski	0:01f31e923fe2	3698	/! @name F3 - LLWU Flag 3 Register /
Pawel Zarembski	0:01f31e923fe2	3699	#define LLWU_F3_MWUF0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3700	#define LLWU_F3_MWUF0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3701	#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
Pawel Zarembski	0:01f31e923fe2	3702	#define LLWU_F3_MWUF1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3703	#define LLWU_F3_MWUF1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3704	#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
Pawel Zarembski	0:01f31e923fe2	3705	#define LLWU_F3_MWUF2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3706	#define LLWU_F3_MWUF2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3707	#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
Pawel Zarembski	0:01f31e923fe2	3708	#define LLWU_F3_MWUF3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3709	#define LLWU_F3_MWUF3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3710	#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
Pawel Zarembski	0:01f31e923fe2	3711	#define LLWU_F3_MWUF4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3712	#define LLWU_F3_MWUF4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3713	#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
Pawel Zarembski	0:01f31e923fe2	3714	#define LLWU_F3_MWUF5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3715	#define LLWU_F3_MWUF5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3716	#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
Pawel Zarembski	0:01f31e923fe2	3717	#define LLWU_F3_MWUF6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3718	#define LLWU_F3_MWUF6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3719	#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
Pawel Zarembski	0:01f31e923fe2	3720	#define LLWU_F3_MWUF7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3721	#define LLWU_F3_MWUF7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3722	#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
Pawel Zarembski	0:01f31e923fe2	3723
Pawel Zarembski	0:01f31e923fe2	3724	/! @name FILT1 - LLWU Pin Filter 1 Register /
Pawel Zarembski	0:01f31e923fe2	3725	#define LLWU_FILT1_FILTSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	3726	#define LLWU_FILT1_FILTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3727	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3728	#define LLWU_FILT1_FILTE_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	3729	#define LLWU_FILT1_FILTE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3730	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
Pawel Zarembski	0:01f31e923fe2	3731	#define LLWU_FILT1_FILTF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3732	#define LLWU_FILT1_FILTF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3733	#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
Pawel Zarembski	0:01f31e923fe2	3734
Pawel Zarembski	0:01f31e923fe2	3735	/! @name FILT2 - LLWU Pin Filter 2 Register /
Pawel Zarembski	0:01f31e923fe2	3736	#define LLWU_FILT2_FILTSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	3737	#define LLWU_FILT2_FILTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3738	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3739	#define LLWU_FILT2_FILTE_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	3740	#define LLWU_FILT2_FILTE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3741	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
Pawel Zarembski	0:01f31e923fe2	3742	#define LLWU_FILT2_FILTF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3743	#define LLWU_FILT2_FILTF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3744	#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
Pawel Zarembski	0:01f31e923fe2	3745
Pawel Zarembski	0:01f31e923fe2	3746	/! @name RST - LLWU Reset Enable Register /
Pawel Zarembski	0:01f31e923fe2	3747	#define LLWU_RST_RSTFILT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3748	#define LLWU_RST_RSTFILT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3749	#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
Pawel Zarembski	0:01f31e923fe2	3750	#define LLWU_RST_LLRSTE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3751	#define LLWU_RST_LLRSTE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3752	#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
Pawel Zarembski	0:01f31e923fe2	3753
Pawel Zarembski	0:01f31e923fe2	3754
Pawel Zarembski	0:01f31e923fe2	3755	/*!
Pawel Zarembski	0:01f31e923fe2	3756	* @}
Pawel Zarembski	0:01f31e923fe2	3757	/ / end of group LLWU_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3758
Pawel Zarembski	0:01f31e923fe2	3759
Pawel Zarembski	0:01f31e923fe2	3760	/* LLWU - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3761	/** Peripheral LLWU base address */
Pawel Zarembski	0:01f31e923fe2	3762	#define LLWU_BASE (0x4007C000u)
Pawel Zarembski	0:01f31e923fe2	3763	/** Peripheral LLWU base pointer */
Pawel Zarembski	0:01f31e923fe2	3764	#define LLWU ((LLWU_Type *)LLWU_BASE)
Pawel Zarembski	0:01f31e923fe2	3765	/** Array initializer of LLWU peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3766	#define LLWU_BASE_ADDRS { LLWU_BASE }
Pawel Zarembski	0:01f31e923fe2	3767	/** Array initializer of LLWU peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3768	#define LLWU_BASE_PTRS { LLWU }
Pawel Zarembski	0:01f31e923fe2	3769	/** Interrupt vectors for the LLWU peripheral type */
Pawel Zarembski	0:01f31e923fe2	3770	#define LLWU_IRQS { LLW_IRQn }
Pawel Zarembski	0:01f31e923fe2	3771
Pawel Zarembski	0:01f31e923fe2	3772	/*!
Pawel Zarembski	0:01f31e923fe2	3773	* @}
Pawel Zarembski	0:01f31e923fe2	3774	/ / end of group LLWU_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3775
Pawel Zarembski	0:01f31e923fe2	3776
Pawel Zarembski	0:01f31e923fe2	3777	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3778	-- LPTMR Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3779	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3780
Pawel Zarembski	0:01f31e923fe2	3781	/*!
Pawel Zarembski	0:01f31e923fe2	3782	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3783	* @{
Pawel Zarembski	0:01f31e923fe2	3784	*/
Pawel Zarembski	0:01f31e923fe2	3785
Pawel Zarembski	0:01f31e923fe2	3786	/** LPTMR - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3787	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3788	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3789	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3790	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3791	__IO uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3792	} LPTMR_Type;
Pawel Zarembski	0:01f31e923fe2	3793
Pawel Zarembski	0:01f31e923fe2	3794	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3795	-- LPTMR Register Masks
Pawel Zarembski	0:01f31e923fe2	3796	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3797
Pawel Zarembski	0:01f31e923fe2	3798	/*!
Pawel Zarembski	0:01f31e923fe2	3799	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Pawel Zarembski	0:01f31e923fe2	3800	* @{
Pawel Zarembski	0:01f31e923fe2	3801	*/
Pawel Zarembski	0:01f31e923fe2	3802
Pawel Zarembski	0:01f31e923fe2	3803	/! @name CSR - Low Power Timer Control Status Register /
Pawel Zarembski	0:01f31e923fe2	3804	#define LPTMR_CSR_TEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3805	#define LPTMR_CSR_TEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3806	#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3807	#define LPTMR_CSR_TMS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3808	#define LPTMR_CSR_TMS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3809	#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
Pawel Zarembski	0:01f31e923fe2	3810	#define LPTMR_CSR_TFC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3811	#define LPTMR_CSR_TFC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3812	#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
Pawel Zarembski	0:01f31e923fe2	3813	#define LPTMR_CSR_TPP_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3814	#define LPTMR_CSR_TPP_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3815	#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
Pawel Zarembski	0:01f31e923fe2	3816	#define LPTMR_CSR_TPS_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3817	#define LPTMR_CSR_TPS_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3818	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
Pawel Zarembski	0:01f31e923fe2	3819	#define LPTMR_CSR_TIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3820	#define LPTMR_CSR_TIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3821	#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3822	#define LPTMR_CSR_TCF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3823	#define LPTMR_CSR_TCF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3824	#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
Pawel Zarembski	0:01f31e923fe2	3825
Pawel Zarembski	0:01f31e923fe2	3826	/! @name PSR - Low Power Timer Prescale Register /
Pawel Zarembski	0:01f31e923fe2	3827	#define LPTMR_PSR_PCS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3828	#define LPTMR_PSR_PCS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3829	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
Pawel Zarembski	0:01f31e923fe2	3830	#define LPTMR_PSR_PBYP_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3831	#define LPTMR_PSR_PBYP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3832	#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
Pawel Zarembski	0:01f31e923fe2	3833	#define LPTMR_PSR_PRESCALE_MASK (0x78U)
Pawel Zarembski	0:01f31e923fe2	3834	#define LPTMR_PSR_PRESCALE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3835	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
Pawel Zarembski	0:01f31e923fe2	3836
Pawel Zarembski	0:01f31e923fe2	3837	/! @name CMR - Low Power Timer Compare Register /
Pawel Zarembski	0:01f31e923fe2	3838	#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	3839	#define LPTMR_CMR_COMPARE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3840	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
Pawel Zarembski	0:01f31e923fe2	3841
Pawel Zarembski	0:01f31e923fe2	3842	/! @name CNR - Low Power Timer Counter Register /
Pawel Zarembski	0:01f31e923fe2	3843	#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	3844	#define LPTMR_CNR_COUNTER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3845	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
Pawel Zarembski	0:01f31e923fe2	3846
Pawel Zarembski	0:01f31e923fe2	3847
Pawel Zarembski	0:01f31e923fe2	3848	/*!
Pawel Zarembski	0:01f31e923fe2	3849	* @}
Pawel Zarembski	0:01f31e923fe2	3850	/ / end of group LPTMR_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3851
Pawel Zarembski	0:01f31e923fe2	3852
Pawel Zarembski	0:01f31e923fe2	3853	/* LPTMR - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3854	/** Peripheral LPTMR0 base address */
Pawel Zarembski	0:01f31e923fe2	3855	#define LPTMR0_BASE (0x40040000u)
Pawel Zarembski	0:01f31e923fe2	3856	/** Peripheral LPTMR0 base pointer */
Pawel Zarembski	0:01f31e923fe2	3857	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Pawel Zarembski	0:01f31e923fe2	3858	/** Array initializer of LPTMR peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3859	#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
Pawel Zarembski	0:01f31e923fe2	3860	/** Array initializer of LPTMR peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3861	#define LPTMR_BASE_PTRS { LPTMR0 }
Pawel Zarembski	0:01f31e923fe2	3862	/** Interrupt vectors for the LPTMR peripheral type */
Pawel Zarembski	0:01f31e923fe2	3863	#define LPTMR_IRQS { LPTimer_IRQn }
Pawel Zarembski	0:01f31e923fe2	3864
Pawel Zarembski	0:01f31e923fe2	3865	/*!
Pawel Zarembski	0:01f31e923fe2	3866	* @}
Pawel Zarembski	0:01f31e923fe2	3867	/ / end of group LPTMR_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3868
Pawel Zarembski	0:01f31e923fe2	3869
Pawel Zarembski	0:01f31e923fe2	3870	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3871	-- MCG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3872	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3873
Pawel Zarembski	0:01f31e923fe2	3874	/*!
Pawel Zarembski	0:01f31e923fe2	3875	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3876	* @{
Pawel Zarembski	0:01f31e923fe2	3877	*/
Pawel Zarembski	0:01f31e923fe2	3878
Pawel Zarembski	0:01f31e923fe2	3879	/** MCG - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3880	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3881	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3882	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	3883	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	3884	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	3885	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3886	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	3887	__IO uint8_t S; /*< MCG Status Register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	3888	uint8_t RESERVED_0[1];
Pawel Zarembski	0:01f31e923fe2	3889	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3890	uint8_t RESERVED_1[1];
Pawel Zarembski	0:01f31e923fe2	3891	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	3892	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	3893	__IO uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3894	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	3895	} MCG_Type;
Pawel Zarembski	0:01f31e923fe2	3896
Pawel Zarembski	0:01f31e923fe2	3897	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3898	-- MCG Register Masks
Pawel Zarembski	0:01f31e923fe2	3899	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3900
Pawel Zarembski	0:01f31e923fe2	3901	/*!
Pawel Zarembski	0:01f31e923fe2	3902	* @addtogroup MCG_Register_Masks MCG Register Masks
Pawel Zarembski	0:01f31e923fe2	3903	* @{
Pawel Zarembski	0:01f31e923fe2	3904	*/
Pawel Zarembski	0:01f31e923fe2	3905
Pawel Zarembski	0:01f31e923fe2	3906	/! @name C1 - MCG Control 1 Register /
Pawel Zarembski	0:01f31e923fe2	3907	#define MCG_C1_IREFSTEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3908	#define MCG_C1_IREFSTEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3909	#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3910	#define MCG_C1_IRCLKEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3911	#define MCG_C1_IRCLKEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3912	#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3913	#define MCG_C1_IREFS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3914	#define MCG_C1_IREFS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3915	#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
Pawel Zarembski	0:01f31e923fe2	3916	#define MCG_C1_FRDIV_MASK (0x38U)
Pawel Zarembski	0:01f31e923fe2	3917	#define MCG_C1_FRDIV_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3918	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	3919	#define MCG_C1_CLKS_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3920	#define MCG_C1_CLKS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3921	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	3922
Pawel Zarembski	0:01f31e923fe2	3923	/! @name C2 - MCG Control 2 Register /
Pawel Zarembski	0:01f31e923fe2	3924	#define MCG_C2_IRCS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3925	#define MCG_C2_IRCS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3926	#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
Pawel Zarembski	0:01f31e923fe2	3927	#define MCG_C2_LP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3928	#define MCG_C2_LP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3929	#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
Pawel Zarembski	0:01f31e923fe2	3930	#define MCG_C2_EREFS0_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3931	#define MCG_C2_EREFS0_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3932	#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
Pawel Zarembski	0:01f31e923fe2	3933	#define MCG_C2_HGO0_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3934	#define MCG_C2_HGO0_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3935	#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
Pawel Zarembski	0:01f31e923fe2	3936	#define MCG_C2_RANGE0_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3937	#define MCG_C2_RANGE0_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3938	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
Pawel Zarembski	0:01f31e923fe2	3939	#define MCG_C2_LOCRE0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3940	#define MCG_C2_LOCRE0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3941	#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
Pawel Zarembski	0:01f31e923fe2	3942
Pawel Zarembski	0:01f31e923fe2	3943	/! @name C3 - MCG Control 3 Register /
Pawel Zarembski	0:01f31e923fe2	3944	#define MCG_C3_SCTRIM_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3945	#define MCG_C3_SCTRIM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3946	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	3947
Pawel Zarembski	0:01f31e923fe2	3948	/! @name C4 - MCG Control 4 Register /
Pawel Zarembski	0:01f31e923fe2	3949	#define MCG_C4_SCFTRIM_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3950	#define MCG_C4_SCFTRIM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3951	#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	3952	#define MCG_C4_FCTRIM_MASK (0x1EU)
Pawel Zarembski	0:01f31e923fe2	3953	#define MCG_C4_FCTRIM_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3954	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	3955	#define MCG_C4_DRST_DRS_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	3956	#define MCG_C4_DRST_DRS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3957	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
Pawel Zarembski	0:01f31e923fe2	3958	#define MCG_C4_DMX32_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3959	#define MCG_C4_DMX32_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3960	#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
Pawel Zarembski	0:01f31e923fe2	3961
Pawel Zarembski	0:01f31e923fe2	3962	/! @name C5 - MCG Control 5 Register /
Pawel Zarembski	0:01f31e923fe2	3963	#define MCG_C5_PRDIV0_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3964	#define MCG_C5_PRDIV0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3965	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
Pawel Zarembski	0:01f31e923fe2	3966	#define MCG_C5_PLLSTEN0_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3967	#define MCG_C5_PLLSTEN0_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3968	#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	3969	#define MCG_C5_PLLCLKEN0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3970	#define MCG_C5_PLLCLKEN0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3971	#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	3972
Pawel Zarembski	0:01f31e923fe2	3973	/! @name C6 - MCG Control 6 Register /
Pawel Zarembski	0:01f31e923fe2	3974	#define MCG_C6_VDIV0_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3975	#define MCG_C6_VDIV0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3976	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
Pawel Zarembski	0:01f31e923fe2	3977	#define MCG_C6_CME0_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3978	#define MCG_C6_CME0_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3979	#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
Pawel Zarembski	0:01f31e923fe2	3980	#define MCG_C6_PLLS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3981	#define MCG_C6_PLLS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3982	#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
Pawel Zarembski	0:01f31e923fe2	3983	#define MCG_C6_LOLIE0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3984	#define MCG_C6_LOLIE0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3985	#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
Pawel Zarembski	0:01f31e923fe2	3986
Pawel Zarembski	0:01f31e923fe2	3987	/! @name S - MCG Status Register /
Pawel Zarembski	0:01f31e923fe2	3988	#define MCG_S_IRCST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3989	#define MCG_S_IRCST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3990	#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
Pawel Zarembski	0:01f31e923fe2	3991	#define MCG_S_OSCINIT0_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3992	#define MCG_S_OSCINIT0_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3993	#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
Pawel Zarembski	0:01f31e923fe2	3994	#define MCG_S_CLKST_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3995	#define MCG_S_CLKST_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3996	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
Pawel Zarembski	0:01f31e923fe2	3997	#define MCG_S_IREFST_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3998	#define MCG_S_IREFST_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3999	#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
Pawel Zarembski	0:01f31e923fe2	4000	#define MCG_S_PLLST_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4001	#define MCG_S_PLLST_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4002	#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
Pawel Zarembski	0:01f31e923fe2	4003	#define MCG_S_LOCK0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4004	#define MCG_S_LOCK0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4005	#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
Pawel Zarembski	0:01f31e923fe2	4006	#define MCG_S_LOLS0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4007	#define MCG_S_LOLS0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4008	#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
Pawel Zarembski	0:01f31e923fe2	4009
Pawel Zarembski	0:01f31e923fe2	4010	/! @name SC - MCG Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	4011	#define MCG_SC_LOCS0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4012	#define MCG_SC_LOCS0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4013	#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
Pawel Zarembski	0:01f31e923fe2	4014	#define MCG_SC_FCRDIV_MASK (0xEU)
Pawel Zarembski	0:01f31e923fe2	4015	#define MCG_SC_FCRDIV_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4016	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	4017	#define MCG_SC_FLTPRSRV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4018	#define MCG_SC_FLTPRSRV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4019	#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
Pawel Zarembski	0:01f31e923fe2	4020	#define MCG_SC_ATMF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4021	#define MCG_SC_ATMF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4022	#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
Pawel Zarembski	0:01f31e923fe2	4023	#define MCG_SC_ATMS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4024	#define MCG_SC_ATMS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4025	#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
Pawel Zarembski	0:01f31e923fe2	4026	#define MCG_SC_ATME_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4027	#define MCG_SC_ATME_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4028	#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
Pawel Zarembski	0:01f31e923fe2	4029
Pawel Zarembski	0:01f31e923fe2	4030	/! @name ATCVH - MCG Auto Trim Compare Value High Register /
Pawel Zarembski	0:01f31e923fe2	4031	#define MCG_ATCVH_ATCVH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4032	#define MCG_ATCVH_ATCVH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4033	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
Pawel Zarembski	0:01f31e923fe2	4034
Pawel Zarembski	0:01f31e923fe2	4035	/! @name ATCVL - MCG Auto Trim Compare Value Low Register /
Pawel Zarembski	0:01f31e923fe2	4036	#define MCG_ATCVL_ATCVL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4037	#define MCG_ATCVL_ATCVL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4038	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
Pawel Zarembski	0:01f31e923fe2	4039
Pawel Zarembski	0:01f31e923fe2	4040	/! @name C7 - MCG Control 7 Register /
Pawel Zarembski	0:01f31e923fe2	4041	#define MCG_C7_OSCSEL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4042	#define MCG_C7_OSCSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4043	#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4044
Pawel Zarembski	0:01f31e923fe2	4045	/! @name C8 - MCG Control 8 Register /
Pawel Zarembski	0:01f31e923fe2	4046	#define MCG_C8_LOCS1_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4047	#define MCG_C8_LOCS1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4048	#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
Pawel Zarembski	0:01f31e923fe2	4049	#define MCG_C8_CME1_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4050	#define MCG_C8_CME1_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4051	#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
Pawel Zarembski	0:01f31e923fe2	4052	#define MCG_C8_LOLRE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4053	#define MCG_C8_LOLRE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4054	#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
Pawel Zarembski	0:01f31e923fe2	4055	#define MCG_C8_LOCRE1_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4056	#define MCG_C8_LOCRE1_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4057	#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
Pawel Zarembski	0:01f31e923fe2	4058
Pawel Zarembski	0:01f31e923fe2	4059
Pawel Zarembski	0:01f31e923fe2	4060	/*!
Pawel Zarembski	0:01f31e923fe2	4061	* @}
Pawel Zarembski	0:01f31e923fe2	4062	/ / end of group MCG_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4063
Pawel Zarembski	0:01f31e923fe2	4064
Pawel Zarembski	0:01f31e923fe2	4065	/* MCG - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4066	/** Peripheral MCG base address */
Pawel Zarembski	0:01f31e923fe2	4067	#define MCG_BASE (0x40064000u)
Pawel Zarembski	0:01f31e923fe2	4068	/** Peripheral MCG base pointer */
Pawel Zarembski	0:01f31e923fe2	4069	#define MCG ((MCG_Type *)MCG_BASE)
Pawel Zarembski	0:01f31e923fe2	4070	/** Array initializer of MCG peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4071	#define MCG_BASE_ADDRS { MCG_BASE }
Pawel Zarembski	0:01f31e923fe2	4072	/** Array initializer of MCG peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4073	#define MCG_BASE_PTRS { MCG }
Pawel Zarembski	0:01f31e923fe2	4074	/* MCG C2[EREFS] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	4075	#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
Pawel Zarembski	0:01f31e923fe2	4076	#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	4077	#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	4078	#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
Pawel Zarembski	0:01f31e923fe2	4079
Pawel Zarembski	0:01f31e923fe2	4080	/* MCG C2[HGO] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	4081	#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
Pawel Zarembski	0:01f31e923fe2	4082	#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	4083	#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	4084	#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
Pawel Zarembski	0:01f31e923fe2	4085
Pawel Zarembski	0:01f31e923fe2	4086	/* MCG C2[RANGE] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	4087	#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
Pawel Zarembski	0:01f31e923fe2	4088	#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	4089	#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	4090	#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
Pawel Zarembski	0:01f31e923fe2	4091
Pawel Zarembski	0:01f31e923fe2	4092
Pawel Zarembski	0:01f31e923fe2	4093	/*!
Pawel Zarembski	0:01f31e923fe2	4094	* @}
Pawel Zarembski	0:01f31e923fe2	4095	/ / end of group MCG_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4096
Pawel Zarembski	0:01f31e923fe2	4097
Pawel Zarembski	0:01f31e923fe2	4098	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4099	-- NV Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4100	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4101
Pawel Zarembski	0:01f31e923fe2	4102	/*!
Pawel Zarembski	0:01f31e923fe2	4103	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4104	* @{
Pawel Zarembski	0:01f31e923fe2	4105	*/
Pawel Zarembski	0:01f31e923fe2	4106
Pawel Zarembski	0:01f31e923fe2	4107	/** NV - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4108	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4109	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4110	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4111	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	4112	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	4113	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4114	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	4115	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	4116	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	4117	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4118	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	4119	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	4120	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	4121	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	4122	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	4123	__I uint8_t FEPROT; /*< Non-volatile EERAM Protection Register, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	4124	__I uint8_t FDPROT; /*< Non-volatile D-Flash Protection Register, offset: 0xF /
Pawel Zarembski	0:01f31e923fe2	4125	} NV_Type;
Pawel Zarembski	0:01f31e923fe2	4126
Pawel Zarembski	0:01f31e923fe2	4127	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4128	-- NV Register Masks
Pawel Zarembski	0:01f31e923fe2	4129	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4130
Pawel Zarembski	0:01f31e923fe2	4131	/*!
Pawel Zarembski	0:01f31e923fe2	4132	* @addtogroup NV_Register_Masks NV Register Masks
Pawel Zarembski	0:01f31e923fe2	4133	* @{
Pawel Zarembski	0:01f31e923fe2	4134	*/
Pawel Zarembski	0:01f31e923fe2	4135
Pawel Zarembski	0:01f31e923fe2	4136	/! @name BACKKEY3 - Backdoor Comparison Key 3. /
Pawel Zarembski	0:01f31e923fe2	4137	#define NV_BACKKEY3_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4138	#define NV_BACKKEY3_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4139	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4140
Pawel Zarembski	0:01f31e923fe2	4141	/! @name BACKKEY2 - Backdoor Comparison Key 2. /
Pawel Zarembski	0:01f31e923fe2	4142	#define NV_BACKKEY2_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4143	#define NV_BACKKEY2_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4144	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4145
Pawel Zarembski	0:01f31e923fe2	4146	/! @name BACKKEY1 - Backdoor Comparison Key 1. /
Pawel Zarembski	0:01f31e923fe2	4147	#define NV_BACKKEY1_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4148	#define NV_BACKKEY1_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4149	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4150
Pawel Zarembski	0:01f31e923fe2	4151	/! @name BACKKEY0 - Backdoor Comparison Key 0. /
Pawel Zarembski	0:01f31e923fe2	4152	#define NV_BACKKEY0_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4153	#define NV_BACKKEY0_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4154	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4155
Pawel Zarembski	0:01f31e923fe2	4156	/! @name BACKKEY7 - Backdoor Comparison Key 7. /
Pawel Zarembski	0:01f31e923fe2	4157	#define NV_BACKKEY7_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4158	#define NV_BACKKEY7_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4159	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4160
Pawel Zarembski	0:01f31e923fe2	4161	/! @name BACKKEY6 - Backdoor Comparison Key 6. /
Pawel Zarembski	0:01f31e923fe2	4162	#define NV_BACKKEY6_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4163	#define NV_BACKKEY6_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4164	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4165
Pawel Zarembski	0:01f31e923fe2	4166	/! @name BACKKEY5 - Backdoor Comparison Key 5. /
Pawel Zarembski	0:01f31e923fe2	4167	#define NV_BACKKEY5_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4168	#define NV_BACKKEY5_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4169	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4170
Pawel Zarembski	0:01f31e923fe2	4171	/! @name BACKKEY4 - Backdoor Comparison Key 4. /
Pawel Zarembski	0:01f31e923fe2	4172	#define NV_BACKKEY4_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4173	#define NV_BACKKEY4_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4174	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	4175
Pawel Zarembski	0:01f31e923fe2	4176	/! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register /
Pawel Zarembski	0:01f31e923fe2	4177	#define NV_FPROT3_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4178	#define NV_FPROT3_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4179	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4180
Pawel Zarembski	0:01f31e923fe2	4181	/! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register /
Pawel Zarembski	0:01f31e923fe2	4182	#define NV_FPROT2_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4183	#define NV_FPROT2_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4184	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4185
Pawel Zarembski	0:01f31e923fe2	4186	/! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register /
Pawel Zarembski	0:01f31e923fe2	4187	#define NV_FPROT1_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4188	#define NV_FPROT1_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4189	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4190
Pawel Zarembski	0:01f31e923fe2	4191	/! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register /
Pawel Zarembski	0:01f31e923fe2	4192	#define NV_FPROT0_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4193	#define NV_FPROT0_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4194	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4195
Pawel Zarembski	0:01f31e923fe2	4196	/! @name FSEC - Non-volatile Flash Security Register /
Pawel Zarembski	0:01f31e923fe2	4197	#define NV_FSEC_SEC_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	4198	#define NV_FSEC_SEC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4199	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
Pawel Zarembski	0:01f31e923fe2	4200	#define NV_FSEC_FSLACC_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	4201	#define NV_FSEC_FSLACC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4202	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
Pawel Zarembski	0:01f31e923fe2	4203	#define NV_FSEC_MEEN_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	4204	#define NV_FSEC_MEEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4205	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4206	#define NV_FSEC_KEYEN_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	4207	#define NV_FSEC_KEYEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4208	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4209
Pawel Zarembski	0:01f31e923fe2	4210	/! @name FOPT - Non-volatile Flash Option Register /
Pawel Zarembski	0:01f31e923fe2	4211	#define NV_FOPT_LPBOOT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4212	#define NV_FOPT_LPBOOT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4213	#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
Pawel Zarembski	0:01f31e923fe2	4214	#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4215	#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4216	#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
Pawel Zarembski	0:01f31e923fe2	4217	#define NV_FOPT_NMI_DIS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4218	#define NV_FOPT_NMI_DIS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4219	#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
Pawel Zarembski	0:01f31e923fe2	4220
Pawel Zarembski	0:01f31e923fe2	4221	/! @name FEPROT - Non-volatile EERAM Protection Register /
Pawel Zarembski	0:01f31e923fe2	4222	#define NV_FEPROT_EPROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4223	#define NV_FEPROT_EPROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4224	#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4225
Pawel Zarembski	0:01f31e923fe2	4226	/! @name FDPROT - Non-volatile D-Flash Protection Register /
Pawel Zarembski	0:01f31e923fe2	4227	#define NV_FDPROT_DPROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4228	#define NV_FDPROT_DPROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4229	#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4230
Pawel Zarembski	0:01f31e923fe2	4231
Pawel Zarembski	0:01f31e923fe2	4232	/*!
Pawel Zarembski	0:01f31e923fe2	4233	* @}
Pawel Zarembski	0:01f31e923fe2	4234	/ / end of group NV_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4235
Pawel Zarembski	0:01f31e923fe2	4236
Pawel Zarembski	0:01f31e923fe2	4237	/* NV - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4238	/** Peripheral FTFL_FlashConfig base address */
Pawel Zarembski	0:01f31e923fe2	4239	#define FTFL_FlashConfig_BASE (0x400u)
Pawel Zarembski	0:01f31e923fe2	4240	/** Peripheral FTFL_FlashConfig base pointer */
Pawel Zarembski	0:01f31e923fe2	4241	#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
Pawel Zarembski	0:01f31e923fe2	4242	/** Array initializer of NV peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4243	#define NV_BASE_ADDRS { FTFL_FlashConfig_BASE }
Pawel Zarembski	0:01f31e923fe2	4244	/** Array initializer of NV peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4245	#define NV_BASE_PTRS { FTFL_FlashConfig }
Pawel Zarembski	0:01f31e923fe2	4246
Pawel Zarembski	0:01f31e923fe2	4247	/*!
Pawel Zarembski	0:01f31e923fe2	4248	* @}
Pawel Zarembski	0:01f31e923fe2	4249	/ / end of group NV_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4250
Pawel Zarembski	0:01f31e923fe2	4251
Pawel Zarembski	0:01f31e923fe2	4252	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4253	-- OSC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4254	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4255
Pawel Zarembski	0:01f31e923fe2	4256	/*!
Pawel Zarembski	0:01f31e923fe2	4257	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4258	* @{
Pawel Zarembski	0:01f31e923fe2	4259	*/
Pawel Zarembski	0:01f31e923fe2	4260
Pawel Zarembski	0:01f31e923fe2	4261	/** OSC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4262	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4263	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4264	} OSC_Type;
Pawel Zarembski	0:01f31e923fe2	4265
Pawel Zarembski	0:01f31e923fe2	4266	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4267	-- OSC Register Masks
Pawel Zarembski	0:01f31e923fe2	4268	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4269
Pawel Zarembski	0:01f31e923fe2	4270	/*!
Pawel Zarembski	0:01f31e923fe2	4271	* @addtogroup OSC_Register_Masks OSC Register Masks
Pawel Zarembski	0:01f31e923fe2	4272	* @{
Pawel Zarembski	0:01f31e923fe2	4273	*/
Pawel Zarembski	0:01f31e923fe2	4274
Pawel Zarembski	0:01f31e923fe2	4275	/! @name CR - OSC Control Register /
Pawel Zarembski	0:01f31e923fe2	4276	#define OSC_CR_SC16P_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4277	#define OSC_CR_SC16P_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4278	#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
Pawel Zarembski	0:01f31e923fe2	4279	#define OSC_CR_SC8P_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4280	#define OSC_CR_SC8P_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4281	#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
Pawel Zarembski	0:01f31e923fe2	4282	#define OSC_CR_SC4P_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4283	#define OSC_CR_SC4P_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4284	#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
Pawel Zarembski	0:01f31e923fe2	4285	#define OSC_CR_SC2P_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4286	#define OSC_CR_SC2P_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4287	#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
Pawel Zarembski	0:01f31e923fe2	4288	#define OSC_CR_EREFSTEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4289	#define OSC_CR_EREFSTEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4290	#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4291	#define OSC_CR_ERCLKEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4292	#define OSC_CR_ERCLKEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4293	#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4294
Pawel Zarembski	0:01f31e923fe2	4295
Pawel Zarembski	0:01f31e923fe2	4296	/*!
Pawel Zarembski	0:01f31e923fe2	4297	* @}
Pawel Zarembski	0:01f31e923fe2	4298	/ / end of group OSC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4299
Pawel Zarembski	0:01f31e923fe2	4300
Pawel Zarembski	0:01f31e923fe2	4301	/* OSC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4302	/** Peripheral OSC0 base address */
Pawel Zarembski	0:01f31e923fe2	4303	#define OSC0_BASE (0x40065000u)
Pawel Zarembski	0:01f31e923fe2	4304	/** Peripheral OSC0 base pointer */
Pawel Zarembski	0:01f31e923fe2	4305	#define OSC0 ((OSC_Type *)OSC0_BASE)
Pawel Zarembski	0:01f31e923fe2	4306	/** Array initializer of OSC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4307	#define OSC_BASE_ADDRS { OSC0_BASE }
Pawel Zarembski	0:01f31e923fe2	4308	/** Array initializer of OSC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4309	#define OSC_BASE_PTRS { OSC0 }
Pawel Zarembski	0:01f31e923fe2	4310
Pawel Zarembski	0:01f31e923fe2	4311	/*!
Pawel Zarembski	0:01f31e923fe2	4312	* @}
Pawel Zarembski	0:01f31e923fe2	4313	/ / end of group OSC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4314
Pawel Zarembski	0:01f31e923fe2	4315
Pawel Zarembski	0:01f31e923fe2	4316	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4317	-- PDB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4318	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4319
Pawel Zarembski	0:01f31e923fe2	4320	/*!
Pawel Zarembski	0:01f31e923fe2	4321	* @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4322	* @{
Pawel Zarembski	0:01f31e923fe2	4323	*/
Pawel Zarembski	0:01f31e923fe2	4324
Pawel Zarembski	0:01f31e923fe2	4325	/** PDB - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4326	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4327	__IO uint32_t SC; /*< Status and Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4328	__IO uint32_t MOD; /*< Modulus Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4329	__I uint32_t CNT; /*< Counter Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4330	__IO uint32_t IDLY; /*< Interrupt Delay Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	4331	struct { /* offset: 0x10, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	4332	__IO uint32_t C1; /*< Channel n Control Register 1, array offset: 0x10, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4333	__IO uint32_t S; /*< Channel n Status Register, array offset: 0x14, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4334	__IO uint32_t DLY[2]; /*< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index0x10, index20x4 /
Pawel Zarembski	0:01f31e923fe2	4335	} CH[1];
Pawel Zarembski	0:01f31e923fe2	4336	uint8_t RESERVED_0[368];
Pawel Zarembski	0:01f31e923fe2	4337	__IO uint32_t POEN; /*< Pulse-Out n Enable Register, offset: 0x190 /
Pawel Zarembski	0:01f31e923fe2	4338	__IO uint32_t PODLY[2]; /*< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4339	} PDB_Type;
Pawel Zarembski	0:01f31e923fe2	4340
Pawel Zarembski	0:01f31e923fe2	4341	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4342	-- PDB Register Masks
Pawel Zarembski	0:01f31e923fe2	4343	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4344
Pawel Zarembski	0:01f31e923fe2	4345	/*!
Pawel Zarembski	0:01f31e923fe2	4346	* @addtogroup PDB_Register_Masks PDB Register Masks
Pawel Zarembski	0:01f31e923fe2	4347	* @{
Pawel Zarembski	0:01f31e923fe2	4348	*/
Pawel Zarembski	0:01f31e923fe2	4349
Pawel Zarembski	0:01f31e923fe2	4350	/! @name SC - Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	4351	#define PDB_SC_LDOK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4352	#define PDB_SC_LDOK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4353	#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
Pawel Zarembski	0:01f31e923fe2	4354	#define PDB_SC_CONT_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4355	#define PDB_SC_CONT_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4356	#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
Pawel Zarembski	0:01f31e923fe2	4357	#define PDB_SC_MULT_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	4358	#define PDB_SC_MULT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4359	#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
Pawel Zarembski	0:01f31e923fe2	4360	#define PDB_SC_PDBIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4361	#define PDB_SC_PDBIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4362	#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4363	#define PDB_SC_PDBIF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4364	#define PDB_SC_PDBIF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4365	#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
Pawel Zarembski	0:01f31e923fe2	4366	#define PDB_SC_PDBEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4367	#define PDB_SC_PDBEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4368	#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4369	#define PDB_SC_TRGSEL_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	4370	#define PDB_SC_TRGSEL_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4371	#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4372	#define PDB_SC_PRESCALER_MASK (0x7000U)
Pawel Zarembski	0:01f31e923fe2	4373	#define PDB_SC_PRESCALER_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	4374	#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
Pawel Zarembski	0:01f31e923fe2	4375	#define PDB_SC_DMAEN_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	4376	#define PDB_SC_DMAEN_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	4377	#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4378	#define PDB_SC_SWTRIG_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	4379	#define PDB_SC_SWTRIG_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4380	#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	4381	#define PDB_SC_PDBEIE_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	4382	#define PDB_SC_PDBEIE_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	4383	#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4384	#define PDB_SC_LDMOD_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	4385	#define PDB_SC_LDMOD_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4386	#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	4387
Pawel Zarembski	0:01f31e923fe2	4388	/! @name MOD - Modulus Register /
Pawel Zarembski	0:01f31e923fe2	4389	#define PDB_MOD_MOD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4390	#define PDB_MOD_MOD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4391	#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
Pawel Zarembski	0:01f31e923fe2	4392
Pawel Zarembski	0:01f31e923fe2	4393	/! @name CNT - Counter Register /
Pawel Zarembski	0:01f31e923fe2	4394	#define PDB_CNT_CNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4395	#define PDB_CNT_CNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4396	#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
Pawel Zarembski	0:01f31e923fe2	4397
Pawel Zarembski	0:01f31e923fe2	4398	/! @name IDLY - Interrupt Delay Register /
Pawel Zarembski	0:01f31e923fe2	4399	#define PDB_IDLY_IDLY_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4400	#define PDB_IDLY_IDLY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4401	#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
Pawel Zarembski	0:01f31e923fe2	4402
Pawel Zarembski	0:01f31e923fe2	4403	/! @name C1 - Channel n Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	4404	#define PDB_C1_EN_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4405	#define PDB_C1_EN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4406	#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
Pawel Zarembski	0:01f31e923fe2	4407	#define PDB_C1_TOS_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	4408	#define PDB_C1_TOS_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4409	#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
Pawel Zarembski	0:01f31e923fe2	4410	#define PDB_C1_BB_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	4411	#define PDB_C1_BB_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4412	#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
Pawel Zarembski	0:01f31e923fe2	4413
Pawel Zarembski	0:01f31e923fe2	4414	/* The count of PDB_C1 */
Pawel Zarembski	0:01f31e923fe2	4415	#define PDB_C1_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	4416
Pawel Zarembski	0:01f31e923fe2	4417	/! @name S - Channel n Status Register /
Pawel Zarembski	0:01f31e923fe2	4418	#define PDB_S_ERR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4419	#define PDB_S_ERR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4420	#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
Pawel Zarembski	0:01f31e923fe2	4421	#define PDB_S_CF_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	4422	#define PDB_S_CF_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4423	#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
Pawel Zarembski	0:01f31e923fe2	4424
Pawel Zarembski	0:01f31e923fe2	4425	/* The count of PDB_S */
Pawel Zarembski	0:01f31e923fe2	4426	#define PDB_S_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	4427
Pawel Zarembski	0:01f31e923fe2	4428	/! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register /
Pawel Zarembski	0:01f31e923fe2	4429	#define PDB_DLY_DLY_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4430	#define PDB_DLY_DLY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4431	#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
Pawel Zarembski	0:01f31e923fe2	4432
Pawel Zarembski	0:01f31e923fe2	4433	/* The count of PDB_DLY */
Pawel Zarembski	0:01f31e923fe2	4434	#define PDB_DLY_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	4435
Pawel Zarembski	0:01f31e923fe2	4436	/* The count of PDB_DLY */
Pawel Zarembski	0:01f31e923fe2	4437	#define PDB_DLY_COUNT2 (2U)
Pawel Zarembski	0:01f31e923fe2	4438
Pawel Zarembski	0:01f31e923fe2	4439	/! @name POEN - Pulse-Out n Enable Register /
Pawel Zarembski	0:01f31e923fe2	4440	#define PDB_POEN_POEN_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4441	#define PDB_POEN_POEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4442	#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4443
Pawel Zarembski	0:01f31e923fe2	4444	/! @name PODLY - Pulse-Out n Delay Register /
Pawel Zarembski	0:01f31e923fe2	4445	#define PDB_PODLY_DLY2_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4446	#define PDB_PODLY_DLY2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4447	#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
Pawel Zarembski	0:01f31e923fe2	4448	#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	4449	#define PDB_PODLY_DLY1_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4450	#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
Pawel Zarembski	0:01f31e923fe2	4451
Pawel Zarembski	0:01f31e923fe2	4452	/* The count of PDB_PODLY */
Pawel Zarembski	0:01f31e923fe2	4453	#define PDB_PODLY_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	4454
Pawel Zarembski	0:01f31e923fe2	4455
Pawel Zarembski	0:01f31e923fe2	4456	/*!
Pawel Zarembski	0:01f31e923fe2	4457	* @}
Pawel Zarembski	0:01f31e923fe2	4458	/ / end of group PDB_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4459
Pawel Zarembski	0:01f31e923fe2	4460
Pawel Zarembski	0:01f31e923fe2	4461	/* PDB - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4462	/** Peripheral PDB0 base address */
Pawel Zarembski	0:01f31e923fe2	4463	#define PDB0_BASE (0x40036000u)
Pawel Zarembski	0:01f31e923fe2	4464	/** Peripheral PDB0 base pointer */
Pawel Zarembski	0:01f31e923fe2	4465	#define PDB0 ((PDB_Type *)PDB0_BASE)
Pawel Zarembski	0:01f31e923fe2	4466	/** Array initializer of PDB peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4467	#define PDB_BASE_ADDRS { PDB0_BASE }
Pawel Zarembski	0:01f31e923fe2	4468	/** Array initializer of PDB peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4469	#define PDB_BASE_PTRS { PDB0 }
Pawel Zarembski	0:01f31e923fe2	4470	/** Interrupt vectors for the PDB peripheral type */
Pawel Zarembski	0:01f31e923fe2	4471	#define PDB_IRQS { PDB0_IRQn }
Pawel Zarembski	0:01f31e923fe2	4472
Pawel Zarembski	0:01f31e923fe2	4473	/*!
Pawel Zarembski	0:01f31e923fe2	4474	* @}
Pawel Zarembski	0:01f31e923fe2	4475	/ / end of group PDB_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4476
Pawel Zarembski	0:01f31e923fe2	4477
Pawel Zarembski	0:01f31e923fe2	4478	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4479	-- PIT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4480	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4481
Pawel Zarembski	0:01f31e923fe2	4482	/*!
Pawel Zarembski	0:01f31e923fe2	4483	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4484	* @{
Pawel Zarembski	0:01f31e923fe2	4485	*/
Pawel Zarembski	0:01f31e923fe2	4486
Pawel Zarembski	0:01f31e923fe2	4487	/** PIT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4488	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4489	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4490	uint8_t RESERVED_0[252];
Pawel Zarembski	0:01f31e923fe2	4491	struct { /* offset: 0x100, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	4492	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4493	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4494	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4495	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	4496	} CHANNEL[4];
Pawel Zarembski	0:01f31e923fe2	4497	} PIT_Type;
Pawel Zarembski	0:01f31e923fe2	4498
Pawel Zarembski	0:01f31e923fe2	4499	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4500	-- PIT Register Masks
Pawel Zarembski	0:01f31e923fe2	4501	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4502
Pawel Zarembski	0:01f31e923fe2	4503	/*!
Pawel Zarembski	0:01f31e923fe2	4504	* @addtogroup PIT_Register_Masks PIT Register Masks
Pawel Zarembski	0:01f31e923fe2	4505	* @{
Pawel Zarembski	0:01f31e923fe2	4506	*/
Pawel Zarembski	0:01f31e923fe2	4507
Pawel Zarembski	0:01f31e923fe2	4508	/! @name MCR - PIT Module Control Register /
Pawel Zarembski	0:01f31e923fe2	4509	#define PIT_MCR_FRZ_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4510	#define PIT_MCR_FRZ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4511	#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
Pawel Zarembski	0:01f31e923fe2	4512	#define PIT_MCR_MDIS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4513	#define PIT_MCR_MDIS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4514	#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	4515
Pawel Zarembski	0:01f31e923fe2	4516	/! @name LDVAL - Timer Load Value Register /
Pawel Zarembski	0:01f31e923fe2	4517	#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4518	#define PIT_LDVAL_TSV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4519	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
Pawel Zarembski	0:01f31e923fe2	4520
Pawel Zarembski	0:01f31e923fe2	4521	/* The count of PIT_LDVAL */
Pawel Zarembski	0:01f31e923fe2	4522	#define PIT_LDVAL_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	4523
Pawel Zarembski	0:01f31e923fe2	4524	/! @name CVAL - Current Timer Value Register /
Pawel Zarembski	0:01f31e923fe2	4525	#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4526	#define PIT_CVAL_TVL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4527	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
Pawel Zarembski	0:01f31e923fe2	4528
Pawel Zarembski	0:01f31e923fe2	4529	/* The count of PIT_CVAL */
Pawel Zarembski	0:01f31e923fe2	4530	#define PIT_CVAL_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	4531
Pawel Zarembski	0:01f31e923fe2	4532	/! @name TCTRL - Timer Control Register /
Pawel Zarembski	0:01f31e923fe2	4533	#define PIT_TCTRL_TEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4534	#define PIT_TCTRL_TEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4535	#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4536	#define PIT_TCTRL_TIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4537	#define PIT_TCTRL_TIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4538	#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4539
Pawel Zarembski	0:01f31e923fe2	4540	/* The count of PIT_TCTRL */
Pawel Zarembski	0:01f31e923fe2	4541	#define PIT_TCTRL_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	4542
Pawel Zarembski	0:01f31e923fe2	4543	/! @name TFLG - Timer Flag Register /
Pawel Zarembski	0:01f31e923fe2	4544	#define PIT_TFLG_TIF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4545	#define PIT_TFLG_TIF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4546	#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
Pawel Zarembski	0:01f31e923fe2	4547
Pawel Zarembski	0:01f31e923fe2	4548	/* The count of PIT_TFLG */
Pawel Zarembski	0:01f31e923fe2	4549	#define PIT_TFLG_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	4550
Pawel Zarembski	0:01f31e923fe2	4551
Pawel Zarembski	0:01f31e923fe2	4552	/*!
Pawel Zarembski	0:01f31e923fe2	4553	* @}
Pawel Zarembski	0:01f31e923fe2	4554	/ / end of group PIT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4555
Pawel Zarembski	0:01f31e923fe2	4556
Pawel Zarembski	0:01f31e923fe2	4557	/* PIT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4558	/** Peripheral PIT base address */
Pawel Zarembski	0:01f31e923fe2	4559	#define PIT_BASE (0x40037000u)
Pawel Zarembski	0:01f31e923fe2	4560	/** Peripheral PIT base pointer */
Pawel Zarembski	0:01f31e923fe2	4561	#define PIT ((PIT_Type *)PIT_BASE)
Pawel Zarembski	0:01f31e923fe2	4562	/** Array initializer of PIT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4563	#define PIT_BASE_ADDRS { PIT_BASE }
Pawel Zarembski	0:01f31e923fe2	4564	/** Array initializer of PIT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4565	#define PIT_BASE_PTRS { PIT }
Pawel Zarembski	0:01f31e923fe2	4566	/** Interrupt vectors for the PIT peripheral type */
Pawel Zarembski	0:01f31e923fe2	4567	#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
Pawel Zarembski	0:01f31e923fe2	4568
Pawel Zarembski	0:01f31e923fe2	4569	/*!
Pawel Zarembski	0:01f31e923fe2	4570	* @}
Pawel Zarembski	0:01f31e923fe2	4571	/ / end of group PIT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4572
Pawel Zarembski	0:01f31e923fe2	4573
Pawel Zarembski	0:01f31e923fe2	4574	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4575	-- PMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4576	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4577
Pawel Zarembski	0:01f31e923fe2	4578	/*!
Pawel Zarembski	0:01f31e923fe2	4579	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4580	* @{
Pawel Zarembski	0:01f31e923fe2	4581	*/
Pawel Zarembski	0:01f31e923fe2	4582
Pawel Zarembski	0:01f31e923fe2	4583	/** PMC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4584	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4585	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status and Control 1 Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4586	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status and Control 2 Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4587	__IO uint8_t REGSC; /*< Regulator Status and Control Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	4588	} PMC_Type;
Pawel Zarembski	0:01f31e923fe2	4589
Pawel Zarembski	0:01f31e923fe2	4590	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4591	-- PMC Register Masks
Pawel Zarembski	0:01f31e923fe2	4592	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4593
Pawel Zarembski	0:01f31e923fe2	4594	/*!
Pawel Zarembski	0:01f31e923fe2	4595	* @addtogroup PMC_Register_Masks PMC Register Masks
Pawel Zarembski	0:01f31e923fe2	4596	* @{
Pawel Zarembski	0:01f31e923fe2	4597	*/
Pawel Zarembski	0:01f31e923fe2	4598
Pawel Zarembski	0:01f31e923fe2	4599	/! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register /
Pawel Zarembski	0:01f31e923fe2	4600	#define PMC_LVDSC1_LVDV_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	4601	#define PMC_LVDSC1_LVDV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4602	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
Pawel Zarembski	0:01f31e923fe2	4603	#define PMC_LVDSC1_LVDRE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4604	#define PMC_LVDSC1_LVDRE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4605	#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
Pawel Zarembski	0:01f31e923fe2	4606	#define PMC_LVDSC1_LVDIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4607	#define PMC_LVDSC1_LVDIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4608	#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4609	#define PMC_LVDSC1_LVDACK_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4610	#define PMC_LVDSC1_LVDACK_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4611	#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
Pawel Zarembski	0:01f31e923fe2	4612	#define PMC_LVDSC1_LVDF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4613	#define PMC_LVDSC1_LVDF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4614	#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
Pawel Zarembski	0:01f31e923fe2	4615
Pawel Zarembski	0:01f31e923fe2	4616	/! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register /
Pawel Zarembski	0:01f31e923fe2	4617	#define PMC_LVDSC2_LVWV_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	4618	#define PMC_LVDSC2_LVWV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4619	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
Pawel Zarembski	0:01f31e923fe2	4620	#define PMC_LVDSC2_LVWIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4621	#define PMC_LVDSC2_LVWIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4622	#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4623	#define PMC_LVDSC2_LVWACK_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4624	#define PMC_LVDSC2_LVWACK_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4625	#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
Pawel Zarembski	0:01f31e923fe2	4626	#define PMC_LVDSC2_LVWF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4627	#define PMC_LVDSC2_LVWF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4628	#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
Pawel Zarembski	0:01f31e923fe2	4629
Pawel Zarembski	0:01f31e923fe2	4630	/! @name REGSC - Regulator Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	4631	#define PMC_REGSC_BGBE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4632	#define PMC_REGSC_BGBE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4633	#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
Pawel Zarembski	0:01f31e923fe2	4634	#define PMC_REGSC_REGONS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4635	#define PMC_REGSC_REGONS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4636	#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
Pawel Zarembski	0:01f31e923fe2	4637	#define PMC_REGSC_ACKISO_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4638	#define PMC_REGSC_ACKISO_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4639	#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
Pawel Zarembski	0:01f31e923fe2	4640
Pawel Zarembski	0:01f31e923fe2	4641
Pawel Zarembski	0:01f31e923fe2	4642	/*!
Pawel Zarembski	0:01f31e923fe2	4643	* @}
Pawel Zarembski	0:01f31e923fe2	4644	/ / end of group PMC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4645
Pawel Zarembski	0:01f31e923fe2	4646
Pawel Zarembski	0:01f31e923fe2	4647	/* PMC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4648	/** Peripheral PMC base address */
Pawel Zarembski	0:01f31e923fe2	4649	#define PMC_BASE (0x4007D000u)
Pawel Zarembski	0:01f31e923fe2	4650	/** Peripheral PMC base pointer */
Pawel Zarembski	0:01f31e923fe2	4651	#define PMC ((PMC_Type *)PMC_BASE)
Pawel Zarembski	0:01f31e923fe2	4652	/** Array initializer of PMC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4653	#define PMC_BASE_ADDRS { PMC_BASE }
Pawel Zarembski	0:01f31e923fe2	4654	/** Array initializer of PMC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4655	#define PMC_BASE_PTRS { PMC }
Pawel Zarembski	0:01f31e923fe2	4656	/** Interrupt vectors for the PMC peripheral type */
Pawel Zarembski	0:01f31e923fe2	4657	#define PMC_IRQS { LVD_LVW_IRQn }
Pawel Zarembski	0:01f31e923fe2	4658
Pawel Zarembski	0:01f31e923fe2	4659	/*!
Pawel Zarembski	0:01f31e923fe2	4660	* @}
Pawel Zarembski	0:01f31e923fe2	4661	/ / end of group PMC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4662
Pawel Zarembski	0:01f31e923fe2	4663
Pawel Zarembski	0:01f31e923fe2	4664	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4665	-- PORT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4666	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4667
Pawel Zarembski	0:01f31e923fe2	4668	/*!
Pawel Zarembski	0:01f31e923fe2	4669	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4670	* @{
Pawel Zarembski	0:01f31e923fe2	4671	*/
Pawel Zarembski	0:01f31e923fe2	4672
Pawel Zarembski	0:01f31e923fe2	4673	/** PORT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4674	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4675	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4676	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	4677	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	4678	uint8_t RESERVED_0[24];
Pawel Zarembski	0:01f31e923fe2	4679	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
Pawel Zarembski	0:01f31e923fe2	4680	uint8_t RESERVED_1[28];
Pawel Zarembski	0:01f31e923fe2	4681	__IO uint32_t DFER; /*< Digital Filter Enable Register, offset: 0xC0 /
Pawel Zarembski	0:01f31e923fe2	4682	__IO uint32_t DFCR; /*< Digital Filter Clock Register, offset: 0xC4 /
Pawel Zarembski	0:01f31e923fe2	4683	__IO uint32_t DFWR; /*< Digital Filter Width Register, offset: 0xC8 /
Pawel Zarembski	0:01f31e923fe2	4684	} PORT_Type;
Pawel Zarembski	0:01f31e923fe2	4685
Pawel Zarembski	0:01f31e923fe2	4686	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4687	-- PORT Register Masks
Pawel Zarembski	0:01f31e923fe2	4688	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4689
Pawel Zarembski	0:01f31e923fe2	4690	/*!
Pawel Zarembski	0:01f31e923fe2	4691	* @addtogroup PORT_Register_Masks PORT Register Masks
Pawel Zarembski	0:01f31e923fe2	4692	* @{
Pawel Zarembski	0:01f31e923fe2	4693	*/
Pawel Zarembski	0:01f31e923fe2	4694
Pawel Zarembski	0:01f31e923fe2	4695	/! @name PCR - Pin Control Register n /
Pawel Zarembski	0:01f31e923fe2	4696	#define PORT_PCR_PS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4697	#define PORT_PCR_PS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4698	#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	4699	#define PORT_PCR_PE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4700	#define PORT_PCR_PE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4701	#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
Pawel Zarembski	0:01f31e923fe2	4702	#define PORT_PCR_SRE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4703	#define PORT_PCR_SRE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4704	#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
Pawel Zarembski	0:01f31e923fe2	4705	#define PORT_PCR_PFE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4706	#define PORT_PCR_PFE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4707	#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
Pawel Zarembski	0:01f31e923fe2	4708	#define PORT_PCR_ODE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4709	#define PORT_PCR_ODE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4710	#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4711	#define PORT_PCR_DSE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4712	#define PORT_PCR_DSE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4713	#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
Pawel Zarembski	0:01f31e923fe2	4714	#define PORT_PCR_MUX_MASK (0x700U)
Pawel Zarembski	0:01f31e923fe2	4715	#define PORT_PCR_MUX_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4716	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
Pawel Zarembski	0:01f31e923fe2	4717	#define PORT_PCR_LK_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	4718	#define PORT_PCR_LK_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	4719	#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
Pawel Zarembski	0:01f31e923fe2	4720	#define PORT_PCR_IRQC_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	4721	#define PORT_PCR_IRQC_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4722	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
Pawel Zarembski	0:01f31e923fe2	4723	#define PORT_PCR_ISF_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	4724	#define PORT_PCR_ISF_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4725	#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
Pawel Zarembski	0:01f31e923fe2	4726
Pawel Zarembski	0:01f31e923fe2	4727	/* The count of PORT_PCR */
Pawel Zarembski	0:01f31e923fe2	4728	#define PORT_PCR_COUNT (32U)
Pawel Zarembski	0:01f31e923fe2	4729
Pawel Zarembski	0:01f31e923fe2	4730	/! @name GPCLR - Global Pin Control Low Register /
Pawel Zarembski	0:01f31e923fe2	4731	#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4732	#define PORT_GPCLR_GPWD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4733	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
Pawel Zarembski	0:01f31e923fe2	4734	#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	4735	#define PORT_GPCLR_GPWE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4736	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
Pawel Zarembski	0:01f31e923fe2	4737
Pawel Zarembski	0:01f31e923fe2	4738	/! @name GPCHR - Global Pin Control High Register /
Pawel Zarembski	0:01f31e923fe2	4739	#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4740	#define PORT_GPCHR_GPWD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4741	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
Pawel Zarembski	0:01f31e923fe2	4742	#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	4743	#define PORT_GPCHR_GPWE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4744	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
Pawel Zarembski	0:01f31e923fe2	4745
Pawel Zarembski	0:01f31e923fe2	4746	/! @name ISFR - Interrupt Status Flag Register /
Pawel Zarembski	0:01f31e923fe2	4747	#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4748	#define PORT_ISFR_ISF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4749	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
Pawel Zarembski	0:01f31e923fe2	4750
Pawel Zarembski	0:01f31e923fe2	4751	/! @name DFER - Digital Filter Enable Register /
Pawel Zarembski	0:01f31e923fe2	4752	#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4753	#define PORT_DFER_DFE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4754	#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
Pawel Zarembski	0:01f31e923fe2	4755
Pawel Zarembski	0:01f31e923fe2	4756	/! @name DFCR - Digital Filter Clock Register /
Pawel Zarembski	0:01f31e923fe2	4757	#define PORT_DFCR_CS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4758	#define PORT_DFCR_CS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4759	#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
Pawel Zarembski	0:01f31e923fe2	4760
Pawel Zarembski	0:01f31e923fe2	4761	/! @name DFWR - Digital Filter Width Register /
Pawel Zarembski	0:01f31e923fe2	4762	#define PORT_DFWR_FILT_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	4763	#define PORT_DFWR_FILT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4764	#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
Pawel Zarembski	0:01f31e923fe2	4765
Pawel Zarembski	0:01f31e923fe2	4766
Pawel Zarembski	0:01f31e923fe2	4767	/*!
Pawel Zarembski	0:01f31e923fe2	4768	* @}
Pawel Zarembski	0:01f31e923fe2	4769	/ / end of group PORT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4770
Pawel Zarembski	0:01f31e923fe2	4771
Pawel Zarembski	0:01f31e923fe2	4772	/* PORT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4773	/** Peripheral PORTA base address */
Pawel Zarembski	0:01f31e923fe2	4774	#define PORTA_BASE (0x40049000u)
Pawel Zarembski	0:01f31e923fe2	4775	/** Peripheral PORTA base pointer */
Pawel Zarembski	0:01f31e923fe2	4776	#define PORTA ((PORT_Type *)PORTA_BASE)
Pawel Zarembski	0:01f31e923fe2	4777	/** Peripheral PORTB base address */
Pawel Zarembski	0:01f31e923fe2	4778	#define PORTB_BASE (0x4004A000u)
Pawel Zarembski	0:01f31e923fe2	4779	/** Peripheral PORTB base pointer */
Pawel Zarembski	0:01f31e923fe2	4780	#define PORTB ((PORT_Type *)PORTB_BASE)
Pawel Zarembski	0:01f31e923fe2	4781	/** Peripheral PORTC base address */
Pawel Zarembski	0:01f31e923fe2	4782	#define PORTC_BASE (0x4004B000u)
Pawel Zarembski	0:01f31e923fe2	4783	/** Peripheral PORTC base pointer */
Pawel Zarembski	0:01f31e923fe2	4784	#define PORTC ((PORT_Type *)PORTC_BASE)
Pawel Zarembski	0:01f31e923fe2	4785	/** Peripheral PORTD base address */
Pawel Zarembski	0:01f31e923fe2	4786	#define PORTD_BASE (0x4004C000u)
Pawel Zarembski	0:01f31e923fe2	4787	/** Peripheral PORTD base pointer */
Pawel Zarembski	0:01f31e923fe2	4788	#define PORTD ((PORT_Type *)PORTD_BASE)
Pawel Zarembski	0:01f31e923fe2	4789	/** Peripheral PORTE base address */
Pawel Zarembski	0:01f31e923fe2	4790	#define PORTE_BASE (0x4004D000u)
Pawel Zarembski	0:01f31e923fe2	4791	/** Peripheral PORTE base pointer */
Pawel Zarembski	0:01f31e923fe2	4792	#define PORTE ((PORT_Type *)PORTE_BASE)
Pawel Zarembski	0:01f31e923fe2	4793	/** Array initializer of PORT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4794	#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
Pawel Zarembski	0:01f31e923fe2	4795	/** Array initializer of PORT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4796	#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
Pawel Zarembski	0:01f31e923fe2	4797	/** Interrupt vectors for the PORT peripheral type */
Pawel Zarembski	0:01f31e923fe2	4798	#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
Pawel Zarembski	0:01f31e923fe2	4799
Pawel Zarembski	0:01f31e923fe2	4800	/*!
Pawel Zarembski	0:01f31e923fe2	4801	* @}
Pawel Zarembski	0:01f31e923fe2	4802	/ / end of group PORT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4803
Pawel Zarembski	0:01f31e923fe2	4804
Pawel Zarembski	0:01f31e923fe2	4805	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4806	-- RCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4807	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4808
Pawel Zarembski	0:01f31e923fe2	4809	/*!
Pawel Zarembski	0:01f31e923fe2	4810	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4811	* @{
Pawel Zarembski	0:01f31e923fe2	4812	*/
Pawel Zarembski	0:01f31e923fe2	4813
Pawel Zarembski	0:01f31e923fe2	4814	/** RCM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4815	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4816	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4817	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4818	uint8_t RESERVED_0[2];
Pawel Zarembski	0:01f31e923fe2	4819	__IO uint8_t RPFC; /*< Reset Pin Filter Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4820	__IO uint8_t RPFW; /*< Reset Pin Filter Width Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	4821	uint8_t RESERVED_1[1];
Pawel Zarembski	0:01f31e923fe2	4822	__I uint8_t MR; /*< Mode Register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	4823	} RCM_Type;
Pawel Zarembski	0:01f31e923fe2	4824
Pawel Zarembski	0:01f31e923fe2	4825	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4826	-- RCM Register Masks
Pawel Zarembski	0:01f31e923fe2	4827	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4828
Pawel Zarembski	0:01f31e923fe2	4829	/*!
Pawel Zarembski	0:01f31e923fe2	4830	* @addtogroup RCM_Register_Masks RCM Register Masks
Pawel Zarembski	0:01f31e923fe2	4831	* @{
Pawel Zarembski	0:01f31e923fe2	4832	*/
Pawel Zarembski	0:01f31e923fe2	4833
Pawel Zarembski	0:01f31e923fe2	4834	/! @name SRS0 - System Reset Status Register 0 /
Pawel Zarembski	0:01f31e923fe2	4835	#define RCM_SRS0_WAKEUP_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4836	#define RCM_SRS0_WAKEUP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4837	#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
Pawel Zarembski	0:01f31e923fe2	4838	#define RCM_SRS0_LVD_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4839	#define RCM_SRS0_LVD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4840	#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
Pawel Zarembski	0:01f31e923fe2	4841	#define RCM_SRS0_LOC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4842	#define RCM_SRS0_LOC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4843	#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
Pawel Zarembski	0:01f31e923fe2	4844	#define RCM_SRS0_LOL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4845	#define RCM_SRS0_LOL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4846	#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
Pawel Zarembski	0:01f31e923fe2	4847	#define RCM_SRS0_WDOG_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4848	#define RCM_SRS0_WDOG_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4849	#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
Pawel Zarembski	0:01f31e923fe2	4850	#define RCM_SRS0_PIN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4851	#define RCM_SRS0_PIN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4852	#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
Pawel Zarembski	0:01f31e923fe2	4853	#define RCM_SRS0_POR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4854	#define RCM_SRS0_POR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4855	#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
Pawel Zarembski	0:01f31e923fe2	4856
Pawel Zarembski	0:01f31e923fe2	4857	/! @name SRS1 - System Reset Status Register 1 /
Pawel Zarembski	0:01f31e923fe2	4858	#define RCM_SRS1_JTAG_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4859	#define RCM_SRS1_JTAG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4860	#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
Pawel Zarembski	0:01f31e923fe2	4861	#define RCM_SRS1_LOCKUP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4862	#define RCM_SRS1_LOCKUP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4863	#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
Pawel Zarembski	0:01f31e923fe2	4864	#define RCM_SRS1_SW_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4865	#define RCM_SRS1_SW_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4866	#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
Pawel Zarembski	0:01f31e923fe2	4867	#define RCM_SRS1_MDM_AP_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4868	#define RCM_SRS1_MDM_AP_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4869	#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
Pawel Zarembski	0:01f31e923fe2	4870	#define RCM_SRS1_EZPT_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4871	#define RCM_SRS1_EZPT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4872	#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
Pawel Zarembski	0:01f31e923fe2	4873	#define RCM_SRS1_SACKERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4874	#define RCM_SRS1_SACKERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4875	#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
Pawel Zarembski	0:01f31e923fe2	4876
Pawel Zarembski	0:01f31e923fe2	4877	/! @name RPFC - Reset Pin Filter Control Register /
Pawel Zarembski	0:01f31e923fe2	4878	#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	4879	#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4880	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
Pawel Zarembski	0:01f31e923fe2	4881	#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4882	#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4883	#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
Pawel Zarembski	0:01f31e923fe2	4884
Pawel Zarembski	0:01f31e923fe2	4885	/! @name RPFW - Reset Pin Filter Width Register /
Pawel Zarembski	0:01f31e923fe2	4886	#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	4887	#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4888	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4889
Pawel Zarembski	0:01f31e923fe2	4890	/! @name MR - Mode Register /
Pawel Zarembski	0:01f31e923fe2	4891	#define RCM_MR_EZP_MS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4892	#define RCM_MR_EZP_MS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4893	#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
Pawel Zarembski	0:01f31e923fe2	4894
Pawel Zarembski	0:01f31e923fe2	4895
Pawel Zarembski	0:01f31e923fe2	4896	/*!
Pawel Zarembski	0:01f31e923fe2	4897	* @}
Pawel Zarembski	0:01f31e923fe2	4898	/ / end of group RCM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4899
Pawel Zarembski	0:01f31e923fe2	4900
Pawel Zarembski	0:01f31e923fe2	4901	/* RCM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4902	/** Peripheral RCM base address */
Pawel Zarembski	0:01f31e923fe2	4903	#define RCM_BASE (0x4007F000u)
Pawel Zarembski	0:01f31e923fe2	4904	/** Peripheral RCM base pointer */
Pawel Zarembski	0:01f31e923fe2	4905	#define RCM ((RCM_Type *)RCM_BASE)
Pawel Zarembski	0:01f31e923fe2	4906	/** Array initializer of RCM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4907	#define RCM_BASE_ADDRS { RCM_BASE }
Pawel Zarembski	0:01f31e923fe2	4908	/** Array initializer of RCM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4909	#define RCM_BASE_PTRS { RCM }
Pawel Zarembski	0:01f31e923fe2	4910
Pawel Zarembski	0:01f31e923fe2	4911	/*!
Pawel Zarembski	0:01f31e923fe2	4912	* @}
Pawel Zarembski	0:01f31e923fe2	4913	/ / end of group RCM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4914
Pawel Zarembski	0:01f31e923fe2	4915
Pawel Zarembski	0:01f31e923fe2	4916	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4917	-- RFSYS Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4918	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4919
Pawel Zarembski	0:01f31e923fe2	4920	/*!
Pawel Zarembski	0:01f31e923fe2	4921	* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4922	* @{
Pawel Zarembski	0:01f31e923fe2	4923	*/
Pawel Zarembski	0:01f31e923fe2	4924
Pawel Zarembski	0:01f31e923fe2	4925	/** RFSYS - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4926	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4927	__IO uint32_t REG[8]; /*< Register file register, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4928	} RFSYS_Type;
Pawel Zarembski	0:01f31e923fe2	4929
Pawel Zarembski	0:01f31e923fe2	4930	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4931	-- RFSYS Register Masks
Pawel Zarembski	0:01f31e923fe2	4932	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4933
Pawel Zarembski	0:01f31e923fe2	4934	/*!
Pawel Zarembski	0:01f31e923fe2	4935	* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
Pawel Zarembski	0:01f31e923fe2	4936	* @{
Pawel Zarembski	0:01f31e923fe2	4937	*/
Pawel Zarembski	0:01f31e923fe2	4938
Pawel Zarembski	0:01f31e923fe2	4939	/! @name REG - Register file register /
Pawel Zarembski	0:01f31e923fe2	4940	#define RFSYS_REG_LL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4941	#define RFSYS_REG_LL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4942	#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
Pawel Zarembski	0:01f31e923fe2	4943	#define RFSYS_REG_LH_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	4944	#define RFSYS_REG_LH_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4945	#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
Pawel Zarembski	0:01f31e923fe2	4946	#define RFSYS_REG_HL_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	4947	#define RFSYS_REG_HL_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4948	#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
Pawel Zarembski	0:01f31e923fe2	4949	#define RFSYS_REG_HH_MASK (0xFF000000U)
Pawel Zarembski	0:01f31e923fe2	4950	#define RFSYS_REG_HH_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4951	#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
Pawel Zarembski	0:01f31e923fe2	4952
Pawel Zarembski	0:01f31e923fe2	4953	/* The count of RFSYS_REG */
Pawel Zarembski	0:01f31e923fe2	4954	#define RFSYS_REG_COUNT (8U)
Pawel Zarembski	0:01f31e923fe2	4955
Pawel Zarembski	0:01f31e923fe2	4956
Pawel Zarembski	0:01f31e923fe2	4957	/*!
Pawel Zarembski	0:01f31e923fe2	4958	* @}
Pawel Zarembski	0:01f31e923fe2	4959	/ / end of group RFSYS_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4960
Pawel Zarembski	0:01f31e923fe2	4961
Pawel Zarembski	0:01f31e923fe2	4962	/* RFSYS - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4963	/** Peripheral RFSYS base address */
Pawel Zarembski	0:01f31e923fe2	4964	#define RFSYS_BASE (0x40041000u)
Pawel Zarembski	0:01f31e923fe2	4965	/** Peripheral RFSYS base pointer */
Pawel Zarembski	0:01f31e923fe2	4966	#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
Pawel Zarembski	0:01f31e923fe2	4967	/** Array initializer of RFSYS peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4968	#define RFSYS_BASE_ADDRS { RFSYS_BASE }
Pawel Zarembski	0:01f31e923fe2	4969	/** Array initializer of RFSYS peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4970	#define RFSYS_BASE_PTRS { RFSYS }
Pawel Zarembski	0:01f31e923fe2	4971
Pawel Zarembski	0:01f31e923fe2	4972	/*!
Pawel Zarembski	0:01f31e923fe2	4973	* @}
Pawel Zarembski	0:01f31e923fe2	4974	/ / end of group RFSYS_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4975
Pawel Zarembski	0:01f31e923fe2	4976
Pawel Zarembski	0:01f31e923fe2	4977	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4978	-- RFVBAT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4979	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4980
Pawel Zarembski	0:01f31e923fe2	4981	/*!
Pawel Zarembski	0:01f31e923fe2	4982	* @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4983	* @{
Pawel Zarembski	0:01f31e923fe2	4984	*/
Pawel Zarembski	0:01f31e923fe2	4985
Pawel Zarembski	0:01f31e923fe2	4986	/** RFVBAT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4987	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4988	__IO uint32_t REG[8]; /*< VBAT register file register, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4989	} RFVBAT_Type;
Pawel Zarembski	0:01f31e923fe2	4990
Pawel Zarembski	0:01f31e923fe2	4991	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4992	-- RFVBAT Register Masks
Pawel Zarembski	0:01f31e923fe2	4993	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4994
Pawel Zarembski	0:01f31e923fe2	4995	/*!
Pawel Zarembski	0:01f31e923fe2	4996	* @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
Pawel Zarembski	0:01f31e923fe2	4997	* @{
Pawel Zarembski	0:01f31e923fe2	4998	*/
Pawel Zarembski	0:01f31e923fe2	4999
Pawel Zarembski	0:01f31e923fe2	5000	/! @name REG - VBAT register file register /
Pawel Zarembski	0:01f31e923fe2	5001	#define RFVBAT_REG_LL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5002	#define RFVBAT_REG_LL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5003	#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
Pawel Zarembski	0:01f31e923fe2	5004	#define RFVBAT_REG_LH_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	5005	#define RFVBAT_REG_LH_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5006	#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
Pawel Zarembski	0:01f31e923fe2	5007	#define RFVBAT_REG_HL_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	5008	#define RFVBAT_REG_HL_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5009	#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
Pawel Zarembski	0:01f31e923fe2	5010	#define RFVBAT_REG_HH_MASK (0xFF000000U)
Pawel Zarembski	0:01f31e923fe2	5011	#define RFVBAT_REG_HH_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5012	#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
Pawel Zarembski	0:01f31e923fe2	5013
Pawel Zarembski	0:01f31e923fe2	5014	/* The count of RFVBAT_REG */
Pawel Zarembski	0:01f31e923fe2	5015	#define RFVBAT_REG_COUNT (8U)
Pawel Zarembski	0:01f31e923fe2	5016
Pawel Zarembski	0:01f31e923fe2	5017
Pawel Zarembski	0:01f31e923fe2	5018	/*!
Pawel Zarembski	0:01f31e923fe2	5019	* @}
Pawel Zarembski	0:01f31e923fe2	5020	/ / end of group RFVBAT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5021
Pawel Zarembski	0:01f31e923fe2	5022
Pawel Zarembski	0:01f31e923fe2	5023	/* RFVBAT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5024	/** Peripheral RFVBAT base address */
Pawel Zarembski	0:01f31e923fe2	5025	#define RFVBAT_BASE (0x4003E000u)
Pawel Zarembski	0:01f31e923fe2	5026	/** Peripheral RFVBAT base pointer */
Pawel Zarembski	0:01f31e923fe2	5027	#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
Pawel Zarembski	0:01f31e923fe2	5028	/** Array initializer of RFVBAT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5029	#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
Pawel Zarembski	0:01f31e923fe2	5030	/** Array initializer of RFVBAT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5031	#define RFVBAT_BASE_PTRS { RFVBAT }
Pawel Zarembski	0:01f31e923fe2	5032
Pawel Zarembski	0:01f31e923fe2	5033	/*!
Pawel Zarembski	0:01f31e923fe2	5034	* @}
Pawel Zarembski	0:01f31e923fe2	5035	/ / end of group RFVBAT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5036
Pawel Zarembski	0:01f31e923fe2	5037
Pawel Zarembski	0:01f31e923fe2	5038	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5039	-- RTC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5040	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5041
Pawel Zarembski	0:01f31e923fe2	5042	/*!
Pawel Zarembski	0:01f31e923fe2	5043	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5044	* @{
Pawel Zarembski	0:01f31e923fe2	5045	*/
Pawel Zarembski	0:01f31e923fe2	5046
Pawel Zarembski	0:01f31e923fe2	5047	/** RTC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5048	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5049	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5050	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5051	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	5052	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	5053	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	5054	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	5055	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	5056	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	5057	uint8_t RESERVED_0[2016];
Pawel Zarembski	0:01f31e923fe2	5058	__IO uint32_t WAR; /*< RTC Write Access Register, offset: 0x800 /
Pawel Zarembski	0:01f31e923fe2	5059	__IO uint32_t RAR; /*< RTC Read Access Register, offset: 0x804 /
Pawel Zarembski	0:01f31e923fe2	5060	} RTC_Type;
Pawel Zarembski	0:01f31e923fe2	5061
Pawel Zarembski	0:01f31e923fe2	5062	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5063	-- RTC Register Masks
Pawel Zarembski	0:01f31e923fe2	5064	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5065
Pawel Zarembski	0:01f31e923fe2	5066	/*!
Pawel Zarembski	0:01f31e923fe2	5067	* @addtogroup RTC_Register_Masks RTC Register Masks
Pawel Zarembski	0:01f31e923fe2	5068	* @{
Pawel Zarembski	0:01f31e923fe2	5069	*/
Pawel Zarembski	0:01f31e923fe2	5070
Pawel Zarembski	0:01f31e923fe2	5071	/! @name TSR - RTC Time Seconds Register /
Pawel Zarembski	0:01f31e923fe2	5072	#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5073	#define RTC_TSR_TSR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5074	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
Pawel Zarembski	0:01f31e923fe2	5075
Pawel Zarembski	0:01f31e923fe2	5076	/! @name TPR - RTC Time Prescaler Register /
Pawel Zarembski	0:01f31e923fe2	5077	#define RTC_TPR_TPR_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5078	#define RTC_TPR_TPR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5079	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
Pawel Zarembski	0:01f31e923fe2	5080
Pawel Zarembski	0:01f31e923fe2	5081	/! @name TAR - RTC Time Alarm Register /
Pawel Zarembski	0:01f31e923fe2	5082	#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5083	#define RTC_TAR_TAR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5084	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
Pawel Zarembski	0:01f31e923fe2	5085
Pawel Zarembski	0:01f31e923fe2	5086	/! @name TCR - RTC Time Compensation Register /
Pawel Zarembski	0:01f31e923fe2	5087	#define RTC_TCR_TCR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5088	#define RTC_TCR_TCR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5089	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
Pawel Zarembski	0:01f31e923fe2	5090	#define RTC_TCR_CIR_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	5091	#define RTC_TCR_CIR_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5092	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
Pawel Zarembski	0:01f31e923fe2	5093	#define RTC_TCR_TCV_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	5094	#define RTC_TCR_TCV_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5095	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
Pawel Zarembski	0:01f31e923fe2	5096	#define RTC_TCR_CIC_MASK (0xFF000000U)
Pawel Zarembski	0:01f31e923fe2	5097	#define RTC_TCR_CIC_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5098	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
Pawel Zarembski	0:01f31e923fe2	5099
Pawel Zarembski	0:01f31e923fe2	5100	/! @name CR - RTC Control Register /
Pawel Zarembski	0:01f31e923fe2	5101	#define RTC_CR_SWR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5102	#define RTC_CR_SWR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5103	#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
Pawel Zarembski	0:01f31e923fe2	5104	#define RTC_CR_WPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5105	#define RTC_CR_WPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5106	#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
Pawel Zarembski	0:01f31e923fe2	5107	#define RTC_CR_SUP_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5108	#define RTC_CR_SUP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5109	#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
Pawel Zarembski	0:01f31e923fe2	5110	#define RTC_CR_UM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5111	#define RTC_CR_UM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5112	#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
Pawel Zarembski	0:01f31e923fe2	5113	#define RTC_CR_OSCE_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	5114	#define RTC_CR_OSCE_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5115	#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
Pawel Zarembski	0:01f31e923fe2	5116	#define RTC_CR_CLKO_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	5117	#define RTC_CR_CLKO_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	5118	#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
Pawel Zarembski	0:01f31e923fe2	5119	#define RTC_CR_SC16P_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	5120	#define RTC_CR_SC16P_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	5121	#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
Pawel Zarembski	0:01f31e923fe2	5122	#define RTC_CR_SC8P_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	5123	#define RTC_CR_SC8P_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	5124	#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
Pawel Zarembski	0:01f31e923fe2	5125	#define RTC_CR_SC4P_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5126	#define RTC_CR_SC4P_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5127	#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
Pawel Zarembski	0:01f31e923fe2	5128	#define RTC_CR_SC2P_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	5129	#define RTC_CR_SC2P_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	5130	#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
Pawel Zarembski	0:01f31e923fe2	5131
Pawel Zarembski	0:01f31e923fe2	5132	/! @name SR - RTC Status Register /
Pawel Zarembski	0:01f31e923fe2	5133	#define RTC_SR_TIF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5134	#define RTC_SR_TIF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5135	#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
Pawel Zarembski	0:01f31e923fe2	5136	#define RTC_SR_TOF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5137	#define RTC_SR_TOF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5138	#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
Pawel Zarembski	0:01f31e923fe2	5139	#define RTC_SR_TAF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5140	#define RTC_SR_TAF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5141	#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
Pawel Zarembski	0:01f31e923fe2	5142	#define RTC_SR_TCE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5143	#define RTC_SR_TCE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5144	#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
Pawel Zarembski	0:01f31e923fe2	5145
Pawel Zarembski	0:01f31e923fe2	5146	/! @name LR - RTC Lock Register /
Pawel Zarembski	0:01f31e923fe2	5147	#define RTC_LR_TCL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5148	#define RTC_LR_TCL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5149	#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
Pawel Zarembski	0:01f31e923fe2	5150	#define RTC_LR_CRL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5151	#define RTC_LR_CRL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5152	#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
Pawel Zarembski	0:01f31e923fe2	5153	#define RTC_LR_SRL_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5154	#define RTC_LR_SRL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5155	#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
Pawel Zarembski	0:01f31e923fe2	5156	#define RTC_LR_LRL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5157	#define RTC_LR_LRL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5158	#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
Pawel Zarembski	0:01f31e923fe2	5159
Pawel Zarembski	0:01f31e923fe2	5160	/! @name IER - RTC Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	5161	#define RTC_IER_TIIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5162	#define RTC_IER_TIIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5163	#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5164	#define RTC_IER_TOIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5165	#define RTC_IER_TOIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5166	#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5167	#define RTC_IER_TAIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5168	#define RTC_IER_TAIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5169	#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5170	#define RTC_IER_TSIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5171	#define RTC_IER_TSIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5172	#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5173
Pawel Zarembski	0:01f31e923fe2	5174	/! @name WAR - RTC Write Access Register /
Pawel Zarembski	0:01f31e923fe2	5175	#define RTC_WAR_TSRW_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5176	#define RTC_WAR_TSRW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5177	#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5178	#define RTC_WAR_TPRW_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5179	#define RTC_WAR_TPRW_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5180	#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5181	#define RTC_WAR_TARW_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5182	#define RTC_WAR_TARW_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5183	#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
Pawel Zarembski	0:01f31e923fe2	5184	#define RTC_WAR_TCRW_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5185	#define RTC_WAR_TCRW_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5186	#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5187	#define RTC_WAR_CRW_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5188	#define RTC_WAR_CRW_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5189	#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5190	#define RTC_WAR_SRW_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5191	#define RTC_WAR_SRW_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5192	#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5193	#define RTC_WAR_LRW_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5194	#define RTC_WAR_LRW_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5195	#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
Pawel Zarembski	0:01f31e923fe2	5196	#define RTC_WAR_IERW_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5197	#define RTC_WAR_IERW_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5198	#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
Pawel Zarembski	0:01f31e923fe2	5199
Pawel Zarembski	0:01f31e923fe2	5200	/! @name RAR - RTC Read Access Register /
Pawel Zarembski	0:01f31e923fe2	5201	#define RTC_RAR_TSRR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5202	#define RTC_RAR_TSRR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5203	#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5204	#define RTC_RAR_TPRR_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5205	#define RTC_RAR_TPRR_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5206	#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5207	#define RTC_RAR_TARR_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5208	#define RTC_RAR_TARR_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5209	#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
Pawel Zarembski	0:01f31e923fe2	5210	#define RTC_RAR_TCRR_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5211	#define RTC_RAR_TCRR_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5212	#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5213	#define RTC_RAR_CRR_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5214	#define RTC_RAR_CRR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5215	#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5216	#define RTC_RAR_SRR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5217	#define RTC_RAR_SRR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5218	#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5219	#define RTC_RAR_LRR_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5220	#define RTC_RAR_LRR_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5221	#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
Pawel Zarembski	0:01f31e923fe2	5222	#define RTC_RAR_IERR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5223	#define RTC_RAR_IERR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5224	#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
Pawel Zarembski	0:01f31e923fe2	5225
Pawel Zarembski	0:01f31e923fe2	5226
Pawel Zarembski	0:01f31e923fe2	5227	/*!
Pawel Zarembski	0:01f31e923fe2	5228	* @}
Pawel Zarembski	0:01f31e923fe2	5229	/ / end of group RTC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5230
Pawel Zarembski	0:01f31e923fe2	5231
Pawel Zarembski	0:01f31e923fe2	5232	/* RTC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5233	/** Peripheral RTC base address */
Pawel Zarembski	0:01f31e923fe2	5234	#define RTC_BASE (0x4003D000u)
Pawel Zarembski	0:01f31e923fe2	5235	/** Peripheral RTC base pointer */
Pawel Zarembski	0:01f31e923fe2	5236	#define RTC ((RTC_Type *)RTC_BASE)
Pawel Zarembski	0:01f31e923fe2	5237	/** Array initializer of RTC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5238	#define RTC_BASE_ADDRS { RTC_BASE }
Pawel Zarembski	0:01f31e923fe2	5239	/** Array initializer of RTC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5240	#define RTC_BASE_PTRS { RTC }
Pawel Zarembski	0:01f31e923fe2	5241	/** Interrupt vectors for the RTC peripheral type */
Pawel Zarembski	0:01f31e923fe2	5242	#define RTC_IRQS { RTC_IRQn }
Pawel Zarembski	0:01f31e923fe2	5243	#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
Pawel Zarembski	0:01f31e923fe2	5244
Pawel Zarembski	0:01f31e923fe2	5245	/*!
Pawel Zarembski	0:01f31e923fe2	5246	* @}
Pawel Zarembski	0:01f31e923fe2	5247	/ / end of group RTC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5248
Pawel Zarembski	0:01f31e923fe2	5249
Pawel Zarembski	0:01f31e923fe2	5250	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5251	-- SIM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5252	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5253
Pawel Zarembski	0:01f31e923fe2	5254	/*!
Pawel Zarembski	0:01f31e923fe2	5255	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5256	* @{
Pawel Zarembski	0:01f31e923fe2	5257	*/
Pawel Zarembski	0:01f31e923fe2	5258
Pawel Zarembski	0:01f31e923fe2	5259	/** SIM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5260	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5261	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5262	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5263	uint8_t RESERVED_0[4092];
Pawel Zarembski	0:01f31e923fe2	5264	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
Pawel Zarembski	0:01f31e923fe2	5265	uint8_t RESERVED_1[4];
Pawel Zarembski	0:01f31e923fe2	5266	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
Pawel Zarembski	0:01f31e923fe2	5267	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
Pawel Zarembski	0:01f31e923fe2	5268	uint8_t RESERVED_2[4];
Pawel Zarembski	0:01f31e923fe2	5269	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
Pawel Zarembski	0:01f31e923fe2	5270	uint8_t RESERVED_3[8];
Pawel Zarembski	0:01f31e923fe2	5271	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
Pawel Zarembski	0:01f31e923fe2	5272	uint8_t RESERVED_4[12];
Pawel Zarembski	0:01f31e923fe2	5273	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
Pawel Zarembski	0:01f31e923fe2	5274	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
Pawel Zarembski	0:01f31e923fe2	5275	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
Pawel Zarembski	0:01f31e923fe2	5276	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
Pawel Zarembski	0:01f31e923fe2	5277	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
Pawel Zarembski	0:01f31e923fe2	5278	__IO uint32_t CLKDIV2; /*< System Clock Divider Register 2, offset: 0x1048 /
Pawel Zarembski	0:01f31e923fe2	5279	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
Pawel Zarembski	0:01f31e923fe2	5280	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
Pawel Zarembski	0:01f31e923fe2	5281	__I uint32_t UIDH; /*< Unique Identification Register High, offset: 0x1054 /
Pawel Zarembski	0:01f31e923fe2	5282	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
Pawel Zarembski	0:01f31e923fe2	5283	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
Pawel Zarembski	0:01f31e923fe2	5284	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
Pawel Zarembski	0:01f31e923fe2	5285	} SIM_Type;
Pawel Zarembski	0:01f31e923fe2	5286
Pawel Zarembski	0:01f31e923fe2	5287	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5288	-- SIM Register Masks
Pawel Zarembski	0:01f31e923fe2	5289	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5290
Pawel Zarembski	0:01f31e923fe2	5291	/*!
Pawel Zarembski	0:01f31e923fe2	5292	* @addtogroup SIM_Register_Masks SIM Register Masks
Pawel Zarembski	0:01f31e923fe2	5293	* @{
Pawel Zarembski	0:01f31e923fe2	5294	*/
Pawel Zarembski	0:01f31e923fe2	5295
Pawel Zarembski	0:01f31e923fe2	5296	/! @name SOPT1 - System Options Register 1 /
Pawel Zarembski	0:01f31e923fe2	5297	#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	5298	#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5299	#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5300	#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	5301	#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5302	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5303	#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	5304	#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	5305	#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
Pawel Zarembski	0:01f31e923fe2	5306	#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	5307	#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	5308	#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
Pawel Zarembski	0:01f31e923fe2	5309	#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5310	#define SIM_SOPT1_USBREGEN_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5311	#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5312
Pawel Zarembski	0:01f31e923fe2	5313	/! @name SOPT1CFG - SOPT1 Configuration Register /
Pawel Zarembski	0:01f31e923fe2	5314	#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5315	#define SIM_SOPT1CFG_URWE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5316	#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
Pawel Zarembski	0:01f31e923fe2	5317	#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5318	#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5319	#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
Pawel Zarembski	0:01f31e923fe2	5320	#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	5321	#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	5322	#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
Pawel Zarembski	0:01f31e923fe2	5323
Pawel Zarembski	0:01f31e923fe2	5324	/! @name SOPT2 - System Options Register 2 /
Pawel Zarembski	0:01f31e923fe2	5325	#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5326	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5327	#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5328	#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
Pawel Zarembski	0:01f31e923fe2	5329	#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5330	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5331	#define SIM_SOPT2_PTD7PAD_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	5332	#define SIM_SOPT2_PTD7PAD_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	5333	#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
Pawel Zarembski	0:01f31e923fe2	5334	#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5335	#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5336	#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5337	#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	5338	#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5339	#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5340	#define SIM_SOPT2_USBSRC_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	5341	#define SIM_SOPT2_USBSRC_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5342	#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5343
Pawel Zarembski	0:01f31e923fe2	5344	/! @name SOPT4 - System Options Register 4 /
Pawel Zarembski	0:01f31e923fe2	5345	#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5346	#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5347	#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
Pawel Zarembski	0:01f31e923fe2	5348	#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5349	#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5350	#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
Pawel Zarembski	0:01f31e923fe2	5351	#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5352	#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5353	#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
Pawel Zarembski	0:01f31e923fe2	5354	#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	5355	#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5356	#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5357	#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5358	#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5359	#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5360	#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5361	#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5362	#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5363	#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	5364	#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5365	#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5366
Pawel Zarembski	0:01f31e923fe2	5367	/! @name SOPT5 - System Options Register 5 /
Pawel Zarembski	0:01f31e923fe2	5368	#define SIM_SOPT5_UART0TXSRC_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5369	#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5370	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5371	#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	5372	#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5373	#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5374	#define SIM_SOPT5_UART1TXSRC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5375	#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5376	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5377	#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	5378	#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5379	#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5380
Pawel Zarembski	0:01f31e923fe2	5381	/! @name SOPT7 - System Options Register 7 /
Pawel Zarembski	0:01f31e923fe2	5382	#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	5383	#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5384	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5385	#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5386	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5387	#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	5388	#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5389	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5390	#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5391
Pawel Zarembski	0:01f31e923fe2	5392	/! @name SDID - System Device Identification Register /
Pawel Zarembski	0:01f31e923fe2	5393	#define SIM_SDID_PINID_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	5394	#define SIM_SDID_PINID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5395	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
Pawel Zarembski	0:01f31e923fe2	5396	#define SIM_SDID_FAMID_MASK (0x70U)
Pawel Zarembski	0:01f31e923fe2	5397	#define SIM_SDID_FAMID_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5398	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
Pawel Zarembski	0:01f31e923fe2	5399	#define SIM_SDID_REVID_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	5400	#define SIM_SDID_REVID_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5401	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
Pawel Zarembski	0:01f31e923fe2	5402
Pawel Zarembski	0:01f31e923fe2	5403	/! @name SCGC4 - System Clock Gating Control Register 4 /
Pawel Zarembski	0:01f31e923fe2	5404	#define SIM_SCGC4_EWM_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5405	#define SIM_SCGC4_EWM_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5406	#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
Pawel Zarembski	0:01f31e923fe2	5407	#define SIM_SCGC4_CMT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5408	#define SIM_SCGC4_CMT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5409	#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
Pawel Zarembski	0:01f31e923fe2	5410	#define SIM_SCGC4_I2C0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5411	#define SIM_SCGC4_I2C0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5412	#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
Pawel Zarembski	0:01f31e923fe2	5413	#define SIM_SCGC4_UART0_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	5414	#define SIM_SCGC4_UART0_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	5415	#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
Pawel Zarembski	0:01f31e923fe2	5416	#define SIM_SCGC4_UART1_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	5417	#define SIM_SCGC4_UART1_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	5418	#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
Pawel Zarembski	0:01f31e923fe2	5419	#define SIM_SCGC4_UART2_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5420	#define SIM_SCGC4_UART2_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5421	#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
Pawel Zarembski	0:01f31e923fe2	5422	#define SIM_SCGC4_USBOTG_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	5423	#define SIM_SCGC4_USBOTG_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5424	#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
Pawel Zarembski	0:01f31e923fe2	5425	#define SIM_SCGC4_CMP_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	5426	#define SIM_SCGC4_CMP_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	5427	#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
Pawel Zarembski	0:01f31e923fe2	5428	#define SIM_SCGC4_VREF_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	5429	#define SIM_SCGC4_VREF_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	5430	#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
Pawel Zarembski	0:01f31e923fe2	5431
Pawel Zarembski	0:01f31e923fe2	5432	/! @name SCGC5 - System Clock Gating Control Register 5 /
Pawel Zarembski	0:01f31e923fe2	5433	#define SIM_SCGC5_LPTIMER_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5434	#define SIM_SCGC5_LPTIMER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5435	#define SIM_SCGC5_LPTIMER(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK)
Pawel Zarembski	0:01f31e923fe2	5436	#define SIM_SCGC5_TSI_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5437	#define SIM_SCGC5_TSI_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5438	#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
Pawel Zarembski	0:01f31e923fe2	5439	#define SIM_SCGC5_PORTA_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	5440	#define SIM_SCGC5_PORTA_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	5441	#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
Pawel Zarembski	0:01f31e923fe2	5442	#define SIM_SCGC5_PORTB_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	5443	#define SIM_SCGC5_PORTB_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	5444	#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
Pawel Zarembski	0:01f31e923fe2	5445	#define SIM_SCGC5_PORTC_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	5446	#define SIM_SCGC5_PORTC_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	5447	#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
Pawel Zarembski	0:01f31e923fe2	5448	#define SIM_SCGC5_PORTD_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5449	#define SIM_SCGC5_PORTD_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5450	#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
Pawel Zarembski	0:01f31e923fe2	5451	#define SIM_SCGC5_PORTE_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	5452	#define SIM_SCGC5_PORTE_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	5453	#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
Pawel Zarembski	0:01f31e923fe2	5454
Pawel Zarembski	0:01f31e923fe2	5455	/! @name SCGC6 - System Clock Gating Control Register 6 /
Pawel Zarembski	0:01f31e923fe2	5456	#define SIM_SCGC6_FTFL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5457	#define SIM_SCGC6_FTFL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5458	#define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
Pawel Zarembski	0:01f31e923fe2	5459	#define SIM_SCGC6_DMAMUX_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5460	#define SIM_SCGC6_DMAMUX_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5461	#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
Pawel Zarembski	0:01f31e923fe2	5462	#define SIM_SCGC6_SPI0_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5463	#define SIM_SCGC6_SPI0_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5464	#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
Pawel Zarembski	0:01f31e923fe2	5465	#define SIM_SCGC6_I2S_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	5466	#define SIM_SCGC6_I2S_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	5467	#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
Pawel Zarembski	0:01f31e923fe2	5468	#define SIM_SCGC6_CRC_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	5469	#define SIM_SCGC6_CRC_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5470	#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5471	#define SIM_SCGC6_USBDCD_MASK (0x200000U)
Pawel Zarembski	0:01f31e923fe2	5472	#define SIM_SCGC6_USBDCD_SHIFT (21U)
Pawel Zarembski	0:01f31e923fe2	5473	#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
Pawel Zarembski	0:01f31e923fe2	5474	#define SIM_SCGC6_PDB_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	5475	#define SIM_SCGC6_PDB_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	5476	#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
Pawel Zarembski	0:01f31e923fe2	5477	#define SIM_SCGC6_PIT_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	5478	#define SIM_SCGC6_PIT_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	5479	#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
Pawel Zarembski	0:01f31e923fe2	5480	#define SIM_SCGC6_FTM0_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5481	#define SIM_SCGC6_FTM0_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5482	#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
Pawel Zarembski	0:01f31e923fe2	5483	#define SIM_SCGC6_FTM1_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5484	#define SIM_SCGC6_FTM1_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5485	#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
Pawel Zarembski	0:01f31e923fe2	5486	#define SIM_SCGC6_ADC0_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	5487	#define SIM_SCGC6_ADC0_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5488	#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
Pawel Zarembski	0:01f31e923fe2	5489	#define SIM_SCGC6_RTC_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	5490	#define SIM_SCGC6_RTC_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	5491	#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
Pawel Zarembski	0:01f31e923fe2	5492
Pawel Zarembski	0:01f31e923fe2	5493	/! @name SCGC7 - System Clock Gating Control Register 7 /
Pawel Zarembski	0:01f31e923fe2	5494	#define SIM_SCGC7_DMA_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5495	#define SIM_SCGC7_DMA_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5496	#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	5497
Pawel Zarembski	0:01f31e923fe2	5498	/! @name CLKDIV1 - System Clock Divider Register 1 /
Pawel Zarembski	0:01f31e923fe2	5499	#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	5500	#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5501	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
Pawel Zarembski	0:01f31e923fe2	5502	#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	5503	#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5504	#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
Pawel Zarembski	0:01f31e923fe2	5505	#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	5506	#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5507	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
Pawel Zarembski	0:01f31e923fe2	5508
Pawel Zarembski	0:01f31e923fe2	5509	/! @name CLKDIV2 - System Clock Divider Register 2 /
Pawel Zarembski	0:01f31e923fe2	5510	#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5511	#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5512	#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
Pawel Zarembski	0:01f31e923fe2	5513	#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
Pawel Zarembski	0:01f31e923fe2	5514	#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5515	#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	5516
Pawel Zarembski	0:01f31e923fe2	5517	/! @name FCFG1 - Flash Configuration Register 1 /
Pawel Zarembski	0:01f31e923fe2	5518	#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5519	#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5520	#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5521	#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5522	#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5523	#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5524	#define SIM_FCFG1_DEPART_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	5525	#define SIM_FCFG1_DEPART_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5526	#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
Pawel Zarembski	0:01f31e923fe2	5527	#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	5528	#define SIM_FCFG1_EESIZE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5529	#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5530	#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	5531	#define SIM_FCFG1_PFSIZE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5532	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5533	#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	5534	#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5535	#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5536
Pawel Zarembski	0:01f31e923fe2	5537	/! @name FCFG2 - Flash Configuration Register 2 /
Pawel Zarembski	0:01f31e923fe2	5538	#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
Pawel Zarembski	0:01f31e923fe2	5539	#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5540	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
Pawel Zarembski	0:01f31e923fe2	5541	#define SIM_FCFG2_PFLSH_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	5542	#define SIM_FCFG2_PFLSH_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	5543	#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
Pawel Zarembski	0:01f31e923fe2	5544	#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
Pawel Zarembski	0:01f31e923fe2	5545	#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5546	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
Pawel Zarembski	0:01f31e923fe2	5547
Pawel Zarembski	0:01f31e923fe2	5548	/! @name UIDH - Unique Identification Register High /
Pawel Zarembski	0:01f31e923fe2	5549	#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5550	#define SIM_UIDH_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5551	#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	5552
Pawel Zarembski	0:01f31e923fe2	5553	/! @name UIDMH - Unique Identification Register Mid-High /
Pawel Zarembski	0:01f31e923fe2	5554	#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5555	#define SIM_UIDMH_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5556	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	5557
Pawel Zarembski	0:01f31e923fe2	5558	/! @name UIDML - Unique Identification Register Mid Low /
Pawel Zarembski	0:01f31e923fe2	5559	#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5560	#define SIM_UIDML_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5561	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	5562
Pawel Zarembski	0:01f31e923fe2	5563	/! @name UIDL - Unique Identification Register Low /
Pawel Zarembski	0:01f31e923fe2	5564	#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5565	#define SIM_UIDL_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5566	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	5567
Pawel Zarembski	0:01f31e923fe2	5568
Pawel Zarembski	0:01f31e923fe2	5569	/*!
Pawel Zarembski	0:01f31e923fe2	5570	* @}
Pawel Zarembski	0:01f31e923fe2	5571	/ / end of group SIM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5572
Pawel Zarembski	0:01f31e923fe2	5573
Pawel Zarembski	0:01f31e923fe2	5574	/* SIM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5575	/** Peripheral SIM base address */
Pawel Zarembski	0:01f31e923fe2	5576	#define SIM_BASE (0x40047000u)
Pawel Zarembski	0:01f31e923fe2	5577	/** Peripheral SIM base pointer */
Pawel Zarembski	0:01f31e923fe2	5578	#define SIM ((SIM_Type *)SIM_BASE)
Pawel Zarembski	0:01f31e923fe2	5579	/** Array initializer of SIM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5580	#define SIM_BASE_ADDRS { SIM_BASE }
Pawel Zarembski	0:01f31e923fe2	5581	/** Array initializer of SIM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5582	#define SIM_BASE_PTRS { SIM }
Pawel Zarembski	0:01f31e923fe2	5583
Pawel Zarembski	0:01f31e923fe2	5584	/*!
Pawel Zarembski	0:01f31e923fe2	5585	* @}
Pawel Zarembski	0:01f31e923fe2	5586	/ / end of group SIM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5587
Pawel Zarembski	0:01f31e923fe2	5588
Pawel Zarembski	0:01f31e923fe2	5589	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5590	-- SMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5591	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5592
Pawel Zarembski	0:01f31e923fe2	5593	/*!
Pawel Zarembski	0:01f31e923fe2	5594	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5595	* @{
Pawel Zarembski	0:01f31e923fe2	5596	*/
Pawel Zarembski	0:01f31e923fe2	5597
Pawel Zarembski	0:01f31e923fe2	5598	/** SMC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5599	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5600	__IO uint8_t PMPROT; /*< Power Mode Protection Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5601	__IO uint8_t PMCTRL; /*< Power Mode Control Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	5602	__IO uint8_t VLLSCTRL; /*< VLLS Control Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	5603	__I uint8_t PMSTAT; /*< Power Mode Status Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	5604	} SMC_Type;
Pawel Zarembski	0:01f31e923fe2	5605
Pawel Zarembski	0:01f31e923fe2	5606	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5607	-- SMC Register Masks
Pawel Zarembski	0:01f31e923fe2	5608	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5609
Pawel Zarembski	0:01f31e923fe2	5610	/*!
Pawel Zarembski	0:01f31e923fe2	5611	* @addtogroup SMC_Register_Masks SMC Register Masks
Pawel Zarembski	0:01f31e923fe2	5612	* @{
Pawel Zarembski	0:01f31e923fe2	5613	*/
Pawel Zarembski	0:01f31e923fe2	5614
Pawel Zarembski	0:01f31e923fe2	5615	/! @name PMPROT - Power Mode Protection Register /
Pawel Zarembski	0:01f31e923fe2	5616	#define SMC_PMPROT_AVLLS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5617	#define SMC_PMPROT_AVLLS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5618	#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
Pawel Zarembski	0:01f31e923fe2	5619	#define SMC_PMPROT_ALLS_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5620	#define SMC_PMPROT_ALLS_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5621	#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
Pawel Zarembski	0:01f31e923fe2	5622	#define SMC_PMPROT_AVLP_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5623	#define SMC_PMPROT_AVLP_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5624	#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
Pawel Zarembski	0:01f31e923fe2	5625
Pawel Zarembski	0:01f31e923fe2	5626	/! @name PMCTRL - Power Mode Control Register /
Pawel Zarembski	0:01f31e923fe2	5627	#define SMC_PMCTRL_STOPM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	5628	#define SMC_PMCTRL_STOPM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5629	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
Pawel Zarembski	0:01f31e923fe2	5630	#define SMC_PMCTRL_STOPA_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5631	#define SMC_PMCTRL_STOPA_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5632	#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
Pawel Zarembski	0:01f31e923fe2	5633	#define SMC_PMCTRL_RUNM_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	5634	#define SMC_PMCTRL_RUNM_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5635	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
Pawel Zarembski	0:01f31e923fe2	5636	#define SMC_PMCTRL_LPWUI_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5637	#define SMC_PMCTRL_LPWUI_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5638	#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
Pawel Zarembski	0:01f31e923fe2	5639
Pawel Zarembski	0:01f31e923fe2	5640	/! @name VLLSCTRL - VLLS Control Register /
Pawel Zarembski	0:01f31e923fe2	5641	#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	5642	#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5643	#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
Pawel Zarembski	0:01f31e923fe2	5644	#define SMC_VLLSCTRL_PORPO_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5645	#define SMC_VLLSCTRL_PORPO_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5646	#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
Pawel Zarembski	0:01f31e923fe2	5647
Pawel Zarembski	0:01f31e923fe2	5648	/! @name PMSTAT - Power Mode Status Register /
Pawel Zarembski	0:01f31e923fe2	5649	#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	5650	#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5651	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
Pawel Zarembski	0:01f31e923fe2	5652
Pawel Zarembski	0:01f31e923fe2	5653
Pawel Zarembski	0:01f31e923fe2	5654	/*!
Pawel Zarembski	0:01f31e923fe2	5655	* @}
Pawel Zarembski	0:01f31e923fe2	5656	/ / end of group SMC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5657
Pawel Zarembski	0:01f31e923fe2	5658
Pawel Zarembski	0:01f31e923fe2	5659	/* SMC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5660	/** Peripheral SMC base address */
Pawel Zarembski	0:01f31e923fe2	5661	#define SMC_BASE (0x4007E000u)
Pawel Zarembski	0:01f31e923fe2	5662	/** Peripheral SMC base pointer */
Pawel Zarembski	0:01f31e923fe2	5663	#define SMC ((SMC_Type *)SMC_BASE)
Pawel Zarembski	0:01f31e923fe2	5664	/** Array initializer of SMC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5665	#define SMC_BASE_ADDRS { SMC_BASE }
Pawel Zarembski	0:01f31e923fe2	5666	/** Array initializer of SMC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5667	#define SMC_BASE_PTRS { SMC }
Pawel Zarembski	0:01f31e923fe2	5668
Pawel Zarembski	0:01f31e923fe2	5669	/*!
Pawel Zarembski	0:01f31e923fe2	5670	* @}
Pawel Zarembski	0:01f31e923fe2	5671	/ / end of group SMC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5672
Pawel Zarembski	0:01f31e923fe2	5673
Pawel Zarembski	0:01f31e923fe2	5674	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5675	-- SPI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5676	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5677
Pawel Zarembski	0:01f31e923fe2	5678	/*!
Pawel Zarembski	0:01f31e923fe2	5679	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5680	* @{
Pawel Zarembski	0:01f31e923fe2	5681	*/
Pawel Zarembski	0:01f31e923fe2	5682
Pawel Zarembski	0:01f31e923fe2	5683	/** SPI - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5684	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5685	__IO uint32_t MCR; /*< DSPI Module Configuration Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5686	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	5687	__IO uint32_t TCR; /*< DSPI Transfer Count Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	5688	union { /* offset: 0xC */
Pawel Zarembski	0:01f31e923fe2	5689	__IO uint32_t CTAR[2]; /*< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5690	__IO uint32_t CTAR_SLAVE[1]; /*< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5691	};
Pawel Zarembski	0:01f31e923fe2	5692	uint8_t RESERVED_1[24];
Pawel Zarembski	0:01f31e923fe2	5693	__IO uint32_t SR; /*< DSPI Status Register, offset: 0x2C /
Pawel Zarembski	0:01f31e923fe2	5694	__IO uint32_t RSER; /*< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 /
Pawel Zarembski	0:01f31e923fe2	5695	union { /* offset: 0x34 */
Pawel Zarembski	0:01f31e923fe2	5696	__IO uint32_t PUSHR; /*< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 /
Pawel Zarembski	0:01f31e923fe2	5697	__IO uint32_t PUSHR_SLAVE; /*< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 /
Pawel Zarembski	0:01f31e923fe2	5698	};
Pawel Zarembski	0:01f31e923fe2	5699	__I uint32_t POPR; /*< DSPI POP RX FIFO Register, offset: 0x38 /
Pawel Zarembski	0:01f31e923fe2	5700	__I uint32_t TXFR0; /*< DSPI Transmit FIFO Registers, offset: 0x3C /
Pawel Zarembski	0:01f31e923fe2	5701	__I uint32_t TXFR1; /*< DSPI Transmit FIFO Registers, offset: 0x40 /
Pawel Zarembski	0:01f31e923fe2	5702	__I uint32_t TXFR2; /*< DSPI Transmit FIFO Registers, offset: 0x44 /
Pawel Zarembski	0:01f31e923fe2	5703	__I uint32_t TXFR3; /*< DSPI Transmit FIFO Registers, offset: 0x48 /
Pawel Zarembski	0:01f31e923fe2	5704	uint8_t RESERVED_2[48];
Pawel Zarembski	0:01f31e923fe2	5705	__I uint32_t RXFR0; /*< DSPI Receive FIFO Registers, offset: 0x7C /
Pawel Zarembski	0:01f31e923fe2	5706	__I uint32_t RXFR1; /*< DSPI Receive FIFO Registers, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	5707	__I uint32_t RXFR2; /*< DSPI Receive FIFO Registers, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	5708	__I uint32_t RXFR3; /*< DSPI Receive FIFO Registers, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	5709	} SPI_Type;
Pawel Zarembski	0:01f31e923fe2	5710
Pawel Zarembski	0:01f31e923fe2	5711	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5712	-- SPI Register Masks
Pawel Zarembski	0:01f31e923fe2	5713	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5714
Pawel Zarembski	0:01f31e923fe2	5715	/*!
Pawel Zarembski	0:01f31e923fe2	5716	* @addtogroup SPI_Register_Masks SPI Register Masks
Pawel Zarembski	0:01f31e923fe2	5717	* @{
Pawel Zarembski	0:01f31e923fe2	5718	*/
Pawel Zarembski	0:01f31e923fe2	5719
Pawel Zarembski	0:01f31e923fe2	5720	/! @name MCR - DSPI Module Configuration Register /
Pawel Zarembski	0:01f31e923fe2	5721	#define SPI_MCR_HALT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5722	#define SPI_MCR_HALT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5723	#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
Pawel Zarembski	0:01f31e923fe2	5724	#define SPI_MCR_SMPL_PT_MASK (0x300U)
Pawel Zarembski	0:01f31e923fe2	5725	#define SPI_MCR_SMPL_PT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5726	#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
Pawel Zarembski	0:01f31e923fe2	5727	#define SPI_MCR_CLR_RXF_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	5728	#define SPI_MCR_CLR_RXF_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	5729	#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
Pawel Zarembski	0:01f31e923fe2	5730	#define SPI_MCR_CLR_TXF_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	5731	#define SPI_MCR_CLR_TXF_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	5732	#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
Pawel Zarembski	0:01f31e923fe2	5733	#define SPI_MCR_DIS_RXF_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	5734	#define SPI_MCR_DIS_RXF_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5735	#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
Pawel Zarembski	0:01f31e923fe2	5736	#define SPI_MCR_DIS_TXF_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	5737	#define SPI_MCR_DIS_TXF_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	5738	#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
Pawel Zarembski	0:01f31e923fe2	5739	#define SPI_MCR_MDIS_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	5740	#define SPI_MCR_MDIS_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	5741	#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5742	#define SPI_MCR_DOZE_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	5743	#define SPI_MCR_DOZE_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	5744	#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
Pawel Zarembski	0:01f31e923fe2	5745	#define SPI_MCR_PCSIS_MASK (0x3F0000U)
Pawel Zarembski	0:01f31e923fe2	5746	#define SPI_MCR_PCSIS_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5747	#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5748	#define SPI_MCR_ROOE_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5749	#define SPI_MCR_ROOE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5750	#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
Pawel Zarembski	0:01f31e923fe2	5751	#define SPI_MCR_PCSSE_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5752	#define SPI_MCR_PCSSE_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5753	#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
Pawel Zarembski	0:01f31e923fe2	5754	#define SPI_MCR_MTFE_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	5755	#define SPI_MCR_MTFE_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	5756	#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
Pawel Zarembski	0:01f31e923fe2	5757	#define SPI_MCR_FRZ_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	5758	#define SPI_MCR_FRZ_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5759	#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
Pawel Zarembski	0:01f31e923fe2	5760	#define SPI_MCR_DCONF_MASK (0x30000000U)
Pawel Zarembski	0:01f31e923fe2	5761	#define SPI_MCR_DCONF_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5762	#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
Pawel Zarembski	0:01f31e923fe2	5763	#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	5764	#define SPI_MCR_CONT_SCKE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	5765	#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
Pawel Zarembski	0:01f31e923fe2	5766	#define SPI_MCR_MSTR_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5767	#define SPI_MCR_MSTR_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5768	#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
Pawel Zarembski	0:01f31e923fe2	5769
Pawel Zarembski	0:01f31e923fe2	5770	/! @name TCR - DSPI Transfer Count Register /
Pawel Zarembski	0:01f31e923fe2	5771	#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	5772	#define SPI_TCR_SPI_TCNT_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5773	#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	5774
Pawel Zarembski	0:01f31e923fe2	5775	/! @name CTAR - DSPI Clock and Transfer Attributes Register (In Master Mode) /
Pawel Zarembski	0:01f31e923fe2	5776	#define SPI_CTAR_BR_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	5777	#define SPI_CTAR_BR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5778	#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
Pawel Zarembski	0:01f31e923fe2	5779	#define SPI_CTAR_DT_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	5780	#define SPI_CTAR_DT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5781	#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
Pawel Zarembski	0:01f31e923fe2	5782	#define SPI_CTAR_ASC_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	5783	#define SPI_CTAR_ASC_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5784	#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
Pawel Zarembski	0:01f31e923fe2	5785	#define SPI_CTAR_CSSCK_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	5786	#define SPI_CTAR_CSSCK_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5787	#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
Pawel Zarembski	0:01f31e923fe2	5788	#define SPI_CTAR_PBR_MASK (0x30000U)
Pawel Zarembski	0:01f31e923fe2	5789	#define SPI_CTAR_PBR_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5790	#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
Pawel Zarembski	0:01f31e923fe2	5791	#define SPI_CTAR_PDT_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	5792	#define SPI_CTAR_PDT_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	5793	#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
Pawel Zarembski	0:01f31e923fe2	5794	#define SPI_CTAR_PASC_MASK (0x300000U)
Pawel Zarembski	0:01f31e923fe2	5795	#define SPI_CTAR_PASC_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	5796	#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
Pawel Zarembski	0:01f31e923fe2	5797	#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
Pawel Zarembski	0:01f31e923fe2	5798	#define SPI_CTAR_PCSSCK_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	5799	#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
Pawel Zarembski	0:01f31e923fe2	5800	#define SPI_CTAR_LSBFE_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5801	#define SPI_CTAR_LSBFE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5802	#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
Pawel Zarembski	0:01f31e923fe2	5803	#define SPI_CTAR_CPHA_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5804	#define SPI_CTAR_CPHA_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5805	#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
Pawel Zarembski	0:01f31e923fe2	5806	#define SPI_CTAR_CPOL_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	5807	#define SPI_CTAR_CPOL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	5808	#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	5809	#define SPI_CTAR_FMSZ_MASK (0x78000000U)
Pawel Zarembski	0:01f31e923fe2	5810	#define SPI_CTAR_FMSZ_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5811	#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	5812	#define SPI_CTAR_DBR_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5813	#define SPI_CTAR_DBR_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5814	#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
Pawel Zarembski	0:01f31e923fe2	5815
Pawel Zarembski	0:01f31e923fe2	5816	/* The count of SPI_CTAR */
Pawel Zarembski	0:01f31e923fe2	5817	#define SPI_CTAR_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	5818
Pawel Zarembski	0:01f31e923fe2	5819	/! @name CTAR_SLAVE - DSPI Clock and Transfer Attributes Register (In Slave Mode) /
Pawel Zarembski	0:01f31e923fe2	5820	#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5821	#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5822	#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
Pawel Zarembski	0:01f31e923fe2	5823	#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	5824	#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	5825	#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	5826	#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
Pawel Zarembski	0:01f31e923fe2	5827	#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5828	#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	5829
Pawel Zarembski	0:01f31e923fe2	5830	/* The count of SPI_CTAR_SLAVE */
Pawel Zarembski	0:01f31e923fe2	5831	#define SPI_CTAR_SLAVE_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	5832
Pawel Zarembski	0:01f31e923fe2	5833	/! @name SR - DSPI Status Register /
Pawel Zarembski	0:01f31e923fe2	5834	#define SPI_SR_POPNXTPTR_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	5835	#define SPI_SR_POPNXTPTR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5836	#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
Pawel Zarembski	0:01f31e923fe2	5837	#define SPI_SR_RXCTR_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	5838	#define SPI_SR_RXCTR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5839	#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
Pawel Zarembski	0:01f31e923fe2	5840	#define SPI_SR_TXNXTPTR_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	5841	#define SPI_SR_TXNXTPTR_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	5842	#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
Pawel Zarembski	0:01f31e923fe2	5843	#define SPI_SR_TXCTR_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	5844	#define SPI_SR_TXCTR_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	5845	#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
Pawel Zarembski	0:01f31e923fe2	5846	#define SPI_SR_RFDF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	5847	#define SPI_SR_RFDF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	5848	#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
Pawel Zarembski	0:01f31e923fe2	5849	#define SPI_SR_RFOF_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	5850	#define SPI_SR_RFOF_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	5851	#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
Pawel Zarembski	0:01f31e923fe2	5852	#define SPI_SR_TFFF_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5853	#define SPI_SR_TFFF_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5854	#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
Pawel Zarembski	0:01f31e923fe2	5855	#define SPI_SR_TFUF_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	5856	#define SPI_SR_TFUF_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5857	#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
Pawel Zarembski	0:01f31e923fe2	5858	#define SPI_SR_EOQF_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	5859	#define SPI_SR_EOQF_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5860	#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
Pawel Zarembski	0:01f31e923fe2	5861	#define SPI_SR_TXRXS_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	5862	#define SPI_SR_TXRXS_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	5863	#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
Pawel Zarembski	0:01f31e923fe2	5864	#define SPI_SR_TCF_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5865	#define SPI_SR_TCF_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5866	#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
Pawel Zarembski	0:01f31e923fe2	5867
Pawel Zarembski	0:01f31e923fe2	5868	/! @name RSER - DSPI DMA/Interrupt Request Select and Enable Register /
Pawel Zarembski	0:01f31e923fe2	5869	#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	5870	#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5871	#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
Pawel Zarembski	0:01f31e923fe2	5872	#define SPI_RSER_RFDF_RE_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	5873	#define SPI_RSER_RFDF_RE_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	5874	#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5875	#define SPI_RSER_RFOF_RE_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	5876	#define SPI_RSER_RFOF_RE_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	5877	#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5878	#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	5879	#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	5880	#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
Pawel Zarembski	0:01f31e923fe2	5881	#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	5882	#define SPI_RSER_TFFF_RE_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	5883	#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5884	#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	5885	#define SPI_RSER_TFUF_RE_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5886	#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5887	#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	5888	#define SPI_RSER_EOQF_RE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5889	#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5890	#define SPI_RSER_TCF_RE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5891	#define SPI_RSER_TCF_RE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5892	#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5893
Pawel Zarembski	0:01f31e923fe2	5894	/! @name PUSHR - DSPI PUSH TX FIFO Register In Master Mode /
Pawel Zarembski	0:01f31e923fe2	5895	#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5896	#define SPI_PUSHR_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5897	#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5898	#define SPI_PUSHR_PCS_MASK (0x3F0000U)
Pawel Zarembski	0:01f31e923fe2	5899	#define SPI_PUSHR_PCS_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5900	#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
Pawel Zarembski	0:01f31e923fe2	5901	#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	5902	#define SPI_PUSHR_CTCNT_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	5903	#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	5904	#define SPI_PUSHR_EOQ_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	5905	#define SPI_PUSHR_EOQ_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	5906	#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
Pawel Zarembski	0:01f31e923fe2	5907	#define SPI_PUSHR_CTAS_MASK (0x70000000U)
Pawel Zarembski	0:01f31e923fe2	5908	#define SPI_PUSHR_CTAS_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	5909	#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
Pawel Zarembski	0:01f31e923fe2	5910	#define SPI_PUSHR_CONT_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	5911	#define SPI_PUSHR_CONT_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	5912	#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
Pawel Zarembski	0:01f31e923fe2	5913
Pawel Zarembski	0:01f31e923fe2	5914	/! @name PUSHR_SLAVE - DSPI PUSH TX FIFO Register In Slave Mode /
Pawel Zarembski	0:01f31e923fe2	5915	#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5916	#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5917	#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5918
Pawel Zarembski	0:01f31e923fe2	5919	/! @name POPR - DSPI POP RX FIFO Register /
Pawel Zarembski	0:01f31e923fe2	5920	#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5921	#define SPI_POPR_RXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5922	#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5923
Pawel Zarembski	0:01f31e923fe2	5924	/! @name TXFR0 - DSPI Transmit FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5925	#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5926	#define SPI_TXFR0_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5927	#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5928	#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	5929	#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5930	#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5931
Pawel Zarembski	0:01f31e923fe2	5932	/! @name TXFR1 - DSPI Transmit FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5933	#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5934	#define SPI_TXFR1_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5935	#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5936	#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	5937	#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5938	#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5939
Pawel Zarembski	0:01f31e923fe2	5940	/! @name TXFR2 - DSPI Transmit FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5941	#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5942	#define SPI_TXFR2_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5943	#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5944	#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	5945	#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5946	#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5947
Pawel Zarembski	0:01f31e923fe2	5948	/! @name TXFR3 - DSPI Transmit FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5949	#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	5950	#define SPI_TXFR3_TXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5951	#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5952	#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	5953	#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	5954	#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5955
Pawel Zarembski	0:01f31e923fe2	5956	/! @name RXFR0 - DSPI Receive FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5957	#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5958	#define SPI_RXFR0_RXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5959	#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5960
Pawel Zarembski	0:01f31e923fe2	5961	/! @name RXFR1 - DSPI Receive FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5962	#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5963	#define SPI_RXFR1_RXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5964	#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5965
Pawel Zarembski	0:01f31e923fe2	5966	/! @name RXFR2 - DSPI Receive FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5967	#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5968	#define SPI_RXFR2_RXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5969	#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5970
Pawel Zarembski	0:01f31e923fe2	5971	/! @name RXFR3 - DSPI Receive FIFO Registers /
Pawel Zarembski	0:01f31e923fe2	5972	#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	5973	#define SPI_RXFR3_RXDATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5974	#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
Pawel Zarembski	0:01f31e923fe2	5975
Pawel Zarembski	0:01f31e923fe2	5976
Pawel Zarembski	0:01f31e923fe2	5977	/*!
Pawel Zarembski	0:01f31e923fe2	5978	* @}
Pawel Zarembski	0:01f31e923fe2	5979	/ / end of group SPI_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5980
Pawel Zarembski	0:01f31e923fe2	5981
Pawel Zarembski	0:01f31e923fe2	5982	/* SPI - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5983	/** Peripheral SPI0 base address */
Pawel Zarembski	0:01f31e923fe2	5984	#define SPI0_BASE (0x4002C000u)
Pawel Zarembski	0:01f31e923fe2	5985	/** Peripheral SPI0 base pointer */
Pawel Zarembski	0:01f31e923fe2	5986	#define SPI0 ((SPI_Type *)SPI0_BASE)
Pawel Zarembski	0:01f31e923fe2	5987	/** Array initializer of SPI peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5988	#define SPI_BASE_ADDRS { SPI0_BASE }
Pawel Zarembski	0:01f31e923fe2	5989	/** Array initializer of SPI peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5990	#define SPI_BASE_PTRS { SPI0 }
Pawel Zarembski	0:01f31e923fe2	5991	/** Interrupt vectors for the SPI peripheral type */
Pawel Zarembski	0:01f31e923fe2	5992	#define SPI_IRQS { SPI0_IRQn }
Pawel Zarembski	0:01f31e923fe2	5993
Pawel Zarembski	0:01f31e923fe2	5994	/*!
Pawel Zarembski	0:01f31e923fe2	5995	* @}
Pawel Zarembski	0:01f31e923fe2	5996	/ / end of group SPI_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5997
Pawel Zarembski	0:01f31e923fe2	5998
Pawel Zarembski	0:01f31e923fe2	5999	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6000	-- TSI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6001	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6002
Pawel Zarembski	0:01f31e923fe2	6003	/*!
Pawel Zarembski	0:01f31e923fe2	6004	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6005	* @{
Pawel Zarembski	0:01f31e923fe2	6006	*/
Pawel Zarembski	0:01f31e923fe2	6007
Pawel Zarembski	0:01f31e923fe2	6008	/** TSI - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	6009	typedef struct {
Pawel Zarembski	0:01f31e923fe2	6010	__IO uint32_t GENCS; /*< General Control and Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	6011	__IO uint32_t SCANC; /*< SCAN Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	6012	__IO uint32_t PEN; /*< Pin Enable Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	6013	__I uint32_t WUCNTR; /*< Wake-Up Channel Counter Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	6014	uint8_t RESERVED_0[240];
Pawel Zarembski	0:01f31e923fe2	6015	__I uint32_t CNTR1; /*< Counter Register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	6016	__I uint32_t CNTR3; /*< Counter Register, offset: 0x104 /
Pawel Zarembski	0:01f31e923fe2	6017	__I uint32_t CNTR5; /*< Counter Register, offset: 0x108 /
Pawel Zarembski	0:01f31e923fe2	6018	__I uint32_t CNTR7; /*< Counter Register, offset: 0x10C /
Pawel Zarembski	0:01f31e923fe2	6019	__I uint32_t CNTR9; /*< Counter Register, offset: 0x110 /
Pawel Zarembski	0:01f31e923fe2	6020	__I uint32_t CNTR11; /*< Counter Register, offset: 0x114 /
Pawel Zarembski	0:01f31e923fe2	6021	__I uint32_t CNTR13; /*< Counter Register, offset: 0x118 /
Pawel Zarembski	0:01f31e923fe2	6022	__I uint32_t CNTR15; /*< Counter Register, offset: 0x11C /
Pawel Zarembski	0:01f31e923fe2	6023	__IO uint32_t THRESHOLD; /*< Low Power Channel Threshold Register, offset: 0x120 /
Pawel Zarembski	0:01f31e923fe2	6024	} TSI_Type;
Pawel Zarembski	0:01f31e923fe2	6025
Pawel Zarembski	0:01f31e923fe2	6026	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6027	-- TSI Register Masks
Pawel Zarembski	0:01f31e923fe2	6028	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6029
Pawel Zarembski	0:01f31e923fe2	6030	/*!
Pawel Zarembski	0:01f31e923fe2	6031	* @addtogroup TSI_Register_Masks TSI Register Masks
Pawel Zarembski	0:01f31e923fe2	6032	* @{
Pawel Zarembski	0:01f31e923fe2	6033	*/
Pawel Zarembski	0:01f31e923fe2	6034
Pawel Zarembski	0:01f31e923fe2	6035	/! @name GENCS - General Control and Status Register /
Pawel Zarembski	0:01f31e923fe2	6036	#define TSI_GENCS_STPE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6037	#define TSI_GENCS_STPE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6038	#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
Pawel Zarembski	0:01f31e923fe2	6039	#define TSI_GENCS_STM_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6040	#define TSI_GENCS_STM_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6041	#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
Pawel Zarembski	0:01f31e923fe2	6042	#define TSI_GENCS_ESOR_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6043	#define TSI_GENCS_ESOR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6044	#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
Pawel Zarembski	0:01f31e923fe2	6045	#define TSI_GENCS_ERIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6046	#define TSI_GENCS_ERIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6047	#define TSI_GENCS_ERIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6048	#define TSI_GENCS_TSIIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6049	#define TSI_GENCS_TSIIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6050	#define TSI_GENCS_TSIIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6051	#define TSI_GENCS_TSIEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6052	#define TSI_GENCS_TSIEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6053	#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	6054	#define TSI_GENCS_SWTS_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	6055	#define TSI_GENCS_SWTS_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	6056	#define TSI_GENCS_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
Pawel Zarembski	0:01f31e923fe2	6057	#define TSI_GENCS_SCNIP_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	6058	#define TSI_GENCS_SCNIP_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	6059	#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
Pawel Zarembski	0:01f31e923fe2	6060	#define TSI_GENCS_OVRF_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	6061	#define TSI_GENCS_OVRF_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	6062	#define TSI_GENCS_OVRF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK)
Pawel Zarembski	0:01f31e923fe2	6063	#define TSI_GENCS_EXTERF_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	6064	#define TSI_GENCS_EXTERF_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	6065	#define TSI_GENCS_EXTERF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK)
Pawel Zarembski	0:01f31e923fe2	6066	#define TSI_GENCS_OUTRGF_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	6067	#define TSI_GENCS_OUTRGF_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	6068	#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
Pawel Zarembski	0:01f31e923fe2	6069	#define TSI_GENCS_EOSF_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	6070	#define TSI_GENCS_EOSF_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	6071	#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
Pawel Zarembski	0:01f31e923fe2	6072	#define TSI_GENCS_PS_MASK (0x70000U)
Pawel Zarembski	0:01f31e923fe2	6073	#define TSI_GENCS_PS_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6074	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	6075	#define TSI_GENCS_NSCN_MASK (0xF80000U)
Pawel Zarembski	0:01f31e923fe2	6076	#define TSI_GENCS_NSCN_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	6077	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
Pawel Zarembski	0:01f31e923fe2	6078	#define TSI_GENCS_LPSCNITV_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	6079	#define TSI_GENCS_LPSCNITV_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	6080	#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK)
Pawel Zarembski	0:01f31e923fe2	6081	#define TSI_GENCS_LPCLKS_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	6082	#define TSI_GENCS_LPCLKS_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	6083	#define TSI_GENCS_LPCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	6084
Pawel Zarembski	0:01f31e923fe2	6085	/! @name SCANC - SCAN Control Register /
Pawel Zarembski	0:01f31e923fe2	6086	#define TSI_SCANC_AMPSC_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	6087	#define TSI_SCANC_AMPSC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6088	#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK)
Pawel Zarembski	0:01f31e923fe2	6089	#define TSI_SCANC_AMCLKS_MASK (0x18U)
Pawel Zarembski	0:01f31e923fe2	6090	#define TSI_SCANC_AMCLKS_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6091	#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	6092	#define TSI_SCANC_SMOD_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	6093	#define TSI_SCANC_SMOD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	6094	#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	6095	#define TSI_SCANC_EXTCHRG_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	6096	#define TSI_SCANC_EXTCHRG_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6097	#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK)
Pawel Zarembski	0:01f31e923fe2	6098	#define TSI_SCANC_REFCHRG_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	6099	#define TSI_SCANC_REFCHRG_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	6100	#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK)
Pawel Zarembski	0:01f31e923fe2	6101
Pawel Zarembski	0:01f31e923fe2	6102	/! @name PEN - Pin Enable Register /
Pawel Zarembski	0:01f31e923fe2	6103	#define TSI_PEN_PEN0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6104	#define TSI_PEN_PEN0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6105	#define TSI_PEN_PEN0(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	6106	#define TSI_PEN_PEN1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6107	#define TSI_PEN_PEN1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6108	#define TSI_PEN_PEN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6109	#define TSI_PEN_PEN2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6110	#define TSI_PEN_PEN2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6111	#define TSI_PEN_PEN2(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	6112	#define TSI_PEN_PEN3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6113	#define TSI_PEN_PEN3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6114	#define TSI_PEN_PEN3(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK)
Pawel Zarembski	0:01f31e923fe2	6115	#define TSI_PEN_PEN4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6116	#define TSI_PEN_PEN4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6117	#define TSI_PEN_PEN4(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK)
Pawel Zarembski	0:01f31e923fe2	6118	#define TSI_PEN_PEN5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6119	#define TSI_PEN_PEN5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6120	#define TSI_PEN_PEN5(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK)
Pawel Zarembski	0:01f31e923fe2	6121	#define TSI_PEN_PEN6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6122	#define TSI_PEN_PEN6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6123	#define TSI_PEN_PEN6(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK)
Pawel Zarembski	0:01f31e923fe2	6124	#define TSI_PEN_PEN7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6125	#define TSI_PEN_PEN7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6126	#define TSI_PEN_PEN7(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK)
Pawel Zarembski	0:01f31e923fe2	6127	#define TSI_PEN_PEN8_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	6128	#define TSI_PEN_PEN8_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	6129	#define TSI_PEN_PEN8(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK)
Pawel Zarembski	0:01f31e923fe2	6130	#define TSI_PEN_PEN9_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	6131	#define TSI_PEN_PEN9_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	6132	#define TSI_PEN_PEN9(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK)
Pawel Zarembski	0:01f31e923fe2	6133	#define TSI_PEN_PEN10_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	6134	#define TSI_PEN_PEN10_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	6135	#define TSI_PEN_PEN10(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK)
Pawel Zarembski	0:01f31e923fe2	6136	#define TSI_PEN_PEN11_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	6137	#define TSI_PEN_PEN11_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	6138	#define TSI_PEN_PEN11(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK)
Pawel Zarembski	0:01f31e923fe2	6139	#define TSI_PEN_PEN12_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	6140	#define TSI_PEN_PEN12_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	6141	#define TSI_PEN_PEN12(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK)
Pawel Zarembski	0:01f31e923fe2	6142	#define TSI_PEN_PEN13_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	6143	#define TSI_PEN_PEN13_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	6144	#define TSI_PEN_PEN13(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK)
Pawel Zarembski	0:01f31e923fe2	6145	#define TSI_PEN_PEN14_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	6146	#define TSI_PEN_PEN14_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	6147	#define TSI_PEN_PEN14(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK)
Pawel Zarembski	0:01f31e923fe2	6148	#define TSI_PEN_PEN15_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	6149	#define TSI_PEN_PEN15_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	6150	#define TSI_PEN_PEN15(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK)
Pawel Zarembski	0:01f31e923fe2	6151	#define TSI_PEN_LPSP_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	6152	#define TSI_PEN_LPSP_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6153	#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK)
Pawel Zarembski	0:01f31e923fe2	6154
Pawel Zarembski	0:01f31e923fe2	6155	/! @name WUCNTR - Wake-Up Channel Counter Register /
Pawel Zarembski	0:01f31e923fe2	6156	#define TSI_WUCNTR_WUCNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6157	#define TSI_WUCNTR_WUCNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6158	#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	6159
Pawel Zarembski	0:01f31e923fe2	6160	/! @name CNTR1 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6161	#define TSI_CNTR1_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6162	#define TSI_CNTR1_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6163	#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6164	#define TSI_CNTR1_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6165	#define TSI_CNTR1_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6166	#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6167
Pawel Zarembski	0:01f31e923fe2	6168	/! @name CNTR3 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6169	#define TSI_CNTR3_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6170	#define TSI_CNTR3_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6171	#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6172	#define TSI_CNTR3_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6173	#define TSI_CNTR3_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6174	#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6175
Pawel Zarembski	0:01f31e923fe2	6176	/! @name CNTR5 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6177	#define TSI_CNTR5_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6178	#define TSI_CNTR5_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6179	#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6180	#define TSI_CNTR5_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6181	#define TSI_CNTR5_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6182	#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6183
Pawel Zarembski	0:01f31e923fe2	6184	/! @name CNTR7 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6185	#define TSI_CNTR7_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6186	#define TSI_CNTR7_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6187	#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6188	#define TSI_CNTR7_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6189	#define TSI_CNTR7_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6190	#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6191
Pawel Zarembski	0:01f31e923fe2	6192	/! @name CNTR9 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6193	#define TSI_CNTR9_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6194	#define TSI_CNTR9_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6195	#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6196	#define TSI_CNTR9_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6197	#define TSI_CNTR9_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6198	#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6199
Pawel Zarembski	0:01f31e923fe2	6200	/! @name CNTR11 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6201	#define TSI_CNTR11_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6202	#define TSI_CNTR11_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6203	#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6204	#define TSI_CNTR11_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6205	#define TSI_CNTR11_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6206	#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6207
Pawel Zarembski	0:01f31e923fe2	6208	/! @name CNTR13 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6209	#define TSI_CNTR13_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6210	#define TSI_CNTR13_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6211	#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6212	#define TSI_CNTR13_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6213	#define TSI_CNTR13_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6214	#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6215
Pawel Zarembski	0:01f31e923fe2	6216	/! @name CNTR15 - Counter Register /
Pawel Zarembski	0:01f31e923fe2	6217	#define TSI_CNTR15_CTN1_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6218	#define TSI_CNTR15_CTN1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6219	#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6220	#define TSI_CNTR15_CTN_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6221	#define TSI_CNTR15_CTN_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6222	#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6223
Pawel Zarembski	0:01f31e923fe2	6224	/! @name THRESHOLD - Low Power Channel Threshold Register /
Pawel Zarembski	0:01f31e923fe2	6225	#define TSI_THRESHOLD_HTHH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	6226	#define TSI_THRESHOLD_HTHH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6227	#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK)
Pawel Zarembski	0:01f31e923fe2	6228	#define TSI_THRESHOLD_LTHH_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	6229	#define TSI_THRESHOLD_LTHH_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	6230	#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK)
Pawel Zarembski	0:01f31e923fe2	6231
Pawel Zarembski	0:01f31e923fe2	6232
Pawel Zarembski	0:01f31e923fe2	6233	/*!
Pawel Zarembski	0:01f31e923fe2	6234	* @}
Pawel Zarembski	0:01f31e923fe2	6235	/ / end of group TSI_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	6236
Pawel Zarembski	0:01f31e923fe2	6237
Pawel Zarembski	0:01f31e923fe2	6238	/* TSI - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	6239	/** Peripheral TSI0 base address */
Pawel Zarembski	0:01f31e923fe2	6240	#define TSI0_BASE (0x40045000u)
Pawel Zarembski	0:01f31e923fe2	6241	/** Peripheral TSI0 base pointer */
Pawel Zarembski	0:01f31e923fe2	6242	#define TSI0 ((TSI_Type *)TSI0_BASE)
Pawel Zarembski	0:01f31e923fe2	6243	/** Array initializer of TSI peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	6244	#define TSI_BASE_ADDRS { TSI0_BASE }
Pawel Zarembski	0:01f31e923fe2	6245	/** Array initializer of TSI peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	6246	#define TSI_BASE_PTRS { TSI0 }
Pawel Zarembski	0:01f31e923fe2	6247	/** Interrupt vectors for the TSI peripheral type */
Pawel Zarembski	0:01f31e923fe2	6248	#define TSI_IRQS { TSI0_IRQn }
Pawel Zarembski	0:01f31e923fe2	6249
Pawel Zarembski	0:01f31e923fe2	6250	/*!
Pawel Zarembski	0:01f31e923fe2	6251	* @}
Pawel Zarembski	0:01f31e923fe2	6252	/ / end of group TSI_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	6253
Pawel Zarembski	0:01f31e923fe2	6254
Pawel Zarembski	0:01f31e923fe2	6255	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6256	-- UART Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6257	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6258
Pawel Zarembski	0:01f31e923fe2	6259	/*!
Pawel Zarembski	0:01f31e923fe2	6260	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6261	* @{
Pawel Zarembski	0:01f31e923fe2	6262	*/
Pawel Zarembski	0:01f31e923fe2	6263
Pawel Zarembski	0:01f31e923fe2	6264	/** UART - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	6265	typedef struct {
Pawel Zarembski	0:01f31e923fe2	6266	__IO uint8_t BDH; /*< UART Baud Rate Registers:High, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	6267	__IO uint8_t BDL; /*< UART Baud Rate Registers: Low, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	6268	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	6269	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	6270	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	6271	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	6272	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	6273	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	6274	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	6275	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	6276	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	6277	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	6278	__I uint8_t ED; /*< UART Extended Data Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	6279	__IO uint8_t MODEM; /*< UART Modem Register, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	6280	__IO uint8_t IR; /*< UART Infrared Register, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	6281	uint8_t RESERVED_0[1];
Pawel Zarembski	0:01f31e923fe2	6282	__IO uint8_t PFIFO; /*< UART FIFO Parameters, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	6283	__IO uint8_t CFIFO; /*< UART FIFO Control Register, offset: 0x11 /
Pawel Zarembski	0:01f31e923fe2	6284	__IO uint8_t SFIFO; /*< UART FIFO Status Register, offset: 0x12 /
Pawel Zarembski	0:01f31e923fe2	6285	__IO uint8_t TWFIFO; /*< UART FIFO Transmit Watermark, offset: 0x13 /
Pawel Zarembski	0:01f31e923fe2	6286	__I uint8_t TCFIFO; /*< UART FIFO Transmit Count, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	6287	__IO uint8_t RWFIFO; /*< UART FIFO Receive Watermark, offset: 0x15 /
Pawel Zarembski	0:01f31e923fe2	6288	__I uint8_t RCFIFO; /*< UART FIFO Receive Count, offset: 0x16 /
Pawel Zarembski	0:01f31e923fe2	6289	uint8_t RESERVED_1[1];
Pawel Zarembski	0:01f31e923fe2	6290	__IO uint8_t C7816; /*< UART 7816 Control Register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	6291	__IO uint8_t IE7816; /*< UART 7816 Interrupt Enable Register, offset: 0x19 /
Pawel Zarembski	0:01f31e923fe2	6292	__IO uint8_t IS7816; /*< UART 7816 Interrupt Status Register, offset: 0x1A /
Pawel Zarembski	0:01f31e923fe2	6293	union { /* offset: 0x1B */
Pawel Zarembski	0:01f31e923fe2	6294	__IO uint8_t WP7816T0; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
Pawel Zarembski	0:01f31e923fe2	6295	__IO uint8_t WP7816T1; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
Pawel Zarembski	0:01f31e923fe2	6296	};
Pawel Zarembski	0:01f31e923fe2	6297	__IO uint8_t WN7816; /*< UART 7816 Wait N Register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	6298	__IO uint8_t WF7816; /*< UART 7816 Wait FD Register, offset: 0x1D /
Pawel Zarembski	0:01f31e923fe2	6299	__IO uint8_t ET7816; /*< UART 7816 Error Threshold Register, offset: 0x1E /
Pawel Zarembski	0:01f31e923fe2	6300	__IO uint8_t TL7816; /*< UART 7816 Transmit Length Register, offset: 0x1F /
Pawel Zarembski	0:01f31e923fe2	6301	uint8_t RESERVED_2[1];
Pawel Zarembski	0:01f31e923fe2	6302	__IO uint8_t C6; /*< UART CEA709.1-B Control Register 6, offset: 0x21 /
Pawel Zarembski	0:01f31e923fe2	6303	__IO uint8_t PCTH; /*< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 /
Pawel Zarembski	0:01f31e923fe2	6304	__IO uint8_t PCTL; /*< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 /
Pawel Zarembski	0:01f31e923fe2	6305	__IO uint8_t B1T; /*< UART CEA709.1-B Beta1 Timer, offset: 0x24 /
Pawel Zarembski	0:01f31e923fe2	6306	__IO uint8_t SDTH; /*< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 /
Pawel Zarembski	0:01f31e923fe2	6307	__IO uint8_t SDTL; /*< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 /
Pawel Zarembski	0:01f31e923fe2	6308	__IO uint8_t PRE; /*< UART CEA709.1-B Preamble, offset: 0x27 /
Pawel Zarembski	0:01f31e923fe2	6309	__IO uint8_t TPL; /*< UART CEA709.1-B Transmit Packet Length, offset: 0x28 /
Pawel Zarembski	0:01f31e923fe2	6310	__IO uint8_t IE; /*< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 /
Pawel Zarembski	0:01f31e923fe2	6311	__IO uint8_t WB; /*< UART CEA709.1-B WBASE, offset: 0x2A /
Pawel Zarembski	0:01f31e923fe2	6312	__IO uint8_t S3; /*< UART CEA709.1-B Status Register, offset: 0x2B /
Pawel Zarembski	0:01f31e923fe2	6313	__IO uint8_t S4; /*< UART CEA709.1-B Status Register, offset: 0x2C /
Pawel Zarembski	0:01f31e923fe2	6314	__I uint8_t RPL; /*< UART CEA709.1-B Received Packet Length, offset: 0x2D /
Pawel Zarembski	0:01f31e923fe2	6315	__I uint8_t RPREL; /*< UART CEA709.1-B Received Preamble Length, offset: 0x2E /
Pawel Zarembski	0:01f31e923fe2	6316	__IO uint8_t CPW; /*< UART CEA709.1-B Collision Pulse Width, offset: 0x2F /
Pawel Zarembski	0:01f31e923fe2	6317	__IO uint8_t RIDT; /*< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 /
Pawel Zarembski	0:01f31e923fe2	6318	__IO uint8_t TIDT; /*< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 /
Pawel Zarembski	0:01f31e923fe2	6319	} UART_Type;
Pawel Zarembski	0:01f31e923fe2	6320
Pawel Zarembski	0:01f31e923fe2	6321	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6322	-- UART Register Masks
Pawel Zarembski	0:01f31e923fe2	6323	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6324
Pawel Zarembski	0:01f31e923fe2	6325	/*!
Pawel Zarembski	0:01f31e923fe2	6326	* @addtogroup UART_Register_Masks UART Register Masks
Pawel Zarembski	0:01f31e923fe2	6327	* @{
Pawel Zarembski	0:01f31e923fe2	6328	*/
Pawel Zarembski	0:01f31e923fe2	6329
Pawel Zarembski	0:01f31e923fe2	6330	/! @name BDH - UART Baud Rate Registers:High /
Pawel Zarembski	0:01f31e923fe2	6331	#define UART_BDH_SBR_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	6332	#define UART_BDH_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6333	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	6334	#define UART_BDH_RXEDGIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6335	#define UART_BDH_RXEDGIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6336	#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6337	#define UART_BDH_LBKDIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6338	#define UART_BDH_LBKDIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6339	#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6340
Pawel Zarembski	0:01f31e923fe2	6341	/! @name BDL - UART Baud Rate Registers: Low /
Pawel Zarembski	0:01f31e923fe2	6342	#define UART_BDL_SBR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6343	#define UART_BDL_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6344	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	6345
Pawel Zarembski	0:01f31e923fe2	6346	/! @name C1 - UART Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	6347	#define UART_C1_PT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6348	#define UART_C1_PT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6349	#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
Pawel Zarembski	0:01f31e923fe2	6350	#define UART_C1_PE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6351	#define UART_C1_PE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6352	#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
Pawel Zarembski	0:01f31e923fe2	6353	#define UART_C1_ILT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6354	#define UART_C1_ILT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6355	#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
Pawel Zarembski	0:01f31e923fe2	6356	#define UART_C1_WAKE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6357	#define UART_C1_WAKE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6358	#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
Pawel Zarembski	0:01f31e923fe2	6359	#define UART_C1_M_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6360	#define UART_C1_M_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6361	#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
Pawel Zarembski	0:01f31e923fe2	6362	#define UART_C1_RSRC_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6363	#define UART_C1_RSRC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6364	#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	6365	#define UART_C1_UARTSWAI_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6366	#define UART_C1_UARTSWAI_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6367	#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
Pawel Zarembski	0:01f31e923fe2	6368	#define UART_C1_LOOPS_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6369	#define UART_C1_LOOPS_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6370	#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
Pawel Zarembski	0:01f31e923fe2	6371
Pawel Zarembski	0:01f31e923fe2	6372	/! @name C2 - UART Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	6373	#define UART_C2_SBK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6374	#define UART_C2_SBK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6375	#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
Pawel Zarembski	0:01f31e923fe2	6376	#define UART_C2_RWU_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6377	#define UART_C2_RWU_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6378	#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
Pawel Zarembski	0:01f31e923fe2	6379	#define UART_C2_RE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6380	#define UART_C2_RE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6381	#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	6382	#define UART_C2_TE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6383	#define UART_C2_TE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6384	#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
Pawel Zarembski	0:01f31e923fe2	6385	#define UART_C2_ILIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6386	#define UART_C2_ILIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6387	#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6388	#define UART_C2_RIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6389	#define UART_C2_RIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6390	#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6391	#define UART_C2_TCIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6392	#define UART_C2_TCIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6393	#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6394	#define UART_C2_TIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6395	#define UART_C2_TIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6396	#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6397
Pawel Zarembski	0:01f31e923fe2	6398	/! @name S1 - UART Status Register 1 /
Pawel Zarembski	0:01f31e923fe2	6399	#define UART_S1_PF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6400	#define UART_S1_PF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6401	#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
Pawel Zarembski	0:01f31e923fe2	6402	#define UART_S1_FE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6403	#define UART_S1_FE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6404	#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
Pawel Zarembski	0:01f31e923fe2	6405	#define UART_S1_NF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6406	#define UART_S1_NF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6407	#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
Pawel Zarembski	0:01f31e923fe2	6408	#define UART_S1_OR_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6409	#define UART_S1_OR_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6410	#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
Pawel Zarembski	0:01f31e923fe2	6411	#define UART_S1_IDLE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6412	#define UART_S1_IDLE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6413	#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
Pawel Zarembski	0:01f31e923fe2	6414	#define UART_S1_RDRF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6415	#define UART_S1_RDRF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6416	#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
Pawel Zarembski	0:01f31e923fe2	6417	#define UART_S1_TC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6418	#define UART_S1_TC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6419	#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
Pawel Zarembski	0:01f31e923fe2	6420	#define UART_S1_TDRE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6421	#define UART_S1_TDRE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6422	#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
Pawel Zarembski	0:01f31e923fe2	6423
Pawel Zarembski	0:01f31e923fe2	6424	/! @name S2 - UART Status Register 2 /
Pawel Zarembski	0:01f31e923fe2	6425	#define UART_S2_RAF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6426	#define UART_S2_RAF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6427	#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
Pawel Zarembski	0:01f31e923fe2	6428	#define UART_S2_LBKDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6429	#define UART_S2_LBKDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6430	#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
Pawel Zarembski	0:01f31e923fe2	6431	#define UART_S2_BRK13_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6432	#define UART_S2_BRK13_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6433	#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
Pawel Zarembski	0:01f31e923fe2	6434	#define UART_S2_RWUID_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6435	#define UART_S2_RWUID_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6436	#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
Pawel Zarembski	0:01f31e923fe2	6437	#define UART_S2_RXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6438	#define UART_S2_RXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6439	#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	6440	#define UART_S2_MSBF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6441	#define UART_S2_MSBF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6442	#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
Pawel Zarembski	0:01f31e923fe2	6443	#define UART_S2_RXEDGIF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6444	#define UART_S2_RXEDGIF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6445	#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
Pawel Zarembski	0:01f31e923fe2	6446	#define UART_S2_LBKDIF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6447	#define UART_S2_LBKDIF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6448	#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
Pawel Zarembski	0:01f31e923fe2	6449
Pawel Zarembski	0:01f31e923fe2	6450	/! @name C3 - UART Control Register 3 /
Pawel Zarembski	0:01f31e923fe2	6451	#define UART_C3_PEIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6452	#define UART_C3_PEIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6453	#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6454	#define UART_C3_FEIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6455	#define UART_C3_FEIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6456	#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6457	#define UART_C3_NEIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6458	#define UART_C3_NEIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6459	#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6460	#define UART_C3_ORIE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6461	#define UART_C3_ORIE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6462	#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6463	#define UART_C3_TXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6464	#define UART_C3_TXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6465	#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	6466	#define UART_C3_TXDIR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6467	#define UART_C3_TXDIR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6468	#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
Pawel Zarembski	0:01f31e923fe2	6469	#define UART_C3_T8_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6470	#define UART_C3_T8_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6471	#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
Pawel Zarembski	0:01f31e923fe2	6472	#define UART_C3_R8_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6473	#define UART_C3_R8_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6474	#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
Pawel Zarembski	0:01f31e923fe2	6475
Pawel Zarembski	0:01f31e923fe2	6476	/! @name D - UART Data Register /
Pawel Zarembski	0:01f31e923fe2	6477	#define UART_D_RT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6478	#define UART_D_RT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6479	#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
Pawel Zarembski	0:01f31e923fe2	6480
Pawel Zarembski	0:01f31e923fe2	6481	/! @name MA1 - UART Match Address Registers 1 /
Pawel Zarembski	0:01f31e923fe2	6482	#define UART_MA1_MA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6483	#define UART_MA1_MA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6484	#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
Pawel Zarembski	0:01f31e923fe2	6485
Pawel Zarembski	0:01f31e923fe2	6486	/! @name MA2 - UART Match Address Registers 2 /
Pawel Zarembski	0:01f31e923fe2	6487	#define UART_MA2_MA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6488	#define UART_MA2_MA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6489	#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
Pawel Zarembski	0:01f31e923fe2	6490
Pawel Zarembski	0:01f31e923fe2	6491	/! @name C4 - UART Control Register 4 /
Pawel Zarembski	0:01f31e923fe2	6492	#define UART_C4_BRFA_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	6493	#define UART_C4_BRFA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6494	#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
Pawel Zarembski	0:01f31e923fe2	6495	#define UART_C4_M10_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6496	#define UART_C4_M10_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6497	#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
Pawel Zarembski	0:01f31e923fe2	6498	#define UART_C4_MAEN2_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6499	#define UART_C4_MAEN2_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6500	#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	6501	#define UART_C4_MAEN1_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6502	#define UART_C4_MAEN1_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6503	#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	6504
Pawel Zarembski	0:01f31e923fe2	6505	/! @name C5 - UART Control Register 5 /
Pawel Zarembski	0:01f31e923fe2	6506	#define UART_C5_RDMAS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6507	#define UART_C5_RDMAS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6508	#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
Pawel Zarembski	0:01f31e923fe2	6509	#define UART_C5_TDMAS_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6510	#define UART_C5_TDMAS_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6511	#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
Pawel Zarembski	0:01f31e923fe2	6512
Pawel Zarembski	0:01f31e923fe2	6513	/! @name ED - UART Extended Data Register /
Pawel Zarembski	0:01f31e923fe2	6514	#define UART_ED_PARITYE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6515	#define UART_ED_PARITYE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6516	#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
Pawel Zarembski	0:01f31e923fe2	6517	#define UART_ED_NOISY_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6518	#define UART_ED_NOISY_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6519	#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
Pawel Zarembski	0:01f31e923fe2	6520
Pawel Zarembski	0:01f31e923fe2	6521	/! @name MODEM - UART Modem Register /
Pawel Zarembski	0:01f31e923fe2	6522	#define UART_MODEM_TXCTSE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6523	#define UART_MODEM_TXCTSE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6524	#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
Pawel Zarembski	0:01f31e923fe2	6525	#define UART_MODEM_TXRTSE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6526	#define UART_MODEM_TXRTSE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6527	#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
Pawel Zarembski	0:01f31e923fe2	6528	#define UART_MODEM_TXRTSPOL_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6529	#define UART_MODEM_TXRTSPOL_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6530	#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	6531	#define UART_MODEM_RXRTSE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6532	#define UART_MODEM_RXRTSE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6533	#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
Pawel Zarembski	0:01f31e923fe2	6534
Pawel Zarembski	0:01f31e923fe2	6535	/! @name IR - UART Infrared Register /
Pawel Zarembski	0:01f31e923fe2	6536	#define UART_IR_TNP_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	6537	#define UART_IR_TNP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6538	#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
Pawel Zarembski	0:01f31e923fe2	6539	#define UART_IR_IREN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6540	#define UART_IR_IREN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6541	#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
Pawel Zarembski	0:01f31e923fe2	6542
Pawel Zarembski	0:01f31e923fe2	6543	/! @name PFIFO - UART FIFO Parameters /
Pawel Zarembski	0:01f31e923fe2	6544	#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	6545	#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6546	#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	6547	#define UART_PFIFO_RXFE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6548	#define UART_PFIFO_RXFE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6549	#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
Pawel Zarembski	0:01f31e923fe2	6550	#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
Pawel Zarembski	0:01f31e923fe2	6551	#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6552	#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	6553	#define UART_PFIFO_TXFE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6554	#define UART_PFIFO_TXFE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6555	#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
Pawel Zarembski	0:01f31e923fe2	6556
Pawel Zarembski	0:01f31e923fe2	6557	/! @name CFIFO - UART FIFO Control Register /
Pawel Zarembski	0:01f31e923fe2	6558	#define UART_CFIFO_RXUFE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6559	#define UART_CFIFO_RXUFE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6560	#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
Pawel Zarembski	0:01f31e923fe2	6561	#define UART_CFIFO_TXOFE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6562	#define UART_CFIFO_TXOFE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6563	#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
Pawel Zarembski	0:01f31e923fe2	6564	#define UART_CFIFO_RXFLUSH_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6565	#define UART_CFIFO_RXFLUSH_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6566	#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
Pawel Zarembski	0:01f31e923fe2	6567	#define UART_CFIFO_TXFLUSH_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6568	#define UART_CFIFO_TXFLUSH_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6569	#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
Pawel Zarembski	0:01f31e923fe2	6570
Pawel Zarembski	0:01f31e923fe2	6571	/! @name SFIFO - UART FIFO Status Register /
Pawel Zarembski	0:01f31e923fe2	6572	#define UART_SFIFO_RXUF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6573	#define UART_SFIFO_RXUF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6574	#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
Pawel Zarembski	0:01f31e923fe2	6575	#define UART_SFIFO_TXOF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6576	#define UART_SFIFO_TXOF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6577	#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
Pawel Zarembski	0:01f31e923fe2	6578	#define UART_SFIFO_RXEMPT_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6579	#define UART_SFIFO_RXEMPT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6580	#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
Pawel Zarembski	0:01f31e923fe2	6581	#define UART_SFIFO_TXEMPT_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6582	#define UART_SFIFO_TXEMPT_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6583	#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
Pawel Zarembski	0:01f31e923fe2	6584
Pawel Zarembski	0:01f31e923fe2	6585	/! @name TWFIFO - UART FIFO Transmit Watermark /
Pawel Zarembski	0:01f31e923fe2	6586	#define UART_TWFIFO_TXWATER_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6587	#define UART_TWFIFO_TXWATER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6588	#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
Pawel Zarembski	0:01f31e923fe2	6589
Pawel Zarembski	0:01f31e923fe2	6590	/! @name TCFIFO - UART FIFO Transmit Count /
Pawel Zarembski	0:01f31e923fe2	6591	#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6592	#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6593	#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
Pawel Zarembski	0:01f31e923fe2	6594
Pawel Zarembski	0:01f31e923fe2	6595	/! @name RWFIFO - UART FIFO Receive Watermark /
Pawel Zarembski	0:01f31e923fe2	6596	#define UART_RWFIFO_RXWATER_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6597	#define UART_RWFIFO_RXWATER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6598	#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
Pawel Zarembski	0:01f31e923fe2	6599
Pawel Zarembski	0:01f31e923fe2	6600	/! @name RCFIFO - UART FIFO Receive Count /
Pawel Zarembski	0:01f31e923fe2	6601	#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6602	#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6603	#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
Pawel Zarembski	0:01f31e923fe2	6604
Pawel Zarembski	0:01f31e923fe2	6605	/! @name C7816 - UART 7816 Control Register /
Pawel Zarembski	0:01f31e923fe2	6606	#define UART_C7816_ISO_7816E_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6607	#define UART_C7816_ISO_7816E_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6608	#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
Pawel Zarembski	0:01f31e923fe2	6609	#define UART_C7816_TTYPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6610	#define UART_C7816_TTYPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6611	#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
Pawel Zarembski	0:01f31e923fe2	6612	#define UART_C7816_INIT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6613	#define UART_C7816_INIT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6614	#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
Pawel Zarembski	0:01f31e923fe2	6615	#define UART_C7816_ANACK_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6616	#define UART_C7816_ANACK_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6617	#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
Pawel Zarembski	0:01f31e923fe2	6618	#define UART_C7816_ONACK_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6619	#define UART_C7816_ONACK_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6620	#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
Pawel Zarembski	0:01f31e923fe2	6621
Pawel Zarembski	0:01f31e923fe2	6622	/! @name IE7816 - UART 7816 Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	6623	#define UART_IE7816_RXTE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6624	#define UART_IE7816_RXTE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6625	#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
Pawel Zarembski	0:01f31e923fe2	6626	#define UART_IE7816_TXTE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6627	#define UART_IE7816_TXTE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6628	#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
Pawel Zarembski	0:01f31e923fe2	6629	#define UART_IE7816_GTVE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6630	#define UART_IE7816_GTVE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6631	#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
Pawel Zarembski	0:01f31e923fe2	6632	#define UART_IE7816_INITDE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6633	#define UART_IE7816_INITDE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6634	#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
Pawel Zarembski	0:01f31e923fe2	6635	#define UART_IE7816_BWTE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6636	#define UART_IE7816_BWTE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6637	#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
Pawel Zarembski	0:01f31e923fe2	6638	#define UART_IE7816_CWTE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6639	#define UART_IE7816_CWTE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6640	#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
Pawel Zarembski	0:01f31e923fe2	6641	#define UART_IE7816_WTE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6642	#define UART_IE7816_WTE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6643	#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
Pawel Zarembski	0:01f31e923fe2	6644
Pawel Zarembski	0:01f31e923fe2	6645	/! @name IS7816 - UART 7816 Interrupt Status Register /
Pawel Zarembski	0:01f31e923fe2	6646	#define UART_IS7816_RXT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6647	#define UART_IS7816_RXT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6648	#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
Pawel Zarembski	0:01f31e923fe2	6649	#define UART_IS7816_TXT_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6650	#define UART_IS7816_TXT_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6651	#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
Pawel Zarembski	0:01f31e923fe2	6652	#define UART_IS7816_GTV_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6653	#define UART_IS7816_GTV_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6654	#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
Pawel Zarembski	0:01f31e923fe2	6655	#define UART_IS7816_INITD_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6656	#define UART_IS7816_INITD_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6657	#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
Pawel Zarembski	0:01f31e923fe2	6658	#define UART_IS7816_BWT_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6659	#define UART_IS7816_BWT_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6660	#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
Pawel Zarembski	0:01f31e923fe2	6661	#define UART_IS7816_CWT_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6662	#define UART_IS7816_CWT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6663	#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
Pawel Zarembski	0:01f31e923fe2	6664	#define UART_IS7816_WT_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6665	#define UART_IS7816_WT_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6666	#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
Pawel Zarembski	0:01f31e923fe2	6667
Pawel Zarembski	0:01f31e923fe2	6668	/! @name WP7816T0 - UART 7816 Wait Parameter Register /
Pawel Zarembski	0:01f31e923fe2	6669	#define UART_WP7816T0_WI_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6670	#define UART_WP7816T0_WI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6671	#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
Pawel Zarembski	0:01f31e923fe2	6672
Pawel Zarembski	0:01f31e923fe2	6673	/! @name WP7816T1 - UART 7816 Wait Parameter Register /
Pawel Zarembski	0:01f31e923fe2	6674	#define UART_WP7816T1_BWI_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	6675	#define UART_WP7816T1_BWI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6676	#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
Pawel Zarembski	0:01f31e923fe2	6677	#define UART_WP7816T1_CWI_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	6678	#define UART_WP7816T1_CWI_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6679	#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
Pawel Zarembski	0:01f31e923fe2	6680
Pawel Zarembski	0:01f31e923fe2	6681	/! @name WN7816 - UART 7816 Wait N Register /
Pawel Zarembski	0:01f31e923fe2	6682	#define UART_WN7816_GTN_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6683	#define UART_WN7816_GTN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6684	#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
Pawel Zarembski	0:01f31e923fe2	6685
Pawel Zarembski	0:01f31e923fe2	6686	/! @name WF7816 - UART 7816 Wait FD Register /
Pawel Zarembski	0:01f31e923fe2	6687	#define UART_WF7816_GTFD_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6688	#define UART_WF7816_GTFD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6689	#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
Pawel Zarembski	0:01f31e923fe2	6690
Pawel Zarembski	0:01f31e923fe2	6691	/! @name ET7816 - UART 7816 Error Threshold Register /
Pawel Zarembski	0:01f31e923fe2	6692	#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	6693	#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6694	#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
Pawel Zarembski	0:01f31e923fe2	6695	#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	6696	#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6697	#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
Pawel Zarembski	0:01f31e923fe2	6698
Pawel Zarembski	0:01f31e923fe2	6699	/! @name TL7816 - UART 7816 Transmit Length Register /
Pawel Zarembski	0:01f31e923fe2	6700	#define UART_TL7816_TLEN_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6701	#define UART_TL7816_TLEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6702	#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
Pawel Zarembski	0:01f31e923fe2	6703
Pawel Zarembski	0:01f31e923fe2	6704	/! @name C6 - UART CEA709.1-B Control Register 6 /
Pawel Zarembski	0:01f31e923fe2	6705	#define UART_C6_CP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6706	#define UART_C6_CP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6707	#define UART_C6_CP(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CP_SHIFT)) & UART_C6_CP_MASK)
Pawel Zarembski	0:01f31e923fe2	6708	#define UART_C6_CE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6709	#define UART_C6_CE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6710	#define UART_C6_CE(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CE_SHIFT)) & UART_C6_CE_MASK)
Pawel Zarembski	0:01f31e923fe2	6711	#define UART_C6_TX709_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6712	#define UART_C6_TX709_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6713	#define UART_C6_TX709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_TX709_SHIFT)) & UART_C6_TX709_MASK)
Pawel Zarembski	0:01f31e923fe2	6714	#define UART_C6_EN709_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6715	#define UART_C6_EN709_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6716	#define UART_C6_EN709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_EN709_SHIFT)) & UART_C6_EN709_MASK)
Pawel Zarembski	0:01f31e923fe2	6717
Pawel Zarembski	0:01f31e923fe2	6718	/! @name PCTH - UART CEA709.1-B Packet Cycle Time Counter High /
Pawel Zarembski	0:01f31e923fe2	6719	#define UART_PCTH_PCTH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6720	#define UART_PCTH_PCTH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6721	#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTH_PCTH_SHIFT)) & UART_PCTH_PCTH_MASK)
Pawel Zarembski	0:01f31e923fe2	6722
Pawel Zarembski	0:01f31e923fe2	6723	/! @name PCTL - UART CEA709.1-B Packet Cycle Time Counter Low /
Pawel Zarembski	0:01f31e923fe2	6724	#define UART_PCTL_PCTL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6725	#define UART_PCTL_PCTL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6726	#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTL_PCTL_SHIFT)) & UART_PCTL_PCTL_MASK)
Pawel Zarembski	0:01f31e923fe2	6727
Pawel Zarembski	0:01f31e923fe2	6728	/! @name B1T - UART CEA709.1-B Beta1 Timer /
Pawel Zarembski	0:01f31e923fe2	6729	#define UART_B1T_B1T_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6730	#define UART_B1T_B1T_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6731	#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x)) << UART_B1T_B1T_SHIFT)) & UART_B1T_B1T_MASK)
Pawel Zarembski	0:01f31e923fe2	6732
Pawel Zarembski	0:01f31e923fe2	6733	/! @name SDTH - UART CEA709.1-B Secondary Delay Timer High /
Pawel Zarembski	0:01f31e923fe2	6734	#define UART_SDTH_SDTH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6735	#define UART_SDTH_SDTH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6736	#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTH_SDTH_SHIFT)) & UART_SDTH_SDTH_MASK)
Pawel Zarembski	0:01f31e923fe2	6737
Pawel Zarembski	0:01f31e923fe2	6738	/! @name SDTL - UART CEA709.1-B Secondary Delay Timer Low /
Pawel Zarembski	0:01f31e923fe2	6739	#define UART_SDTL_SDTL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6740	#define UART_SDTL_SDTL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6741	#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTL_SDTL_SHIFT)) & UART_SDTL_SDTL_MASK)
Pawel Zarembski	0:01f31e923fe2	6742
Pawel Zarembski	0:01f31e923fe2	6743	/! @name PRE - UART CEA709.1-B Preamble /
Pawel Zarembski	0:01f31e923fe2	6744	#define UART_PRE_PREAMBLE_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6745	#define UART_PRE_PREAMBLE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6746	#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x)) << UART_PRE_PREAMBLE_SHIFT)) & UART_PRE_PREAMBLE_MASK)
Pawel Zarembski	0:01f31e923fe2	6747
Pawel Zarembski	0:01f31e923fe2	6748	/! @name TPL - UART CEA709.1-B Transmit Packet Length /
Pawel Zarembski	0:01f31e923fe2	6749	#define UART_TPL_TPL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6750	#define UART_TPL_TPL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6751	#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x)) << UART_TPL_TPL_SHIFT)) & UART_TPL_TPL_MASK)
Pawel Zarembski	0:01f31e923fe2	6752
Pawel Zarembski	0:01f31e923fe2	6753	/! @name IE - UART CEA709.1-B Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	6754	#define UART_IE_TXFIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6755	#define UART_IE_TXFIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6756	#define UART_IE_TXFIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_TXFIE_SHIFT)) & UART_IE_TXFIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6757	#define UART_IE_PSIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6758	#define UART_IE_PSIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6759	#define UART_IE_PSIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PSIE_SHIFT)) & UART_IE_PSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6760	#define UART_IE_PCTEIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6761	#define UART_IE_PCTEIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6762	#define UART_IE_PCTEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PCTEIE_SHIFT)) & UART_IE_PCTEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6763	#define UART_IE_PTXIE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6764	#define UART_IE_PTXIE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6765	#define UART_IE_PTXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PTXIE_SHIFT)) & UART_IE_PTXIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6766	#define UART_IE_PRXIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6767	#define UART_IE_PRXIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6768	#define UART_IE_PRXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PRXIE_SHIFT)) & UART_IE_PRXIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6769	#define UART_IE_ISDIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6770	#define UART_IE_ISDIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6771	#define UART_IE_ISDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_ISDIE_SHIFT)) & UART_IE_ISDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6772	#define UART_IE_WBEIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6773	#define UART_IE_WBEIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6774	#define UART_IE_WBEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_WBEIE_SHIFT)) & UART_IE_WBEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	6775
Pawel Zarembski	0:01f31e923fe2	6776	/! @name WB - UART CEA709.1-B WBASE /
Pawel Zarembski	0:01f31e923fe2	6777	#define UART_WB_WBASE_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6778	#define UART_WB_WBASE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6779	#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x)) << UART_WB_WBASE_SHIFT)) & UART_WB_WBASE_MASK)
Pawel Zarembski	0:01f31e923fe2	6780
Pawel Zarembski	0:01f31e923fe2	6781	/! @name S3 - UART CEA709.1-B Status Register /
Pawel Zarembski	0:01f31e923fe2	6782	#define UART_S3_TXFF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6783	#define UART_S3_TXFF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6784	#define UART_S3_TXFF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_TXFF_SHIFT)) & UART_S3_TXFF_MASK)
Pawel Zarembski	0:01f31e923fe2	6785	#define UART_S3_PSF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6786	#define UART_S3_PSF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6787	#define UART_S3_PSF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PSF_SHIFT)) & UART_S3_PSF_MASK)
Pawel Zarembski	0:01f31e923fe2	6788	#define UART_S3_PCTEF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6789	#define UART_S3_PCTEF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6790	#define UART_S3_PCTEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PCTEF_SHIFT)) & UART_S3_PCTEF_MASK)
Pawel Zarembski	0:01f31e923fe2	6791	#define UART_S3_PTXF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6792	#define UART_S3_PTXF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6793	#define UART_S3_PTXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PTXF_SHIFT)) & UART_S3_PTXF_MASK)
Pawel Zarembski	0:01f31e923fe2	6794	#define UART_S3_PRXF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6795	#define UART_S3_PRXF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6796	#define UART_S3_PRXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PRXF_SHIFT)) & UART_S3_PRXF_MASK)
Pawel Zarembski	0:01f31e923fe2	6797	#define UART_S3_ISD_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6798	#define UART_S3_ISD_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6799	#define UART_S3_ISD(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_ISD_SHIFT)) & UART_S3_ISD_MASK)
Pawel Zarembski	0:01f31e923fe2	6800	#define UART_S3_WBEF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6801	#define UART_S3_WBEF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6802	#define UART_S3_WBEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_WBEF_SHIFT)) & UART_S3_WBEF_MASK)
Pawel Zarembski	0:01f31e923fe2	6803	#define UART_S3_PEF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6804	#define UART_S3_PEF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6805	#define UART_S3_PEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PEF_SHIFT)) & UART_S3_PEF_MASK)
Pawel Zarembski	0:01f31e923fe2	6806
Pawel Zarembski	0:01f31e923fe2	6807	/! @name S4 - UART CEA709.1-B Status Register /
Pawel Zarembski	0:01f31e923fe2	6808	#define UART_S4_FE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6809	#define UART_S4_FE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6810	#define UART_S4_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_FE_SHIFT)) & UART_S4_FE_MASK)
Pawel Zarembski	0:01f31e923fe2	6811	#define UART_S4_ILCV_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	6812	#define UART_S4_ILCV_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	6813	#define UART_S4_ILCV(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_ILCV_SHIFT)) & UART_S4_ILCV_MASK)
Pawel Zarembski	0:01f31e923fe2	6814	#define UART_S4_CDET_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	6815	#define UART_S4_CDET_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6816	#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_CDET_SHIFT)) & UART_S4_CDET_MASK)
Pawel Zarembski	0:01f31e923fe2	6817	#define UART_S4_INITF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	6818	#define UART_S4_INITF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	6819	#define UART_S4_INITF(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_INITF_SHIFT)) & UART_S4_INITF_MASK)
Pawel Zarembski	0:01f31e923fe2	6820
Pawel Zarembski	0:01f31e923fe2	6821	/! @name RPL - UART CEA709.1-B Received Packet Length /
Pawel Zarembski	0:01f31e923fe2	6822	#define UART_RPL_RPL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6823	#define UART_RPL_RPL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6824	#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPL_RPL_SHIFT)) & UART_RPL_RPL_MASK)
Pawel Zarembski	0:01f31e923fe2	6825
Pawel Zarembski	0:01f31e923fe2	6826	/! @name RPREL - UART CEA709.1-B Received Preamble Length /
Pawel Zarembski	0:01f31e923fe2	6827	#define UART_RPREL_RPREL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6828	#define UART_RPREL_RPREL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6829	#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPREL_RPREL_SHIFT)) & UART_RPREL_RPREL_MASK)
Pawel Zarembski	0:01f31e923fe2	6830
Pawel Zarembski	0:01f31e923fe2	6831	/! @name CPW - UART CEA709.1-B Collision Pulse Width /
Pawel Zarembski	0:01f31e923fe2	6832	#define UART_CPW_CPW_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6833	#define UART_CPW_CPW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6834	#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x)) << UART_CPW_CPW_SHIFT)) & UART_CPW_CPW_MASK)
Pawel Zarembski	0:01f31e923fe2	6835
Pawel Zarembski	0:01f31e923fe2	6836	/! @name RIDT - UART CEA709.1-B Receive Indeterminate Time /
Pawel Zarembski	0:01f31e923fe2	6837	#define UART_RIDT_RIDT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6838	#define UART_RIDT_RIDT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6839	#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_RIDT_RIDT_SHIFT)) & UART_RIDT_RIDT_MASK)
Pawel Zarembski	0:01f31e923fe2	6840
Pawel Zarembski	0:01f31e923fe2	6841	/! @name TIDT - UART CEA709.1-B Transmit Indeterminate Time /
Pawel Zarembski	0:01f31e923fe2	6842	#define UART_TIDT_TIDT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6843	#define UART_TIDT_TIDT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6844	#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_TIDT_TIDT_SHIFT)) & UART_TIDT_TIDT_MASK)
Pawel Zarembski	0:01f31e923fe2	6845
Pawel Zarembski	0:01f31e923fe2	6846
Pawel Zarembski	0:01f31e923fe2	6847	/*!
Pawel Zarembski	0:01f31e923fe2	6848	* @}
Pawel Zarembski	0:01f31e923fe2	6849	/ / end of group UART_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	6850
Pawel Zarembski	0:01f31e923fe2	6851
Pawel Zarembski	0:01f31e923fe2	6852	/* UART - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	6853	/** Peripheral UART0 base address */
Pawel Zarembski	0:01f31e923fe2	6854	#define UART0_BASE (0x4006A000u)
Pawel Zarembski	0:01f31e923fe2	6855	/** Peripheral UART0 base pointer */
Pawel Zarembski	0:01f31e923fe2	6856	#define UART0 ((UART_Type *)UART0_BASE)
Pawel Zarembski	0:01f31e923fe2	6857	/** Peripheral UART1 base address */
Pawel Zarembski	0:01f31e923fe2	6858	#define UART1_BASE (0x4006B000u)
Pawel Zarembski	0:01f31e923fe2	6859	/** Peripheral UART1 base pointer */
Pawel Zarembski	0:01f31e923fe2	6860	#define UART1 ((UART_Type *)UART1_BASE)
Pawel Zarembski	0:01f31e923fe2	6861	/** Peripheral UART2 base address */
Pawel Zarembski	0:01f31e923fe2	6862	#define UART2_BASE (0x4006C000u)
Pawel Zarembski	0:01f31e923fe2	6863	/** Peripheral UART2 base pointer */
Pawel Zarembski	0:01f31e923fe2	6864	#define UART2 ((UART_Type *)UART2_BASE)
Pawel Zarembski	0:01f31e923fe2	6865	/** Array initializer of UART peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	6866	#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
Pawel Zarembski	0:01f31e923fe2	6867	/** Array initializer of UART peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	6868	#define UART_BASE_PTRS { UART0, UART1, UART2 }
Pawel Zarembski	0:01f31e923fe2	6869	/** Interrupt vectors for the UART peripheral type */
Pawel Zarembski	0:01f31e923fe2	6870	#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
Pawel Zarembski	0:01f31e923fe2	6871	#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
Pawel Zarembski	0:01f31e923fe2	6872	#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn }
Pawel Zarembski	0:01f31e923fe2	6873
Pawel Zarembski	0:01f31e923fe2	6874	/*!
Pawel Zarembski	0:01f31e923fe2	6875	* @}
Pawel Zarembski	0:01f31e923fe2	6876	/ / end of group UART_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	6877
Pawel Zarembski	0:01f31e923fe2	6878
Pawel Zarembski	0:01f31e923fe2	6879	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6880	-- USB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6881	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6882
Pawel Zarembski	0:01f31e923fe2	6883	/*!
Pawel Zarembski	0:01f31e923fe2	6884	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	6885	* @{
Pawel Zarembski	0:01f31e923fe2	6886	*/
Pawel Zarembski	0:01f31e923fe2	6887
Pawel Zarembski	0:01f31e923fe2	6888	/** USB - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	6889	typedef struct {
Pawel Zarembski	0:01f31e923fe2	6890	__I uint8_t PERID; /*< Peripheral ID Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	6891	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	6892	__I uint8_t IDCOMP; /*< Peripheral ID Complement Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	6893	uint8_t RESERVED_1[3];
Pawel Zarembski	0:01f31e923fe2	6894	__I uint8_t REV; /*< Peripheral Revision Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	6895	uint8_t RESERVED_2[3];
Pawel Zarembski	0:01f31e923fe2	6896	__I uint8_t ADDINFO; /*< Peripheral Additional Info Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	6897	uint8_t RESERVED_3[3];
Pawel Zarembski	0:01f31e923fe2	6898	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	6899	uint8_t RESERVED_4[3];
Pawel Zarembski	0:01f31e923fe2	6900	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	6901	uint8_t RESERVED_5[3];
Pawel Zarembski	0:01f31e923fe2	6902	__IO uint8_t OTGSTAT; /*< OTG Status Register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	6903	uint8_t RESERVED_6[3];
Pawel Zarembski	0:01f31e923fe2	6904	__IO uint8_t OTGCTL; /*< OTG Control Register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	6905	uint8_t RESERVED_7[99];
Pawel Zarembski	0:01f31e923fe2	6906	__IO uint8_t ISTAT; /*< Interrupt Status Register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	6907	uint8_t RESERVED_8[3];
Pawel Zarembski	0:01f31e923fe2	6908	__IO uint8_t INTEN; /*< Interrupt Enable Register, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	6909	uint8_t RESERVED_9[3];
Pawel Zarembski	0:01f31e923fe2	6910	__IO uint8_t ERRSTAT; /*< Error Interrupt Status Register, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	6911	uint8_t RESERVED_10[3];
Pawel Zarembski	0:01f31e923fe2	6912	__IO uint8_t ERREN; /*< Error Interrupt Enable Register, offset: 0x8C /
Pawel Zarembski	0:01f31e923fe2	6913	uint8_t RESERVED_11[3];
Pawel Zarembski	0:01f31e923fe2	6914	__I uint8_t STAT; /*< Status Register, offset: 0x90 /
Pawel Zarembski	0:01f31e923fe2	6915	uint8_t RESERVED_12[3];
Pawel Zarembski	0:01f31e923fe2	6916	__IO uint8_t CTL; /*< Control Register, offset: 0x94 /
Pawel Zarembski	0:01f31e923fe2	6917	uint8_t RESERVED_13[3];
Pawel Zarembski	0:01f31e923fe2	6918	__IO uint8_t ADDR; /*< Address Register, offset: 0x98 /
Pawel Zarembski	0:01f31e923fe2	6919	uint8_t RESERVED_14[3];
Pawel Zarembski	0:01f31e923fe2	6920	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
Pawel Zarembski	0:01f31e923fe2	6921	uint8_t RESERVED_15[3];
Pawel Zarembski	0:01f31e923fe2	6922	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
Pawel Zarembski	0:01f31e923fe2	6923	uint8_t RESERVED_16[3];
Pawel Zarembski	0:01f31e923fe2	6924	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
Pawel Zarembski	0:01f31e923fe2	6925	uint8_t RESERVED_17[3];
Pawel Zarembski	0:01f31e923fe2	6926	__IO uint8_t TOKEN; /*< Token Register, offset: 0xA8 /
Pawel Zarembski	0:01f31e923fe2	6927	uint8_t RESERVED_18[3];
Pawel Zarembski	0:01f31e923fe2	6928	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
Pawel Zarembski	0:01f31e923fe2	6929	uint8_t RESERVED_19[3];
Pawel Zarembski	0:01f31e923fe2	6930	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
Pawel Zarembski	0:01f31e923fe2	6931	uint8_t RESERVED_20[3];
Pawel Zarembski	0:01f31e923fe2	6932	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
Pawel Zarembski	0:01f31e923fe2	6933	uint8_t RESERVED_21[11];
Pawel Zarembski	0:01f31e923fe2	6934	struct { /* offset: 0xC0, array step: 0x4 */
Pawel Zarembski	0:01f31e923fe2	6935	__IO uint8_t ENDPT; /*< Endpoint Control Register, array offset: 0xC0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	6936	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	6937	} ENDPOINT[16];
Pawel Zarembski	0:01f31e923fe2	6938	__IO uint8_t USBCTRL; /*< USB Control Register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	6939	uint8_t RESERVED_22[3];
Pawel Zarembski	0:01f31e923fe2	6940	__I uint8_t OBSERVE; /*< USB OTG Observe Register, offset: 0x104 /
Pawel Zarembski	0:01f31e923fe2	6941	uint8_t RESERVED_23[3];
Pawel Zarembski	0:01f31e923fe2	6942	__IO uint8_t CONTROL; /*< USB OTG Control Register, offset: 0x108 /
Pawel Zarembski	0:01f31e923fe2	6943	uint8_t RESERVED_24[3];
Pawel Zarembski	0:01f31e923fe2	6944	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
Pawel Zarembski	0:01f31e923fe2	6945	uint8_t RESERVED_25[7];
Pawel Zarembski	0:01f31e923fe2	6946	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
Pawel Zarembski	0:01f31e923fe2	6947	} USB_Type;
Pawel Zarembski	0:01f31e923fe2	6948
Pawel Zarembski	0:01f31e923fe2	6949	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	6950	-- USB Register Masks
Pawel Zarembski	0:01f31e923fe2	6951	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	6952
Pawel Zarembski	0:01f31e923fe2	6953	/*!
Pawel Zarembski	0:01f31e923fe2	6954	* @addtogroup USB_Register_Masks USB Register Masks
Pawel Zarembski	0:01f31e923fe2	6955	* @{
Pawel Zarembski	0:01f31e923fe2	6956	*/
Pawel Zarembski	0:01f31e923fe2	6957
Pawel Zarembski	0:01f31e923fe2	6958	/! @name PERID - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	6959	#define USB_PERID_ID_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	6960	#define USB_PERID_ID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6961	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
Pawel Zarembski	0:01f31e923fe2	6962
Pawel Zarembski	0:01f31e923fe2	6963	/! @name IDCOMP - Peripheral ID Complement Register /
Pawel Zarembski	0:01f31e923fe2	6964	#define USB_IDCOMP_NID_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	6965	#define USB_IDCOMP_NID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6966	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
Pawel Zarembski	0:01f31e923fe2	6967
Pawel Zarembski	0:01f31e923fe2	6968	/! @name REV - Peripheral Revision Register /
Pawel Zarembski	0:01f31e923fe2	6969	#define USB_REV_REV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	6970	#define USB_REV_REV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6971	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
Pawel Zarembski	0:01f31e923fe2	6972
Pawel Zarembski	0:01f31e923fe2	6973	/! @name ADDINFO - Peripheral Additional Info Register /
Pawel Zarembski	0:01f31e923fe2	6974	#define USB_ADDINFO_IEHOST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6975	#define USB_ADDINFO_IEHOST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6976	#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
Pawel Zarembski	0:01f31e923fe2	6977	#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
Pawel Zarembski	0:01f31e923fe2	6978	#define USB_ADDINFO_IRQNUM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6979	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
Pawel Zarembski	0:01f31e923fe2	6980
Pawel Zarembski	0:01f31e923fe2	6981	/! @name OTGISTAT - OTG Interrupt Status Register /
Pawel Zarembski	0:01f31e923fe2	6982	#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	6983	#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	6984	#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	6985	#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	6986	#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	6987	#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
Pawel Zarembski	0:01f31e923fe2	6988	#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	6989	#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	6990	#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	6991	#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	6992	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	6993	#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
Pawel Zarembski	0:01f31e923fe2	6994	#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	6995	#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	6996	#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
Pawel Zarembski	0:01f31e923fe2	6997	#define USB_OTGISTAT_IDCHG_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	6998	#define USB_OTGISTAT_IDCHG_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	6999	#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	7000
Pawel Zarembski	0:01f31e923fe2	7001	/! @name OTGICR - OTG Interrupt Control Register /
Pawel Zarembski	0:01f31e923fe2	7002	#define USB_OTGICR_AVBUSEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7003	#define USB_OTGICR_AVBUSEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7004	#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7005	#define USB_OTGICR_BSESSEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7006	#define USB_OTGICR_BSESSEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7007	#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7008	#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7009	#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7010	#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7011	#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7012	#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7013	#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7014	#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7015	#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7016	#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7017	#define USB_OTGICR_IDEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7018	#define USB_OTGICR_IDEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7019	#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7020
Pawel Zarembski	0:01f31e923fe2	7021	/! @name OTGSTAT - OTG Status Register /
Pawel Zarembski	0:01f31e923fe2	7022	#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7023	#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7024	#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
Pawel Zarembski	0:01f31e923fe2	7025	#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7026	#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7027	#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
Pawel Zarembski	0:01f31e923fe2	7028	#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7029	#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7030	#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
Pawel Zarembski	0:01f31e923fe2	7031	#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7032	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7033	#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
Pawel Zarembski	0:01f31e923fe2	7034	#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7035	#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7036	#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7037	#define USB_OTGSTAT_ID_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7038	#define USB_OTGSTAT_ID_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7039	#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
Pawel Zarembski	0:01f31e923fe2	7040
Pawel Zarembski	0:01f31e923fe2	7041	/! @name OTGCTL - OTG Control Register /
Pawel Zarembski	0:01f31e923fe2	7042	#define USB_OTGCTL_OTGEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7043	#define USB_OTGCTL_OTGEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7044	#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7045	#define USB_OTGCTL_DMLOW_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7046	#define USB_OTGCTL_DMLOW_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7047	#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	7048	#define USB_OTGCTL_DPLOW_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7049	#define USB_OTGCTL_DPLOW_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7050	#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	7051	#define USB_OTGCTL_DPHIGH_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7052	#define USB_OTGCTL_DPHIGH_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7053	#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	7054
Pawel Zarembski	0:01f31e923fe2	7055	/! @name ISTAT - Interrupt Status Register /
Pawel Zarembski	0:01f31e923fe2	7056	#define USB_ISTAT_USBRST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7057	#define USB_ISTAT_USBRST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7058	#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
Pawel Zarembski	0:01f31e923fe2	7059	#define USB_ISTAT_ERROR_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7060	#define USB_ISTAT_ERROR_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7061	#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
Pawel Zarembski	0:01f31e923fe2	7062	#define USB_ISTAT_SOFTOK_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7063	#define USB_ISTAT_SOFTOK_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7064	#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
Pawel Zarembski	0:01f31e923fe2	7065	#define USB_ISTAT_TOKDNE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7066	#define USB_ISTAT_TOKDNE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7067	#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
Pawel Zarembski	0:01f31e923fe2	7068	#define USB_ISTAT_SLEEP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7069	#define USB_ISTAT_SLEEP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7070	#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
Pawel Zarembski	0:01f31e923fe2	7071	#define USB_ISTAT_RESUME_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7072	#define USB_ISTAT_RESUME_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7073	#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
Pawel Zarembski	0:01f31e923fe2	7074	#define USB_ISTAT_ATTACH_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7075	#define USB_ISTAT_ATTACH_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7076	#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
Pawel Zarembski	0:01f31e923fe2	7077	#define USB_ISTAT_STALL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7078	#define USB_ISTAT_STALL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7079	#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
Pawel Zarembski	0:01f31e923fe2	7080
Pawel Zarembski	0:01f31e923fe2	7081	/! @name INTEN - Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	7082	#define USB_INTEN_USBRSTEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7083	#define USB_INTEN_USBRSTEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7084	#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7085	#define USB_INTEN_ERROREN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7086	#define USB_INTEN_ERROREN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7087	#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
Pawel Zarembski	0:01f31e923fe2	7088	#define USB_INTEN_SOFTOKEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7089	#define USB_INTEN_SOFTOKEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7090	#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7091	#define USB_INTEN_TOKDNEEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7092	#define USB_INTEN_TOKDNEEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7093	#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7094	#define USB_INTEN_SLEEPEN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7095	#define USB_INTEN_SLEEPEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7096	#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7097	#define USB_INTEN_RESUMEEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7098	#define USB_INTEN_RESUMEEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7099	#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7100	#define USB_INTEN_ATTACHEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7101	#define USB_INTEN_ATTACHEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7102	#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7103	#define USB_INTEN_STALLEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7104	#define USB_INTEN_STALLEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7105	#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7106
Pawel Zarembski	0:01f31e923fe2	7107	/! @name ERRSTAT - Error Interrupt Status Register /
Pawel Zarembski	0:01f31e923fe2	7108	#define USB_ERRSTAT_PIDERR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7109	#define USB_ERRSTAT_PIDERR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7110	#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
Pawel Zarembski	0:01f31e923fe2	7111	#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7112	#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7113	#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
Pawel Zarembski	0:01f31e923fe2	7114	#define USB_ERRSTAT_CRC16_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7115	#define USB_ERRSTAT_CRC16_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7116	#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
Pawel Zarembski	0:01f31e923fe2	7117	#define USB_ERRSTAT_DFN8_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7118	#define USB_ERRSTAT_DFN8_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7119	#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
Pawel Zarembski	0:01f31e923fe2	7120	#define USB_ERRSTAT_BTOERR_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7121	#define USB_ERRSTAT_BTOERR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7122	#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
Pawel Zarembski	0:01f31e923fe2	7123	#define USB_ERRSTAT_DMAERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7124	#define USB_ERRSTAT_DMAERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7125	#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
Pawel Zarembski	0:01f31e923fe2	7126	#define USB_ERRSTAT_BTSERR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7127	#define USB_ERRSTAT_BTSERR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7128	#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
Pawel Zarembski	0:01f31e923fe2	7129
Pawel Zarembski	0:01f31e923fe2	7130	/! @name ERREN - Error Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	7131	#define USB_ERREN_PIDERREN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7132	#define USB_ERREN_PIDERREN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7133	#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	7134	#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7135	#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7136	#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7137	#define USB_ERREN_CRC16EN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7138	#define USB_ERREN_CRC16EN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7139	#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
Pawel Zarembski	0:01f31e923fe2	7140	#define USB_ERREN_DFN8EN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7141	#define USB_ERREN_DFN8EN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7142	#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
Pawel Zarembski	0:01f31e923fe2	7143	#define USB_ERREN_BTOERREN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7144	#define USB_ERREN_BTOERREN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7145	#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	7146	#define USB_ERREN_DMAERREN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7147	#define USB_ERREN_DMAERREN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7148	#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	7149	#define USB_ERREN_BTSERREN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7150	#define USB_ERREN_BTSERREN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7151	#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	7152
Pawel Zarembski	0:01f31e923fe2	7153	/! @name STAT - Status Register /
Pawel Zarembski	0:01f31e923fe2	7154	#define USB_STAT_ODD_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7155	#define USB_STAT_ODD_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7156	#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
Pawel Zarembski	0:01f31e923fe2	7157	#define USB_STAT_TX_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7158	#define USB_STAT_TX_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7159	#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
Pawel Zarembski	0:01f31e923fe2	7160	#define USB_STAT_ENDP_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	7161	#define USB_STAT_ENDP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7162	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
Pawel Zarembski	0:01f31e923fe2	7163
Pawel Zarembski	0:01f31e923fe2	7164	/! @name CTL - Control Register /
Pawel Zarembski	0:01f31e923fe2	7165	#define USB_CTL_USBENSOFEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7166	#define USB_CTL_USBENSOFEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7167	#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7168	#define USB_CTL_ODDRST_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7169	#define USB_CTL_ODDRST_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7170	#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
Pawel Zarembski	0:01f31e923fe2	7171	#define USB_CTL_RESUME_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7172	#define USB_CTL_RESUME_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7173	#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
Pawel Zarembski	0:01f31e923fe2	7174	#define USB_CTL_HOSTMODEEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7175	#define USB_CTL_HOSTMODEEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7176	#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7177	#define USB_CTL_RESET_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7178	#define USB_CTL_RESET_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7179	#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
Pawel Zarembski	0:01f31e923fe2	7180	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7181	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7182	#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
Pawel Zarembski	0:01f31e923fe2	7183	#define USB_CTL_SE0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7184	#define USB_CTL_SE0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7185	#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
Pawel Zarembski	0:01f31e923fe2	7186	#define USB_CTL_JSTATE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7187	#define USB_CTL_JSTATE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7188	#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
Pawel Zarembski	0:01f31e923fe2	7189
Pawel Zarembski	0:01f31e923fe2	7190	/! @name ADDR - Address Register /
Pawel Zarembski	0:01f31e923fe2	7191	#define USB_ADDR_ADDR_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	7192	#define USB_ADDR_ADDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7193	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
Pawel Zarembski	0:01f31e923fe2	7194	#define USB_ADDR_LSEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7195	#define USB_ADDR_LSEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7196	#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7197
Pawel Zarembski	0:01f31e923fe2	7198	/! @name BDTPAGE1 - BDT Page Register 1 /
Pawel Zarembski	0:01f31e923fe2	7199	#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	7200	#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7201	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	7202
Pawel Zarembski	0:01f31e923fe2	7203	/! @name FRMNUML - Frame Number Register Low /
Pawel Zarembski	0:01f31e923fe2	7204	#define USB_FRMNUML_FRM_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	7205	#define USB_FRMNUML_FRM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7206	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
Pawel Zarembski	0:01f31e923fe2	7207
Pawel Zarembski	0:01f31e923fe2	7208	/! @name FRMNUMH - Frame Number Register High /
Pawel Zarembski	0:01f31e923fe2	7209	#define USB_FRMNUMH_FRM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	7210	#define USB_FRMNUMH_FRM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7211	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
Pawel Zarembski	0:01f31e923fe2	7212
Pawel Zarembski	0:01f31e923fe2	7213	/! @name TOKEN - Token Register /
Pawel Zarembski	0:01f31e923fe2	7214	#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	7215	#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7216	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
Pawel Zarembski	0:01f31e923fe2	7217	#define USB_TOKEN_TOKENPID_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	7218	#define USB_TOKEN_TOKENPID_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7219	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
Pawel Zarembski	0:01f31e923fe2	7220
Pawel Zarembski	0:01f31e923fe2	7221	/! @name SOFTHLD - SOF Threshold Register /
Pawel Zarembski	0:01f31e923fe2	7222	#define USB_SOFTHLD_CNT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	7223	#define USB_SOFTHLD_CNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7224	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
Pawel Zarembski	0:01f31e923fe2	7225
Pawel Zarembski	0:01f31e923fe2	7226	/! @name BDTPAGE2 - BDT Page Register 2 /
Pawel Zarembski	0:01f31e923fe2	7227	#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	7228	#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7229	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	7230
Pawel Zarembski	0:01f31e923fe2	7231	/! @name BDTPAGE3 - BDT Page Register 3 /
Pawel Zarembski	0:01f31e923fe2	7232	#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	7233	#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7234	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	7235
Pawel Zarembski	0:01f31e923fe2	7236	/! @name ENDPT - Endpoint Control Register /
Pawel Zarembski	0:01f31e923fe2	7237	#define USB_ENDPT_EPHSHK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7238	#define USB_ENDPT_EPHSHK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7239	#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
Pawel Zarembski	0:01f31e923fe2	7240	#define USB_ENDPT_EPSTALL_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7241	#define USB_ENDPT_EPSTALL_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7242	#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
Pawel Zarembski	0:01f31e923fe2	7243	#define USB_ENDPT_EPTXEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7244	#define USB_ENDPT_EPTXEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7245	#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7246	#define USB_ENDPT_EPRXEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7247	#define USB_ENDPT_EPRXEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7248	#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7249	#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7250	#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7251	#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	7252	#define USB_ENDPT_RETRYDIS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7253	#define USB_ENDPT_RETRYDIS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7254	#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	7255	#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7256	#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7257	#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
Pawel Zarembski	0:01f31e923fe2	7258
Pawel Zarembski	0:01f31e923fe2	7259	/* The count of USB_ENDPT */
Pawel Zarembski	0:01f31e923fe2	7260	#define USB_ENDPT_COUNT (16U)
Pawel Zarembski	0:01f31e923fe2	7261
Pawel Zarembski	0:01f31e923fe2	7262	/! @name USBCTRL - USB Control Register /
Pawel Zarembski	0:01f31e923fe2	7263	#define USB_USBCTRL_PDE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7264	#define USB_USBCTRL_PDE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7265	#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
Pawel Zarembski	0:01f31e923fe2	7266	#define USB_USBCTRL_SUSP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7267	#define USB_USBCTRL_SUSP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7268	#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
Pawel Zarembski	0:01f31e923fe2	7269
Pawel Zarembski	0:01f31e923fe2	7270	/! @name OBSERVE - USB OTG Observe Register /
Pawel Zarembski	0:01f31e923fe2	7271	#define USB_OBSERVE_DMPD_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7272	#define USB_OBSERVE_DMPD_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7273	#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
Pawel Zarembski	0:01f31e923fe2	7274	#define USB_OBSERVE_DPPD_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7275	#define USB_OBSERVE_DPPD_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7276	#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
Pawel Zarembski	0:01f31e923fe2	7277	#define USB_OBSERVE_DPPU_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7278	#define USB_OBSERVE_DPPU_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7279	#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
Pawel Zarembski	0:01f31e923fe2	7280
Pawel Zarembski	0:01f31e923fe2	7281	/! @name CONTROL - USB OTG Control Register /
Pawel Zarembski	0:01f31e923fe2	7282	#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7283	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7284	#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
Pawel Zarembski	0:01f31e923fe2	7285
Pawel Zarembski	0:01f31e923fe2	7286	/! @name USBTRC0 - USB Transceiver Control Register 0 /
Pawel Zarembski	0:01f31e923fe2	7287	#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7288	#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7289	#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
Pawel Zarembski	0:01f31e923fe2	7290	#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7291	#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7292	#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
Pawel Zarembski	0:01f31e923fe2	7293	#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7294	#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7295	#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7296	#define USB_USBTRC0_USBRESET_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7297	#define USB_USBTRC0_USBRESET_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7298	#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
Pawel Zarembski	0:01f31e923fe2	7299
Pawel Zarembski	0:01f31e923fe2	7300	/! @name USBFRMADJUST - Frame Adjust Register /
Pawel Zarembski	0:01f31e923fe2	7301	#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	7302	#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7303	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
Pawel Zarembski	0:01f31e923fe2	7304
Pawel Zarembski	0:01f31e923fe2	7305
Pawel Zarembski	0:01f31e923fe2	7306	/*!
Pawel Zarembski	0:01f31e923fe2	7307	* @}
Pawel Zarembski	0:01f31e923fe2	7308	/ / end of group USB_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	7309
Pawel Zarembski	0:01f31e923fe2	7310
Pawel Zarembski	0:01f31e923fe2	7311	/* USB - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	7312	/** Peripheral USB0 base address */
Pawel Zarembski	0:01f31e923fe2	7313	#define USB0_BASE (0x40072000u)
Pawel Zarembski	0:01f31e923fe2	7314	/** Peripheral USB0 base pointer */
Pawel Zarembski	0:01f31e923fe2	7315	#define USB0 ((USB_Type *)USB0_BASE)
Pawel Zarembski	0:01f31e923fe2	7316	/** Array initializer of USB peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	7317	#define USB_BASE_ADDRS { USB0_BASE }
Pawel Zarembski	0:01f31e923fe2	7318	/** Array initializer of USB peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	7319	#define USB_BASE_PTRS { USB0 }
Pawel Zarembski	0:01f31e923fe2	7320	/** Interrupt vectors for the USB peripheral type */
Pawel Zarembski	0:01f31e923fe2	7321	#define USB_IRQS { USB0_IRQn }
Pawel Zarembski	0:01f31e923fe2	7322
Pawel Zarembski	0:01f31e923fe2	7323	/*!
Pawel Zarembski	0:01f31e923fe2	7324	* @}
Pawel Zarembski	0:01f31e923fe2	7325	/ / end of group USB_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	7326
Pawel Zarembski	0:01f31e923fe2	7327
Pawel Zarembski	0:01f31e923fe2	7328	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7329	-- USBDCD Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7330	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7331
Pawel Zarembski	0:01f31e923fe2	7332	/*!
Pawel Zarembski	0:01f31e923fe2	7333	* @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7334	* @{
Pawel Zarembski	0:01f31e923fe2	7335	*/
Pawel Zarembski	0:01f31e923fe2	7336
Pawel Zarembski	0:01f31e923fe2	7337	/** USBDCD - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	7338	typedef struct {
Pawel Zarembski	0:01f31e923fe2	7339	__IO uint32_t CONTROL; /*< Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	7340	__IO uint32_t CLOCK; /*< Clock Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	7341	__I uint32_t STATUS; /*< Status Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	7342	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	7343	__IO uint32_t TIMER0; /*< TIMER0 Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	7344	__IO uint32_t TIMER1; /*< , offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	7345	__IO uint32_t TIMER2; /*< , offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	7346	} USBDCD_Type;
Pawel Zarembski	0:01f31e923fe2	7347
Pawel Zarembski	0:01f31e923fe2	7348	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7349	-- USBDCD Register Masks
Pawel Zarembski	0:01f31e923fe2	7350	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7351
Pawel Zarembski	0:01f31e923fe2	7352	/*!
Pawel Zarembski	0:01f31e923fe2	7353	* @addtogroup USBDCD_Register_Masks USBDCD Register Masks
Pawel Zarembski	0:01f31e923fe2	7354	* @{
Pawel Zarembski	0:01f31e923fe2	7355	*/
Pawel Zarembski	0:01f31e923fe2	7356
Pawel Zarembski	0:01f31e923fe2	7357	/! @name CONTROL - Control Register /
Pawel Zarembski	0:01f31e923fe2	7358	#define USBDCD_CONTROL_IACK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7359	#define USBDCD_CONTROL_IACK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7360	#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
Pawel Zarembski	0:01f31e923fe2	7361	#define USBDCD_CONTROL_IF_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	7362	#define USBDCD_CONTROL_IF_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	7363	#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
Pawel Zarembski	0:01f31e923fe2	7364	#define USBDCD_CONTROL_IE_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	7365	#define USBDCD_CONTROL_IE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	7366	#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
Pawel Zarembski	0:01f31e923fe2	7367	#define USBDCD_CONTROL_START_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	7368	#define USBDCD_CONTROL_START_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	7369	#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
Pawel Zarembski	0:01f31e923fe2	7370	#define USBDCD_CONTROL_SR_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	7371	#define USBDCD_CONTROL_SR_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	7372	#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
Pawel Zarembski	0:01f31e923fe2	7373
Pawel Zarembski	0:01f31e923fe2	7374	/! @name CLOCK - Clock Register /
Pawel Zarembski	0:01f31e923fe2	7375	#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7376	#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7377	#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
Pawel Zarembski	0:01f31e923fe2	7378	#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
Pawel Zarembski	0:01f31e923fe2	7379	#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7380	#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
Pawel Zarembski	0:01f31e923fe2	7381
Pawel Zarembski	0:01f31e923fe2	7382	/! @name STATUS - Status Register /
Pawel Zarembski	0:01f31e923fe2	7383	#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
Pawel Zarembski	0:01f31e923fe2	7384	#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	7385	#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
Pawel Zarembski	0:01f31e923fe2	7386	#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	7387	#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	7388	#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
Pawel Zarembski	0:01f31e923fe2	7389	#define USBDCD_STATUS_ERR_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	7390	#define USBDCD_STATUS_ERR_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	7391	#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
Pawel Zarembski	0:01f31e923fe2	7392	#define USBDCD_STATUS_TO_MASK (0x200000U)
Pawel Zarembski	0:01f31e923fe2	7393	#define USBDCD_STATUS_TO_SHIFT (21U)
Pawel Zarembski	0:01f31e923fe2	7394	#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
Pawel Zarembski	0:01f31e923fe2	7395	#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	7396	#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	7397	#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
Pawel Zarembski	0:01f31e923fe2	7398
Pawel Zarembski	0:01f31e923fe2	7399	/! @name TIMER0 - TIMER0 Register /
Pawel Zarembski	0:01f31e923fe2	7400	#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
Pawel Zarembski	0:01f31e923fe2	7401	#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7402	#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
Pawel Zarembski	0:01f31e923fe2	7403	#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
Pawel Zarembski	0:01f31e923fe2	7404	#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	7405	#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
Pawel Zarembski	0:01f31e923fe2	7406
Pawel Zarembski	0:01f31e923fe2	7407	/! @name TIMER1 - /
Pawel Zarembski	0:01f31e923fe2	7408	#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	7409	#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7410	#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
Pawel Zarembski	0:01f31e923fe2	7411	#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
Pawel Zarembski	0:01f31e923fe2	7412	#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	7413	#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
Pawel Zarembski	0:01f31e923fe2	7414
Pawel Zarembski	0:01f31e923fe2	7415	/! @name TIMER2 - /
Pawel Zarembski	0:01f31e923fe2	7416	#define USBDCD_TIMER2_CHECK_DM_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	7417	#define USBDCD_TIMER2_CHECK_DM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7418	#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK)
Pawel Zarembski	0:01f31e923fe2	7419	#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U)
Pawel Zarembski	0:01f31e923fe2	7420	#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	7421	#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK)
Pawel Zarembski	0:01f31e923fe2	7422
Pawel Zarembski	0:01f31e923fe2	7423
Pawel Zarembski	0:01f31e923fe2	7424	/*!
Pawel Zarembski	0:01f31e923fe2	7425	* @}
Pawel Zarembski	0:01f31e923fe2	7426	/ / end of group USBDCD_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	7427
Pawel Zarembski	0:01f31e923fe2	7428
Pawel Zarembski	0:01f31e923fe2	7429	/* USBDCD - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	7430	/** Peripheral USBDCD base address */
Pawel Zarembski	0:01f31e923fe2	7431	#define USBDCD_BASE (0x40035000u)
Pawel Zarembski	0:01f31e923fe2	7432	/** Peripheral USBDCD base pointer */
Pawel Zarembski	0:01f31e923fe2	7433	#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
Pawel Zarembski	0:01f31e923fe2	7434	/** Array initializer of USBDCD peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	7435	#define USBDCD_BASE_ADDRS { USBDCD_BASE }
Pawel Zarembski	0:01f31e923fe2	7436	/** Array initializer of USBDCD peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	7437	#define USBDCD_BASE_PTRS { USBDCD }
Pawel Zarembski	0:01f31e923fe2	7438	/** Interrupt vectors for the USBDCD peripheral type */
Pawel Zarembski	0:01f31e923fe2	7439	#define USBDCD_IRQS { USBDCD_IRQn }
Pawel Zarembski	0:01f31e923fe2	7440
Pawel Zarembski	0:01f31e923fe2	7441	/*!
Pawel Zarembski	0:01f31e923fe2	7442	* @}
Pawel Zarembski	0:01f31e923fe2	7443	/ / end of group USBDCD_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	7444
Pawel Zarembski	0:01f31e923fe2	7445
Pawel Zarembski	0:01f31e923fe2	7446	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7447	-- VREF Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7448	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7449
Pawel Zarembski	0:01f31e923fe2	7450	/*!
Pawel Zarembski	0:01f31e923fe2	7451	* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7452	* @{
Pawel Zarembski	0:01f31e923fe2	7453	*/
Pawel Zarembski	0:01f31e923fe2	7454
Pawel Zarembski	0:01f31e923fe2	7455	/** VREF - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	7456	typedef struct {
Pawel Zarembski	0:01f31e923fe2	7457	__IO uint8_t TRM; /*< VREF Trim Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	7458	__IO uint8_t SC; /*< VREF Status and Control Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	7459	} VREF_Type;
Pawel Zarembski	0:01f31e923fe2	7460
Pawel Zarembski	0:01f31e923fe2	7461	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7462	-- VREF Register Masks
Pawel Zarembski	0:01f31e923fe2	7463	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7464
Pawel Zarembski	0:01f31e923fe2	7465	/*!
Pawel Zarembski	0:01f31e923fe2	7466	* @addtogroup VREF_Register_Masks VREF Register Masks
Pawel Zarembski	0:01f31e923fe2	7467	* @{
Pawel Zarembski	0:01f31e923fe2	7468	*/
Pawel Zarembski	0:01f31e923fe2	7469
Pawel Zarembski	0:01f31e923fe2	7470	/! @name TRM - VREF Trim Register /
Pawel Zarembski	0:01f31e923fe2	7471	#define VREF_TRM_TRIM_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	7472	#define VREF_TRM_TRIM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7473	#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	7474	#define VREF_TRM_CHOPEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7475	#define VREF_TRM_CHOPEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7476	#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7477
Pawel Zarembski	0:01f31e923fe2	7478	/! @name SC - VREF Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	7479	#define VREF_SC_MODE_LV_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	7480	#define VREF_SC_MODE_LV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7481	#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
Pawel Zarembski	0:01f31e923fe2	7482	#define VREF_SC_VREFST_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7483	#define VREF_SC_VREFST_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7484	#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
Pawel Zarembski	0:01f31e923fe2	7485	#define VREF_SC_REGEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7486	#define VREF_SC_REGEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7487	#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7488	#define VREF_SC_VREFEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7489	#define VREF_SC_VREFEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7490	#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7491
Pawel Zarembski	0:01f31e923fe2	7492
Pawel Zarembski	0:01f31e923fe2	7493	/*!
Pawel Zarembski	0:01f31e923fe2	7494	* @}
Pawel Zarembski	0:01f31e923fe2	7495	/ / end of group VREF_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	7496
Pawel Zarembski	0:01f31e923fe2	7497
Pawel Zarembski	0:01f31e923fe2	7498	/* VREF - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	7499	/** Peripheral VREF base address */
Pawel Zarembski	0:01f31e923fe2	7500	#define VREF_BASE (0x40074000u)
Pawel Zarembski	0:01f31e923fe2	7501	/** Peripheral VREF base pointer */
Pawel Zarembski	0:01f31e923fe2	7502	#define VREF ((VREF_Type *)VREF_BASE)
Pawel Zarembski	0:01f31e923fe2	7503	/** Array initializer of VREF peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	7504	#define VREF_BASE_ADDRS { VREF_BASE }
Pawel Zarembski	0:01f31e923fe2	7505	/** Array initializer of VREF peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	7506	#define VREF_BASE_PTRS { VREF }
Pawel Zarembski	0:01f31e923fe2	7507
Pawel Zarembski	0:01f31e923fe2	7508	/*!
Pawel Zarembski	0:01f31e923fe2	7509	* @}
Pawel Zarembski	0:01f31e923fe2	7510	/ / end of group VREF_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	7511
Pawel Zarembski	0:01f31e923fe2	7512
Pawel Zarembski	0:01f31e923fe2	7513	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7514	-- WDOG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7515	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7516
Pawel Zarembski	0:01f31e923fe2	7517	/*!
Pawel Zarembski	0:01f31e923fe2	7518	* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	7519	* @{
Pawel Zarembski	0:01f31e923fe2	7520	*/
Pawel Zarembski	0:01f31e923fe2	7521
Pawel Zarembski	0:01f31e923fe2	7522	/** WDOG - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	7523	typedef struct {
Pawel Zarembski	0:01f31e923fe2	7524	__IO uint16_t STCTRLH; /*< Watchdog Status and Control Register High, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	7525	__IO uint16_t STCTRLL; /*< Watchdog Status and Control Register Low, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	7526	__IO uint16_t TOVALH; /*< Watchdog Time-out Value Register High, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	7527	__IO uint16_t TOVALL; /*< Watchdog Time-out Value Register Low, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	7528	__IO uint16_t WINH; /*< Watchdog Window Register High, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	7529	__IO uint16_t WINL; /*< Watchdog Window Register Low, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	7530	__IO uint16_t REFRESH; /*< Watchdog Refresh Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	7531	__IO uint16_t UNLOCK; /*< Watchdog Unlock Register, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	7532	__IO uint16_t TMROUTH; /*< Watchdog Timer Output Register High, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	7533	__IO uint16_t TMROUTL; /*< Watchdog Timer Output Register Low, offset: 0x12 /
Pawel Zarembski	0:01f31e923fe2	7534	__IO uint16_t RSTCNT; /*< Watchdog Reset Count Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	7535	__IO uint16_t PRESC; /*< Watchdog Prescaler Register, offset: 0x16 /
Pawel Zarembski	0:01f31e923fe2	7536	} WDOG_Type;
Pawel Zarembski	0:01f31e923fe2	7537
Pawel Zarembski	0:01f31e923fe2	7538	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7539	-- WDOG Register Masks
Pawel Zarembski	0:01f31e923fe2	7540	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7541
Pawel Zarembski	0:01f31e923fe2	7542	/*!
Pawel Zarembski	0:01f31e923fe2	7543	* @addtogroup WDOG_Register_Masks WDOG Register Masks
Pawel Zarembski	0:01f31e923fe2	7544	* @{
Pawel Zarembski	0:01f31e923fe2	7545	*/
Pawel Zarembski	0:01f31e923fe2	7546
Pawel Zarembski	0:01f31e923fe2	7547	/! @name STCTRLH - Watchdog Status and Control Register High /
Pawel Zarembski	0:01f31e923fe2	7548	#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	7549	#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7550	#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7551	#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	7552	#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	7553	#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	7554	#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	7555	#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	7556	#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7557	#define WDOG_STCTRLH_WINEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	7558	#define WDOG_STCTRLH_WINEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	7559	#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7560	#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	7561	#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	7562	#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
Pawel Zarembski	0:01f31e923fe2	7563	#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	7564	#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	7565	#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7566	#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	7567	#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	7568	#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7569	#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	7570	#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	7571	#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
Pawel Zarembski	0:01f31e923fe2	7572	#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	7573	#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	7574	#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
Pawel Zarembski	0:01f31e923fe2	7575	#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	7576	#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	7577	#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	7578	#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
Pawel Zarembski	0:01f31e923fe2	7579	#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	7580	#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
Pawel Zarembski	0:01f31e923fe2	7581	#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	7582	#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	7583	#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
Pawel Zarembski	0:01f31e923fe2	7584
Pawel Zarembski	0:01f31e923fe2	7585	/! @name STCTRLL - Watchdog Status and Control Register Low /
Pawel Zarembski	0:01f31e923fe2	7586	#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	7587	#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	7588	#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
Pawel Zarembski	0:01f31e923fe2	7589
Pawel Zarembski	0:01f31e923fe2	7590	/! @name TOVALH - Watchdog Time-out Value Register High /
Pawel Zarembski	0:01f31e923fe2	7591	#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7592	#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7593	#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	7594
Pawel Zarembski	0:01f31e923fe2	7595	/! @name TOVALL - Watchdog Time-out Value Register Low /
Pawel Zarembski	0:01f31e923fe2	7596	#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7597	#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7598	#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	7599
Pawel Zarembski	0:01f31e923fe2	7600	/! @name WINH - Watchdog Window Register High /
Pawel Zarembski	0:01f31e923fe2	7601	#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7602	#define WDOG_WINH_WINHIGH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7603	#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	7604
Pawel Zarembski	0:01f31e923fe2	7605	/! @name WINL - Watchdog Window Register Low /
Pawel Zarembski	0:01f31e923fe2	7606	#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7607	#define WDOG_WINL_WINLOW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7608	#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	7609
Pawel Zarembski	0:01f31e923fe2	7610	/! @name REFRESH - Watchdog Refresh Register /
Pawel Zarembski	0:01f31e923fe2	7611	#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7612	#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7613	#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
Pawel Zarembski	0:01f31e923fe2	7614
Pawel Zarembski	0:01f31e923fe2	7615	/! @name UNLOCK - Watchdog Unlock Register /
Pawel Zarembski	0:01f31e923fe2	7616	#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7617	#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7618	#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
Pawel Zarembski	0:01f31e923fe2	7619
Pawel Zarembski	0:01f31e923fe2	7620	/! @name TMROUTH - Watchdog Timer Output Register High /
Pawel Zarembski	0:01f31e923fe2	7621	#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7622	#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7623	#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	7624
Pawel Zarembski	0:01f31e923fe2	7625	/! @name TMROUTL - Watchdog Timer Output Register Low /
Pawel Zarembski	0:01f31e923fe2	7626	#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7627	#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7628	#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	7629
Pawel Zarembski	0:01f31e923fe2	7630	/! @name RSTCNT - Watchdog Reset Count Register /
Pawel Zarembski	0:01f31e923fe2	7631	#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	7632	#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	7633	#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
Pawel Zarembski	0:01f31e923fe2	7634
Pawel Zarembski	0:01f31e923fe2	7635	/! @name PRESC - Watchdog Prescaler Register /
Pawel Zarembski	0:01f31e923fe2	7636	#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
Pawel Zarembski	0:01f31e923fe2	7637	#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	7638	#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
Pawel Zarembski	0:01f31e923fe2	7639
Pawel Zarembski	0:01f31e923fe2	7640
Pawel Zarembski	0:01f31e923fe2	7641	/*!
Pawel Zarembski	0:01f31e923fe2	7642	* @}
Pawel Zarembski	0:01f31e923fe2	7643	/ / end of group WDOG_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	7644
Pawel Zarembski	0:01f31e923fe2	7645
Pawel Zarembski	0:01f31e923fe2	7646	/* WDOG - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	7647	/** Peripheral WDOG base address */
Pawel Zarembski	0:01f31e923fe2	7648	#define WDOG_BASE (0x40052000u)
Pawel Zarembski	0:01f31e923fe2	7649	/** Peripheral WDOG base pointer */
Pawel Zarembski	0:01f31e923fe2	7650	#define WDOG ((WDOG_Type *)WDOG_BASE)
Pawel Zarembski	0:01f31e923fe2	7651	/** Array initializer of WDOG peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	7652	#define WDOG_BASE_ADDRS { WDOG_BASE }
Pawel Zarembski	0:01f31e923fe2	7653	/** Array initializer of WDOG peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	7654	#define WDOG_BASE_PTRS { WDOG }
Pawel Zarembski	0:01f31e923fe2	7655	/** Interrupt vectors for the WDOG peripheral type */
Pawel Zarembski	0:01f31e923fe2	7656	#define WDOG_IRQS { Watchdog_IRQn }
Pawel Zarembski	0:01f31e923fe2	7657
Pawel Zarembski	0:01f31e923fe2	7658	/*!
Pawel Zarembski	0:01f31e923fe2	7659	* @}
Pawel Zarembski	0:01f31e923fe2	7660	/ / end of group WDOG_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	7661
Pawel Zarembski	0:01f31e923fe2	7662
Pawel Zarembski	0:01f31e923fe2	7663	/*
Pawel Zarembski	0:01f31e923fe2	7664	** End of section using anonymous unions
Pawel Zarembski	0:01f31e923fe2	7665	*/
Pawel Zarembski	0:01f31e923fe2	7666
Pawel Zarembski	0:01f31e923fe2	7667	#if defined(__ARMCC_VERSION)
Pawel Zarembski	0:01f31e923fe2	7668	#pragma pop
Pawel Zarembski	0:01f31e923fe2	7669	#elif defined(__CWCC__)
Pawel Zarembski	0:01f31e923fe2	7670	#pragma pop
Pawel Zarembski	0:01f31e923fe2	7671	#elif defined(__GNUC__)
Pawel Zarembski	0:01f31e923fe2	7672	/* leave anonymous unions enabled */
Pawel Zarembski	0:01f31e923fe2	7673	#elif defined(__IAR_SYSTEMS_ICC__)
Pawel Zarembski	0:01f31e923fe2	7674	#pragma language=default
Pawel Zarembski	0:01f31e923fe2	7675	#else
Pawel Zarembski	0:01f31e923fe2	7676	#error Not supported compiler type
Pawel Zarembski	0:01f31e923fe2	7677	#endif
Pawel Zarembski	0:01f31e923fe2	7678
Pawel Zarembski	0:01f31e923fe2	7679	/*!
Pawel Zarembski	0:01f31e923fe2	7680	* @}
Pawel Zarembski	0:01f31e923fe2	7681	/ / end of group Peripheral_access_layer */
Pawel Zarembski	0:01f31e923fe2	7682
Pawel Zarembski	0:01f31e923fe2	7683
Pawel Zarembski	0:01f31e923fe2	7684	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	7685	-- SDK Compatibility
Pawel Zarembski	0:01f31e923fe2	7686	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	7687
Pawel Zarembski	0:01f31e923fe2	7688	/*!
Pawel Zarembski	0:01f31e923fe2	7689	* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
Pawel Zarembski	0:01f31e923fe2	7690	* @{
Pawel Zarembski	0:01f31e923fe2	7691	*/
Pawel Zarembski	0:01f31e923fe2	7692
Pawel Zarembski	0:01f31e923fe2	7693	#define PDB_CHC1_REG(base,index) PDB_C1_REG(base,index)
Pawel Zarembski	0:01f31e923fe2	7694	#define PDB_CHDLY0_REG(base,index) PDB_DLY_REG(base,index,0)
Pawel Zarembski	0:01f31e923fe2	7695	#define PDB_CHDLY1_REG(base,index) PDB_DLY_REG(base,index,1)
Pawel Zarembski	0:01f31e923fe2	7696	#define PDB_CHC1_EN_MASK PDB_C1_EN_MASK
Pawel Zarembski	0:01f31e923fe2	7697	#define PDB_CHC1_EN_SHIFT PDB_C1_EN_SHIFT
Pawel Zarembski	0:01f31e923fe2	7698	#define PDB_CHC1_EN(x) PDB_C1_EN(x)
Pawel Zarembski	0:01f31e923fe2	7699	#define PDB_CHC1_TOS_MASK PDB_C1_TOS_MASK
Pawel Zarembski	0:01f31e923fe2	7700	#define PDB_CHC1_TOS_SHIFT PDB_C1_TOS_SHIFT
Pawel Zarembski	0:01f31e923fe2	7701	#define PDB_CHC1_TOS(x) PDB_C1_TOS(x)
Pawel Zarembski	0:01f31e923fe2	7702	#define PDB_CHC1_BB_MASK PDB_C1_BB_MASK
Pawel Zarembski	0:01f31e923fe2	7703	#define PDB_CHC1_BB_SHIFT PDB_C1_BB_SHIFT
Pawel Zarembski	0:01f31e923fe2	7704	#define PDB_CHC1_BB(x) PDB_C1_BB(x)
Pawel Zarembski	0:01f31e923fe2	7705	#define PDB_CHDLY0_DLY_MASK PDB_DLY_DLY_MASK
Pawel Zarembski	0:01f31e923fe2	7706	#define PDB_CHDLY0_DLY_SHIFT PDB_DLY_DLY_SHIFT
Pawel Zarembski	0:01f31e923fe2	7707	#define PDB_CHDLY0_DLY(x) PDB_DLY_DLY(x)
Pawel Zarembski	0:01f31e923fe2	7708	#define PDB_CHDLY1_DLY_MASK PDB_DLY_DLY_MASK
Pawel Zarembski	0:01f31e923fe2	7709	#define PDB_CHDLY1_DLY_SHIFT PDB_DLY_DLY_SHIFT
Pawel Zarembski	0:01f31e923fe2	7710	#define PDB_CHDLY1_DLY(x) PDB_DLY_DLY(x)
Pawel Zarembski	0:01f31e923fe2	7711	#define PDB0_CHC1(index) PDB0_C1(index)
Pawel Zarembski	0:01f31e923fe2	7712	#define PDB0_CHDLY0(index) PDB0_DLY(index,0)
Pawel Zarembski	0:01f31e923fe2	7713	#define PDB0_CHDLY1(index) PDB0_DLY(index,1)
Pawel Zarembski	0:01f31e923fe2	7714	#define GPIOA_BASE PTA_BASE
Pawel Zarembski	0:01f31e923fe2	7715	#define GPIOA PTA
Pawel Zarembski	0:01f31e923fe2	7716	#define GPIOB_BASE PTB_BASE
Pawel Zarembski	0:01f31e923fe2	7717	#define GPIOB PTB
Pawel Zarembski	0:01f31e923fe2	7718	#define GPIOC_BASE PTC_BASE
Pawel Zarembski	0:01f31e923fe2	7719	#define GPIOC PTC
Pawel Zarembski	0:01f31e923fe2	7720	#define GPIOD_BASE PTD_BASE
Pawel Zarembski	0:01f31e923fe2	7721	#define GPIOD PTD
Pawel Zarembski	0:01f31e923fe2	7722	#define GPIOE_BASE PTE_BASE
Pawel Zarembski	0:01f31e923fe2	7723	#define GPIOE PTE
Pawel Zarembski	0:01f31e923fe2	7724	#define DMAMUX0 DMAMUX
Pawel Zarembski	0:01f31e923fe2	7725
Pawel Zarembski	0:01f31e923fe2	7726	/*!
Pawel Zarembski	0:01f31e923fe2	7727	* @}
Pawel Zarembski	0:01f31e923fe2	7728	/ / end of group SDK_Compatibility_Symbols */
Pawel Zarembski	0:01f31e923fe2	7729
Pawel Zarembski	0:01f31e923fe2	7730
Pawel Zarembski	0:01f31e923fe2	7731	#endif /* _MK20D5_H_ */
Pawel Zarembski	0:01f31e923fe2	7732

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Type:	Library
Created:	07 Apr 2020
Imports:	6
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	12

source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h@0:01f31e923fe2, 2020-04-07 (annotated)

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