Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k20dx/IO_Config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file IO_Config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "MK20D5.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "compiler.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 // This GPIO configuration is only valid for the K20DX HIC
Pawel Zarembski 0:01f31e923fe2 30 COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K20DX);
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 // Debug Port I/O Pins
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 // SWCLK Pin PTC5
Pawel Zarembski 0:01f31e923fe2 36 #define PIN_SWCLK_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 37 #define PIN_SWCLK_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 38 #define PIN_SWCLK_BIT 5
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 // SWDIO Out Pin PTC6
Pawel Zarembski 0:01f31e923fe2 41 #define PIN_SWDIO_OUT_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 42 #define PIN_SWDIO_OUT_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 43 #define PIN_SWDIO_OUT_BIT 6
Pawel Zarembski 0:01f31e923fe2 44
Pawel Zarembski 0:01f31e923fe2 45 // SWDIO In Pin PTC7
Pawel Zarembski 0:01f31e923fe2 46 #define PIN_SWDIO_IN_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 47 #define PIN_SWDIO_IN_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 48 #define PIN_SWDIO_IN_BIT 7
Pawel Zarembski 0:01f31e923fe2 49
Pawel Zarembski 0:01f31e923fe2 50 // SWDIO Neg. Output Enable Pin PTB0
Pawel Zarembski 0:01f31e923fe2 51 #define PIN_SWDIO_NOE_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 52 #define PIN_SWDIO_NOE_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 53 #define PIN_SWDIO_NOE_BIT 0
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 // SWD Neg. Enable Pin PTA4
Pawel Zarembski 0:01f31e923fe2 56 #define PIN_SWD_NOE_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 57 #define PIN_SWD_NOE_GPIO PTA
Pawel Zarembski 0:01f31e923fe2 58 #define PIN_SWD_NOE_BIT 4
Pawel Zarembski 0:01f31e923fe2 59
Pawel Zarembski 0:01f31e923fe2 60 // nRESET Pin PTB1
Pawel Zarembski 0:01f31e923fe2 61 #define PIN_nRESET_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 62 #define PIN_nRESET_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 63 #define PIN_nRESET_BIT 1
Pawel Zarembski 0:01f31e923fe2 64 #define PIN_nRESET (1 << PIN_nRESET_BIT)
Pawel Zarembski 0:01f31e923fe2 65
Pawel Zarembski 0:01f31e923fe2 66 // Power and fault detection
Pawel Zarembski 0:01f31e923fe2 67
Pawel Zarembski 0:01f31e923fe2 68 // PWR_REG_EN PTD2 PTD6
Pawel Zarembski 0:01f31e923fe2 69 #define PIN_POWER_EN_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 70 #define PIN_POWER_EN_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 71 #define PIN_POWER_EN_BIT (6)
Pawel Zarembski 0:01f31e923fe2 72 #define PIN_POWER_EN (1<<PIN_POWER_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 // VTRG_FAULT_B PTD7
Pawel Zarembski 0:01f31e923fe2 75 #define PIN_VTRG_FAULT_B_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 76 #define PIN_VTRG_FAULT_B_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 77 #define PIN_VTRG_FAULT_B_BIT (7)
Pawel Zarembski 0:01f31e923fe2 78
Pawel Zarembski 0:01f31e923fe2 79 // Debug Unit LEDs
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 // Connected LED PTD4
Pawel Zarembski 0:01f31e923fe2 82 #define LED_CONNECTED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 83 #define LED_CONNECTED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 84 #define LED_CONNECTED_BIT 4
Pawel Zarembski 0:01f31e923fe2 85
Pawel Zarembski 0:01f31e923fe2 86 // Target Running LED Not available
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88 // Debug Unit LEDs
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 // HID_LED PTD4
Pawel Zarembski 0:01f31e923fe2 91 #define PIN_HID_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 92 #define PIN_HID_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 93 #define PIN_HID_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 94 #define PIN_HID_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 // MSC_LED PTD4
Pawel Zarembski 0:01f31e923fe2 97 #define PIN_MSC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 98 #define PIN_MSC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 99 #define PIN_MSC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 100 #define PIN_MSC_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 101
Pawel Zarembski 0:01f31e923fe2 102 // CDC_LED PTD4
Pawel Zarembski 0:01f31e923fe2 103 #define PIN_CDC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 104 #define PIN_CDC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 105 #define PIN_CDC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 106 #define PIN_CDC_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 107
Pawel Zarembski 0:01f31e923fe2 108 // SW RESET BUTTON PTB1
Pawel Zarembski 0:01f31e923fe2 109 #define PIN_SW_RESET_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 110 #define PIN_SW_RESET_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 111 #define PIN_SW_RESET_BIT (1)
Pawel Zarembski 0:01f31e923fe2 112 #define PIN_SW_RESET (1<<PIN_SW_RESET_BIT)
Pawel Zarembski 0:01f31e923fe2 113
Pawel Zarembski 0:01f31e923fe2 114 #endif