Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/pio/sam3u2c.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 29 | |
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0:01f31e923fe2 | 30 | #ifndef _SAM3U2C_PIO_ |
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0:01f31e923fe2 | 31 | #define _SAM3U2C_PIO_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | #define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ |
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0:01f31e923fe2 | 34 | #define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ |
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0:01f31e923fe2 | 35 | #define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ |
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0:01f31e923fe2 | 36 | #define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ |
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0:01f31e923fe2 | 37 | #define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ |
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0:01f31e923fe2 | 38 | #define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ |
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0:01f31e923fe2 | 39 | #define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ |
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0:01f31e923fe2 | 40 | #define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ |
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0:01f31e923fe2 | 41 | #define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ |
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0:01f31e923fe2 | 42 | #define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ |
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0:01f31e923fe2 | 43 | #define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ |
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0:01f31e923fe2 | 44 | #define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ |
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0:01f31e923fe2 | 45 | #define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ |
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0:01f31e923fe2 | 46 | #define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ |
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0:01f31e923fe2 | 47 | #define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ |
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0:01f31e923fe2 | 48 | #define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ |
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0:01f31e923fe2 | 49 | #define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ |
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0:01f31e923fe2 | 50 | #define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ |
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0:01f31e923fe2 | 51 | #define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ |
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0:01f31e923fe2 | 52 | #define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ |
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0:01f31e923fe2 | 53 | #define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ |
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0:01f31e923fe2 | 54 | #define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ |
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0:01f31e923fe2 | 55 | #define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ |
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0:01f31e923fe2 | 56 | #define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ |
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0:01f31e923fe2 | 57 | #define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ |
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0:01f31e923fe2 | 58 | #define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ |
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0:01f31e923fe2 | 59 | #define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ |
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0:01f31e923fe2 | 60 | #define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ |
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0:01f31e923fe2 | 61 | #define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ |
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0:01f31e923fe2 | 62 | #define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ |
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0:01f31e923fe2 | 63 | #define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ |
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0:01f31e923fe2 | 64 | #define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ |
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0:01f31e923fe2 | 65 | #define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ |
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0:01f31e923fe2 | 66 | #define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ |
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0:01f31e923fe2 | 67 | #define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ |
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0:01f31e923fe2 | 68 | #define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ |
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0:01f31e923fe2 | 69 | #define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ |
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0:01f31e923fe2 | 70 | #define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ |
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0:01f31e923fe2 | 71 | #define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ |
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0:01f31e923fe2 | 72 | #define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ |
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0:01f31e923fe2 | 73 | #define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ |
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0:01f31e923fe2 | 74 | #define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ |
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0:01f31e923fe2 | 75 | #define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ |
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0:01f31e923fe2 | 76 | #define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ |
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0:01f31e923fe2 | 77 | #define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ |
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0:01f31e923fe2 | 78 | #define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ |
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0:01f31e923fe2 | 79 | #define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ |
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0:01f31e923fe2 | 80 | #define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ |
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0:01f31e923fe2 | 81 | #define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ |
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0:01f31e923fe2 | 82 | #define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ |
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0:01f31e923fe2 | 83 | #define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ |
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0:01f31e923fe2 | 84 | #define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ |
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0:01f31e923fe2 | 85 | #define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ |
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0:01f31e923fe2 | 86 | #define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ |
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0:01f31e923fe2 | 87 | #define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ |
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0:01f31e923fe2 | 88 | #define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ |
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0:01f31e923fe2 | 89 | #define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ |
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0:01f31e923fe2 | 90 | /* ========== Pio definition for ADC peripheral ========== */ |
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0:01f31e923fe2 | 91 | #define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */ |
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0:01f31e923fe2 | 92 | #define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */ |
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0:01f31e923fe2 | 93 | #define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */ |
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0:01f31e923fe2 | 94 | #define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */ |
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0:01f31e923fe2 | 95 | #define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */ |
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0:01f31e923fe2 | 96 | #define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */ |
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0:01f31e923fe2 | 97 | #define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */ |
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0:01f31e923fe2 | 98 | #define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */ |
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0:01f31e923fe2 | 99 | #define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */ |
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0:01f31e923fe2 | 100 | /* ========== Pio definition for ADC12B peripheral ========== */ |
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0:01f31e923fe2 | 101 | #define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */ |
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0:01f31e923fe2 | 102 | #define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */ |
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0:01f31e923fe2 | 103 | #define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */ |
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0:01f31e923fe2 | 104 | #define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */ |
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0:01f31e923fe2 | 105 | #define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */ |
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0:01f31e923fe2 | 106 | #define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */ |
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0:01f31e923fe2 | 107 | #define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */ |
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0:01f31e923fe2 | 108 | #define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */ |
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0:01f31e923fe2 | 109 | #define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */ |
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0:01f31e923fe2 | 110 | /* ========== Pio definition for EBI peripheral ========== */ |
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0:01f31e923fe2 | 111 | #define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */ |
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0:01f31e923fe2 | 112 | #define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */ |
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0:01f31e923fe2 | 113 | #define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */ |
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0:01f31e923fe2 | 114 | #define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */ |
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0:01f31e923fe2 | 115 | #define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */ |
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0:01f31e923fe2 | 116 | #define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */ |
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0:01f31e923fe2 | 117 | #define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */ |
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0:01f31e923fe2 | 118 | #define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */ |
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0:01f31e923fe2 | 119 | #define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */ |
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0:01f31e923fe2 | 120 | #define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */ |
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0:01f31e923fe2 | 121 | #define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */ |
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0:01f31e923fe2 | 122 | #define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */ |
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0:01f31e923fe2 | 123 | #define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */ |
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0:01f31e923fe2 | 124 | #define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */ |
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0:01f31e923fe2 | 125 | #define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */ |
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0:01f31e923fe2 | 126 | #define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */ |
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0:01f31e923fe2 | 127 | #define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */ |
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0:01f31e923fe2 | 128 | #define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ |
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0:01f31e923fe2 | 129 | #define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ |
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0:01f31e923fe2 | 130 | #define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ |
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0:01f31e923fe2 | 131 | #define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ |
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0:01f31e923fe2 | 132 | #define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */ |
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0:01f31e923fe2 | 133 | #define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */ |
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0:01f31e923fe2 | 134 | #define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */ |
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0:01f31e923fe2 | 135 | #define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */ |
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0:01f31e923fe2 | 136 | #define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */ |
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0:01f31e923fe2 | 137 | #define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */ |
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0:01f31e923fe2 | 138 | #define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */ |
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0:01f31e923fe2 | 139 | #define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */ |
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0:01f31e923fe2 | 140 | #define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */ |
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0:01f31e923fe2 | 141 | #define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */ |
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0:01f31e923fe2 | 142 | #define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */ |
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0:01f31e923fe2 | 143 | #define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */ |
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0:01f31e923fe2 | 144 | #define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */ |
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0:01f31e923fe2 | 145 | #define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */ |
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0:01f31e923fe2 | 146 | #define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */ |
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0:01f31e923fe2 | 147 | #define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */ |
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0:01f31e923fe2 | 148 | #define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */ |
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0:01f31e923fe2 | 149 | #define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */ |
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0:01f31e923fe2 | 150 | #define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */ |
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0:01f31e923fe2 | 151 | #define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */ |
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0:01f31e923fe2 | 152 | #define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */ |
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0:01f31e923fe2 | 153 | #define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */ |
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0:01f31e923fe2 | 154 | #define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */ |
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0:01f31e923fe2 | 155 | #define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */ |
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0:01f31e923fe2 | 156 | #define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */ |
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0:01f31e923fe2 | 157 | #define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */ |
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0:01f31e923fe2 | 158 | #define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */ |
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0:01f31e923fe2 | 159 | #define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */ |
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0:01f31e923fe2 | 160 | #define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */ |
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0:01f31e923fe2 | 161 | #define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */ |
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0:01f31e923fe2 | 162 | #define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */ |
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0:01f31e923fe2 | 163 | #define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */ |
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0:01f31e923fe2 | 164 | #define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */ |
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0:01f31e923fe2 | 165 | #define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */ |
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0:01f31e923fe2 | 166 | #define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */ |
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0:01f31e923fe2 | 167 | #define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */ |
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0:01f31e923fe2 | 168 | #define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */ |
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0:01f31e923fe2 | 169 | #define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */ |
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0:01f31e923fe2 | 170 | #define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */ |
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0:01f31e923fe2 | 171 | #define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */ |
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0:01f31e923fe2 | 172 | #define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */ |
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0:01f31e923fe2 | 173 | #define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */ |
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0:01f31e923fe2 | 174 | #define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ |
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0:01f31e923fe2 | 175 | #define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ |
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0:01f31e923fe2 | 176 | /* ========== Pio definition for HSMCI peripheral ========== */ |
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0:01f31e923fe2 | 177 | #define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */ |
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0:01f31e923fe2 | 178 | #define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */ |
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0:01f31e923fe2 | 179 | #define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */ |
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0:01f31e923fe2 | 180 | #define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */ |
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0:01f31e923fe2 | 181 | #define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */ |
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0:01f31e923fe2 | 182 | #define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */ |
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0:01f31e923fe2 | 183 | #define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */ |
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0:01f31e923fe2 | 184 | #define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */ |
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0:01f31e923fe2 | 185 | #define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */ |
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0:01f31e923fe2 | 186 | #define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */ |
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0:01f31e923fe2 | 187 | /* ========== Pio definition for PMC peripheral ========== */ |
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0:01f31e923fe2 | 188 | #define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */ |
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0:01f31e923fe2 | 189 | #define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */ |
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0:01f31e923fe2 | 190 | #define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */ |
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0:01f31e923fe2 | 191 | #define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ |
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0:01f31e923fe2 | 192 | #define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */ |
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0:01f31e923fe2 | 193 | /* ========== Pio definition for PWM peripheral ========== */ |
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0:01f31e923fe2 | 194 | #define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */ |
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0:01f31e923fe2 | 195 | #define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */ |
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0:01f31e923fe2 | 196 | #define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */ |
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0:01f31e923fe2 | 197 | #define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */ |
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0:01f31e923fe2 | 198 | #define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */ |
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0:01f31e923fe2 | 199 | #define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ |
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0:01f31e923fe2 | 200 | #define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */ |
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0:01f31e923fe2 | 201 | #define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */ |
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0:01f31e923fe2 | 202 | #define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ |
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0:01f31e923fe2 | 203 | #define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */ |
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0:01f31e923fe2 | 204 | #define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ |
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0:01f31e923fe2 | 205 | #define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */ |
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0:01f31e923fe2 | 206 | #define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */ |
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0:01f31e923fe2 | 207 | #define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */ |
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0:01f31e923fe2 | 208 | #define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */ |
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0:01f31e923fe2 | 209 | #define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ |
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0:01f31e923fe2 | 210 | #define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */ |
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0:01f31e923fe2 | 211 | #define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */ |
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0:01f31e923fe2 | 212 | #define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */ |
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0:01f31e923fe2 | 213 | #define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ |
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0:01f31e923fe2 | 214 | #define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */ |
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0:01f31e923fe2 | 215 | #define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */ |
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0:01f31e923fe2 | 216 | #define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */ |
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0:01f31e923fe2 | 217 | #define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */ |
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0:01f31e923fe2 | 218 | #define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */ |
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0:01f31e923fe2 | 219 | #define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */ |
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0:01f31e923fe2 | 220 | #define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */ |
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0:01f31e923fe2 | 221 | #define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */ |
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0:01f31e923fe2 | 222 | #define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */ |
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0:01f31e923fe2 | 223 | #define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */ |
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0:01f31e923fe2 | 224 | #define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */ |
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0:01f31e923fe2 | 225 | #define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */ |
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0:01f31e923fe2 | 226 | #define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */ |
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0:01f31e923fe2 | 227 | #define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */ |
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0:01f31e923fe2 | 228 | #define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */ |
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0:01f31e923fe2 | 229 | #define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */ |
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0:01f31e923fe2 | 230 | #define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */ |
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0:01f31e923fe2 | 231 | #define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */ |
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0:01f31e923fe2 | 232 | #define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */ |
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0:01f31e923fe2 | 233 | #define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */ |
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0:01f31e923fe2 | 234 | #define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */ |
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0:01f31e923fe2 | 235 | #define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */ |
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0:01f31e923fe2 | 236 | /* ========== Pio definition for SPI peripheral ========== */ |
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0:01f31e923fe2 | 237 | #define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */ |
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0:01f31e923fe2 | 238 | #define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */ |
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0:01f31e923fe2 | 239 | #define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */ |
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0:01f31e923fe2 | 240 | #define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */ |
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0:01f31e923fe2 | 241 | #define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */ |
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0:01f31e923fe2 | 242 | #define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */ |
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0:01f31e923fe2 | 243 | #define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */ |
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0:01f31e923fe2 | 244 | #define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */ |
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0:01f31e923fe2 | 245 | #define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */ |
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0:01f31e923fe2 | 246 | #define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */ |
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0:01f31e923fe2 | 247 | #define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ |
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0:01f31e923fe2 | 248 | #define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */ |
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0:01f31e923fe2 | 249 | /* ========== Pio definition for SSC peripheral ========== */ |
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0:01f31e923fe2 | 250 | #define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */ |
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0:01f31e923fe2 | 251 | #define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */ |
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0:01f31e923fe2 | 252 | #define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */ |
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0:01f31e923fe2 | 253 | #define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */ |
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0:01f31e923fe2 | 254 | #define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */ |
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0:01f31e923fe2 | 255 | #define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */ |
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0:01f31e923fe2 | 256 | /* ========== Pio definition for TC0 peripheral ========== */ |
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0:01f31e923fe2 | 257 | #define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ |
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0:01f31e923fe2 | 258 | #define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ |
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0:01f31e923fe2 | 259 | #define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */ |
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0:01f31e923fe2 | 260 | #define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */ |
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0:01f31e923fe2 | 261 | #define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */ |
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0:01f31e923fe2 | 262 | #define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */ |
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0:01f31e923fe2 | 263 | #define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */ |
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0:01f31e923fe2 | 264 | #define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */ |
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0:01f31e923fe2 | 265 | #define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */ |
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0:01f31e923fe2 | 266 | /* ========== Pio definition for TWI0 peripheral ========== */ |
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0:01f31e923fe2 | 267 | #define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */ |
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0:01f31e923fe2 | 268 | #define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */ |
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0:01f31e923fe2 | 269 | /* ========== Pio definition for TWI1 peripheral ========== */ |
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0:01f31e923fe2 | 270 | #define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */ |
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0:01f31e923fe2 | 271 | #define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */ |
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0:01f31e923fe2 | 272 | /* ========== Pio definition for UART peripheral ========== */ |
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0:01f31e923fe2 | 273 | #define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */ |
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0:01f31e923fe2 | 274 | #define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */ |
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0:01f31e923fe2 | 275 | /* ========== Pio definition for USART0 peripheral ========== */ |
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0:01f31e923fe2 | 276 | #define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ |
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0:01f31e923fe2 | 277 | #define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */ |
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0:01f31e923fe2 | 278 | #define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */ |
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0:01f31e923fe2 | 279 | #define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */ |
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0:01f31e923fe2 | 280 | #define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */ |
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0:01f31e923fe2 | 281 | #define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ |
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0:01f31e923fe2 | 282 | #define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */ |
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0:01f31e923fe2 | 283 | #define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ |
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0:01f31e923fe2 | 284 | #define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */ |
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0:01f31e923fe2 | 285 | /* ========== Pio definition for USART1 peripheral ========== */ |
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0:01f31e923fe2 | 286 | #define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */ |
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0:01f31e923fe2 | 287 | #define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */ |
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0:01f31e923fe2 | 288 | #define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ |
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0:01f31e923fe2 | 289 | #define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */ |
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0:01f31e923fe2 | 290 | #define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */ |
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0:01f31e923fe2 | 291 | /* ========== Pio definition for USART2 peripheral ========== */ |
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0:01f31e923fe2 | 292 | #define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */ |
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0:01f31e923fe2 | 293 | #define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */ |
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0:01f31e923fe2 | 294 | #define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */ |
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0:01f31e923fe2 | 295 | #define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */ |
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0:01f31e923fe2 | 296 | #define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */ |
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0:01f31e923fe2 | 297 | /* ========== Pio indexes ========== */ |
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0:01f31e923fe2 | 298 | #define PIO_PA0_IDX 0 |
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0:01f31e923fe2 | 299 | #define PIO_PA1_IDX 1 |
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0:01f31e923fe2 | 300 | #define PIO_PA2_IDX 2 |
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0:01f31e923fe2 | 301 | #define PIO_PA3_IDX 3 |
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0:01f31e923fe2 | 302 | #define PIO_PA4_IDX 4 |
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0:01f31e923fe2 | 303 | #define PIO_PA5_IDX 5 |
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0:01f31e923fe2 | 304 | #define PIO_PA6_IDX 6 |
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0:01f31e923fe2 | 305 | #define PIO_PA7_IDX 7 |
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0:01f31e923fe2 | 306 | #define PIO_PA8_IDX 8 |
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0:01f31e923fe2 | 307 | #define PIO_PA9_IDX 9 |
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0:01f31e923fe2 | 308 | #define PIO_PA10_IDX 10 |
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0:01f31e923fe2 | 309 | #define PIO_PA11_IDX 11 |
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0:01f31e923fe2 | 310 | #define PIO_PA12_IDX 12 |
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0:01f31e923fe2 | 311 | #define PIO_PA13_IDX 13 |
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0:01f31e923fe2 | 312 | #define PIO_PA14_IDX 14 |
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0:01f31e923fe2 | 313 | #define PIO_PA15_IDX 15 |
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0:01f31e923fe2 | 314 | #define PIO_PA16_IDX 16 |
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0:01f31e923fe2 | 315 | #define PIO_PA17_IDX 17 |
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0:01f31e923fe2 | 316 | #define PIO_PA18_IDX 18 |
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0:01f31e923fe2 | 317 | #define PIO_PA19_IDX 19 |
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0:01f31e923fe2 | 318 | #define PIO_PA20_IDX 20 |
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0:01f31e923fe2 | 319 | #define PIO_PA21_IDX 21 |
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0:01f31e923fe2 | 320 | #define PIO_PA22_IDX 22 |
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0:01f31e923fe2 | 321 | #define PIO_PA23_IDX 23 |
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0:01f31e923fe2 | 322 | #define PIO_PA24_IDX 24 |
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0:01f31e923fe2 | 323 | #define PIO_PA25_IDX 25 |
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0:01f31e923fe2 | 324 | #define PIO_PA26_IDX 26 |
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0:01f31e923fe2 | 325 | #define PIO_PA27_IDX 27 |
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0:01f31e923fe2 | 326 | #define PIO_PA28_IDX 28 |
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0:01f31e923fe2 | 327 | #define PIO_PA29_IDX 29 |
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0:01f31e923fe2 | 328 | #define PIO_PA30_IDX 30 |
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0:01f31e923fe2 | 329 | #define PIO_PA31_IDX 31 |
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0:01f31e923fe2 | 330 | #define PIO_PB0_IDX 32 |
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0:01f31e923fe2 | 331 | #define PIO_PB1_IDX 33 |
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0:01f31e923fe2 | 332 | #define PIO_PB2_IDX 34 |
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0:01f31e923fe2 | 333 | #define PIO_PB3_IDX 35 |
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0:01f31e923fe2 | 334 | #define PIO_PB4_IDX 36 |
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0:01f31e923fe2 | 335 | #define PIO_PB5_IDX 37 |
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0:01f31e923fe2 | 336 | #define PIO_PB6_IDX 38 |
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0:01f31e923fe2 | 337 | #define PIO_PB7_IDX 39 |
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0:01f31e923fe2 | 338 | #define PIO_PB8_IDX 40 |
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0:01f31e923fe2 | 339 | #define PIO_PB9_IDX 41 |
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0:01f31e923fe2 | 340 | #define PIO_PB10_IDX 42 |
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0:01f31e923fe2 | 341 | #define PIO_PB11_IDX 43 |
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0:01f31e923fe2 | 342 | #define PIO_PB12_IDX 44 |
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0:01f31e923fe2 | 343 | #define PIO_PB13_IDX 45 |
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0:01f31e923fe2 | 344 | #define PIO_PB14_IDX 46 |
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0:01f31e923fe2 | 345 | #define PIO_PB15_IDX 47 |
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0:01f31e923fe2 | 346 | #define PIO_PB16_IDX 48 |
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0:01f31e923fe2 | 347 | #define PIO_PB17_IDX 49 |
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0:01f31e923fe2 | 348 | #define PIO_PB18_IDX 50 |
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0:01f31e923fe2 | 349 | #define PIO_PB19_IDX 51 |
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0:01f31e923fe2 | 350 | #define PIO_PB20_IDX 52 |
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0:01f31e923fe2 | 351 | #define PIO_PB21_IDX 53 |
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0:01f31e923fe2 | 352 | #define PIO_PB22_IDX 54 |
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0:01f31e923fe2 | 353 | #define PIO_PB23_IDX 55 |
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0:01f31e923fe2 | 354 | #define PIO_PB24_IDX 56 |
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0:01f31e923fe2 | 355 | |
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0:01f31e923fe2 | 356 | #endif /* _SAM3U2C_PIO_ */ |