Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/twi0.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_TWI0_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_TWI0_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for TWI0 peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_TWI0_CR (0x40084000U) /**< \brief (TWI0) Control Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_TWI0_MMR (0x40084004U) /**< \brief (TWI0) Master Mode Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_TWI0_SMR (0x40084008U) /**< \brief (TWI0) Slave Mode Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_TWI0_IADR (0x4008400CU) /**< \brief (TWI0) Internal Address Register */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_TWI0_CWGR (0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_TWI0_SR (0x40084020U) /**< \brief (TWI0) Status Register */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_TWI0_IER (0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_TWI0_IDR (0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_TWI0_IMR (0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_TWI0_RHR (0x40084030U) /**< \brief (TWI0) Receive Holding Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_TWI0_THR (0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_TWI0_RPR (0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_TWI0_RCR (0x40084104U) /**< \brief (TWI0) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_TWI0_TPR (0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_TWI0_TCR (0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_TWI0_RNPR (0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_TWI0_RNCR (0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_TWI0_TNPR (0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_TWI0_TNCR (0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_TWI0_PTCR (0x40084120U) /**< \brief (TWI0) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_TWI0_PTSR (0x40084124U) /**< \brief (TWI0) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 56 #else
Pawel Zarembski 0:01f31e923fe2 57 #define REG_TWI0_CR (*(WoReg*)0x40084000U) /**< \brief (TWI0) Control Register */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_TWI0_MMR (*(RwReg*)0x40084004U) /**< \brief (TWI0) Master Mode Register */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_TWI0_SMR (*(RwReg*)0x40084008U) /**< \brief (TWI0) Slave Mode Register */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_TWI0_IADR (*(RwReg*)0x4008400CU) /**< \brief (TWI0) Internal Address Register */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_TWI0_CWGR (*(RwReg*)0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_TWI0_SR (*(RoReg*)0x40084020U) /**< \brief (TWI0) Status Register */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_TWI0_IER (*(WoReg*)0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_TWI0_IDR (*(WoReg*)0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_TWI0_IMR (*(RoReg*)0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_TWI0_RHR (*(RoReg*)0x40084030U) /**< \brief (TWI0) Receive Holding Register */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_TWI0_THR (*(WoReg*)0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_TWI0_RPR (*(RwReg*)0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_TWI0_RCR (*(RwReg*)0x40084104U) /**< \brief (TWI0) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_TWI0_TPR (*(RwReg*)0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_TWI0_TCR (*(RwReg*)0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_TWI0_RNPR (*(RwReg*)0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_TWI0_RNCR (*(RwReg*)0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_TWI0_TNPR (*(RwReg*)0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_TWI0_PTCR (*(WoReg*)0x40084120U) /**< \brief (TWI0) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_TWI0_PTSR (*(RoReg*)0x40084124U) /**< \brief (TWI0) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 #endif /* _SAM3U_TWI0_INSTANCE_ */