Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/smc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_SMC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_SMC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for SMC peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_SMC_CFG (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_SMC_CTRL (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_SMC_SR (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_SMC_IER (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_SMC_IDR (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_SMC_IMR (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_SMC_ADDR (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_SMC_BANK (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_SMC_ECC_CTRL (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_SMC_ECC_MD (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_SMC_ECC_SR1 (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_SMC_ECC_PR0 (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_SMC_ECC_PR1 (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_SMC_ECC_SR2 (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_SMC_ECC_PR2 (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_SMC_ECC_PR3 (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_SMC_ECC_PR4 (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_SMC_ECC_PR5 (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_SMC_ECC_PR6 (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_SMC_ECC_PR7 (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_SMC_ECC_PR8 (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
Pawel Zarembski 0:01f31e923fe2 56 #define REG_SMC_ECC_PR9 (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
Pawel Zarembski 0:01f31e923fe2 57 #define REG_SMC_ECC_PR10 (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_SMC_ECC_PR11 (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_SMC_ECC_PR12 (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_SMC_ECC_PR13 (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_SMC_ECC_PR14 (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_SMC_ECC_PR15 (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_SMC_SETUP0 (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_SMC_PULSE0 (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_SMC_CYCLE0 (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_SMC_TIMINGS0 (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_SMC_MODE0 (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_SMC_SETUP1 (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_SMC_PULSE1 (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_SMC_CYCLE1 (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_SMC_TIMINGS1 (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_SMC_MODE1 (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_SMC_SETUP2 (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_SMC_PULSE2 (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_SMC_CYCLE2 (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_SMC_TIMINGS2 (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_SMC_MODE2 (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 78 #define REG_SMC_SETUP3 (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 79 #define REG_SMC_PULSE3 (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 80 #define REG_SMC_CYCLE3 (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 81 #define REG_SMC_TIMINGS3 (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 82 #define REG_SMC_MODE3 (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 83 #define REG_SMC_OCMS (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
Pawel Zarembski 0:01f31e923fe2 84 #define REG_SMC_KEY1 (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
Pawel Zarembski 0:01f31e923fe2 85 #define REG_SMC_KEY2 (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
Pawel Zarembski 0:01f31e923fe2 86 #define REG_SMC_WPCR (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
Pawel Zarembski 0:01f31e923fe2 87 #define REG_SMC_WPSR (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
Pawel Zarembski 0:01f31e923fe2 88 #else
Pawel Zarembski 0:01f31e923fe2 89 #define REG_SMC_CFG (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
Pawel Zarembski 0:01f31e923fe2 90 #define REG_SMC_CTRL (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
Pawel Zarembski 0:01f31e923fe2 91 #define REG_SMC_SR (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
Pawel Zarembski 0:01f31e923fe2 92 #define REG_SMC_IER (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 93 #define REG_SMC_IDR (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 94 #define REG_SMC_IMR (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 95 #define REG_SMC_ADDR (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
Pawel Zarembski 0:01f31e923fe2 96 #define REG_SMC_BANK (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
Pawel Zarembski 0:01f31e923fe2 97 #define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
Pawel Zarembski 0:01f31e923fe2 98 #define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
Pawel Zarembski 0:01f31e923fe2 99 #define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
Pawel Zarembski 0:01f31e923fe2 100 #define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
Pawel Zarembski 0:01f31e923fe2 101 #define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
Pawel Zarembski 0:01f31e923fe2 102 #define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
Pawel Zarembski 0:01f31e923fe2 103 #define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
Pawel Zarembski 0:01f31e923fe2 104 #define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
Pawel Zarembski 0:01f31e923fe2 105 #define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
Pawel Zarembski 0:01f31e923fe2 106 #define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
Pawel Zarembski 0:01f31e923fe2 107 #define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
Pawel Zarembski 0:01f31e923fe2 108 #define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
Pawel Zarembski 0:01f31e923fe2 109 #define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
Pawel Zarembski 0:01f31e923fe2 110 #define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
Pawel Zarembski 0:01f31e923fe2 111 #define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
Pawel Zarembski 0:01f31e923fe2 112 #define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
Pawel Zarembski 0:01f31e923fe2 113 #define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
Pawel Zarembski 0:01f31e923fe2 114 #define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
Pawel Zarembski 0:01f31e923fe2 115 #define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
Pawel Zarembski 0:01f31e923fe2 116 #define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
Pawel Zarembski 0:01f31e923fe2 117 #define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 118 #define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 119 #define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 120 #define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 121 #define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
Pawel Zarembski 0:01f31e923fe2 122 #define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 123 #define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 124 #define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 125 #define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 126 #define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
Pawel Zarembski 0:01f31e923fe2 127 #define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 128 #define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 129 #define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 130 #define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 131 #define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
Pawel Zarembski 0:01f31e923fe2 132 #define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 133 #define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 134 #define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 135 #define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 136 #define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
Pawel Zarembski 0:01f31e923fe2 137 #define REG_SMC_OCMS (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
Pawel Zarembski 0:01f31e923fe2 138 #define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
Pawel Zarembski 0:01f31e923fe2 139 #define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
Pawel Zarembski 0:01f31e923fe2 140 #define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
Pawel Zarembski 0:01f31e923fe2 141 #define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
Pawel Zarembski 0:01f31e923fe2 142 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 143
Pawel Zarembski 0:01f31e923fe2 144 #endif /* _SAM3U_SMC_INSTANCE_ */