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Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/instance/pwm.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_PWM_INSTANCE_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_PWM_INSTANCE_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | /* ========== Register definition for PWM peripheral ========== */ |
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0:01f31e923fe2 | 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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0:01f31e923fe2 | 35 | #define REG_PWM_CLK (0x4008C000U) /**< \brief (PWM) PWM Clock Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define REG_PWM_ENA (0x4008C004U) /**< \brief (PWM) PWM Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | #define REG_PWM_DIS (0x4008C008U) /**< \brief (PWM) PWM Disable Register */ |
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0:01f31e923fe2 | 38 | #define REG_PWM_SR (0x4008C00CU) /**< \brief (PWM) PWM Status Register */ |
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0:01f31e923fe2 | 39 | #define REG_PWM_IER1 (0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ |
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0:01f31e923fe2 | 40 | #define REG_PWM_IDR1 (0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ |
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0:01f31e923fe2 | 41 | #define REG_PWM_IMR1 (0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ |
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0:01f31e923fe2 | 42 | #define REG_PWM_ISR1 (0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ |
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0:01f31e923fe2 | 43 | #define REG_PWM_SCM (0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ |
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0:01f31e923fe2 | 44 | #define REG_PWM_SCUC (0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ |
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0:01f31e923fe2 | 45 | #define REG_PWM_SCUP (0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ |
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0:01f31e923fe2 | 46 | #define REG_PWM_SCUPUPD (0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ |
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0:01f31e923fe2 | 47 | #define REG_PWM_IER2 (0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ |
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0:01f31e923fe2 | 48 | #define REG_PWM_IDR2 (0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ |
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0:01f31e923fe2 | 49 | #define REG_PWM_IMR2 (0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ |
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0:01f31e923fe2 | 50 | #define REG_PWM_ISR2 (0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ |
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0:01f31e923fe2 | 51 | #define REG_PWM_OOV (0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ |
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0:01f31e923fe2 | 52 | #define REG_PWM_OS (0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ |
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0:01f31e923fe2 | 53 | #define REG_PWM_OSS (0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ |
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0:01f31e923fe2 | 54 | #define REG_PWM_OSC (0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ |
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0:01f31e923fe2 | 55 | #define REG_PWM_OSSUPD (0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ |
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0:01f31e923fe2 | 56 | #define REG_PWM_OSCUPD (0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ |
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0:01f31e923fe2 | 57 | #define REG_PWM_FMR (0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ |
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0:01f31e923fe2 | 58 | #define REG_PWM_FSR (0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ |
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0:01f31e923fe2 | 59 | #define REG_PWM_FCR (0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ |
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0:01f31e923fe2 | 60 | #define REG_PWM_FPV (0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ |
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0:01f31e923fe2 | 61 | #define REG_PWM_FPE (0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ |
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0:01f31e923fe2 | 62 | #define REG_PWM_ELMR (0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ |
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0:01f31e923fe2 | 63 | #define REG_PWM_SMMR (0x4008C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ |
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0:01f31e923fe2 | 64 | #define REG_PWM_WPCR (0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ |
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0:01f31e923fe2 | 65 | #define REG_PWM_WPSR (0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ |
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0:01f31e923fe2 | 66 | #define REG_PWM_TPR (0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ |
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0:01f31e923fe2 | 67 | #define REG_PWM_TCR (0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ |
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0:01f31e923fe2 | 68 | #define REG_PWM_TNPR (0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ |
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0:01f31e923fe2 | 69 | #define REG_PWM_TNCR (0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ |
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0:01f31e923fe2 | 70 | #define REG_PWM_PTCR (0x4008C120U) /**< \brief (PWM) Transfer Control Register */ |
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0:01f31e923fe2 | 71 | #define REG_PWM_PTSR (0x4008C124U) /**< \brief (PWM) Transfer Status Register */ |
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0:01f31e923fe2 | 72 | #define REG_PWM_CMPV0 (0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ |
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0:01f31e923fe2 | 73 | #define REG_PWM_CMPVUPD0 (0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ |
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0:01f31e923fe2 | 74 | #define REG_PWM_CMPM0 (0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ |
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0:01f31e923fe2 | 75 | #define REG_PWM_CMPMUPD0 (0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ |
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0:01f31e923fe2 | 76 | #define REG_PWM_CMPV1 (0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ |
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0:01f31e923fe2 | 77 | #define REG_PWM_CMPVUPD1 (0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ |
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0:01f31e923fe2 | 78 | #define REG_PWM_CMPM1 (0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ |
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0:01f31e923fe2 | 79 | #define REG_PWM_CMPMUPD1 (0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ |
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0:01f31e923fe2 | 80 | #define REG_PWM_CMPV2 (0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ |
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0:01f31e923fe2 | 81 | #define REG_PWM_CMPVUPD2 (0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ |
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0:01f31e923fe2 | 82 | #define REG_PWM_CMPM2 (0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ |
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0:01f31e923fe2 | 83 | #define REG_PWM_CMPMUPD2 (0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ |
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0:01f31e923fe2 | 84 | #define REG_PWM_CMPV3 (0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ |
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0:01f31e923fe2 | 85 | #define REG_PWM_CMPVUPD3 (0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ |
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0:01f31e923fe2 | 86 | #define REG_PWM_CMPM3 (0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ |
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0:01f31e923fe2 | 87 | #define REG_PWM_CMPMUPD3 (0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ |
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0:01f31e923fe2 | 88 | #define REG_PWM_CMPV4 (0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ |
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0:01f31e923fe2 | 89 | #define REG_PWM_CMPVUPD4 (0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ |
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0:01f31e923fe2 | 90 | #define REG_PWM_CMPM4 (0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ |
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0:01f31e923fe2 | 91 | #define REG_PWM_CMPMUPD4 (0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ |
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0:01f31e923fe2 | 92 | #define REG_PWM_CMPV5 (0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ |
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0:01f31e923fe2 | 93 | #define REG_PWM_CMPVUPD5 (0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ |
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0:01f31e923fe2 | 94 | #define REG_PWM_CMPM5 (0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ |
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0:01f31e923fe2 | 95 | #define REG_PWM_CMPMUPD5 (0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ |
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0:01f31e923fe2 | 96 | #define REG_PWM_CMPV6 (0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ |
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0:01f31e923fe2 | 97 | #define REG_PWM_CMPVUPD6 (0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ |
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0:01f31e923fe2 | 98 | #define REG_PWM_CMPM6 (0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ |
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0:01f31e923fe2 | 99 | #define REG_PWM_CMPMUPD6 (0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ |
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0:01f31e923fe2 | 100 | #define REG_PWM_CMPV7 (0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ |
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0:01f31e923fe2 | 101 | #define REG_PWM_CMPVUPD7 (0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ |
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0:01f31e923fe2 | 102 | #define REG_PWM_CMPM7 (0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ |
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0:01f31e923fe2 | 103 | #define REG_PWM_CMPMUPD7 (0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ |
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0:01f31e923fe2 | 104 | #define REG_PWM_CMR0 (0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ |
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0:01f31e923fe2 | 105 | #define REG_PWM_CDTY0 (0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ |
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0:01f31e923fe2 | 106 | #define REG_PWM_CDTYUPD0 (0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 107 | #define REG_PWM_CPRD0 (0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ |
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0:01f31e923fe2 | 108 | #define REG_PWM_CPRDUPD0 (0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 109 | #define REG_PWM_CCNT0 (0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ |
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0:01f31e923fe2 | 110 | #define REG_PWM_DT0 (0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ |
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0:01f31e923fe2 | 111 | #define REG_PWM_DTUPD0 (0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 112 | #define REG_PWM_CMR1 (0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ |
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0:01f31e923fe2 | 113 | #define REG_PWM_CDTY1 (0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ |
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0:01f31e923fe2 | 114 | #define REG_PWM_CDTYUPD1 (0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 115 | #define REG_PWM_CPRD1 (0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ |
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0:01f31e923fe2 | 116 | #define REG_PWM_CPRDUPD1 (0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 117 | #define REG_PWM_CCNT1 (0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ |
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0:01f31e923fe2 | 118 | #define REG_PWM_DT1 (0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ |
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0:01f31e923fe2 | 119 | #define REG_PWM_DTUPD1 (0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 120 | #define REG_PWM_CMR2 (0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ |
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0:01f31e923fe2 | 121 | #define REG_PWM_CDTY2 (0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ |
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0:01f31e923fe2 | 122 | #define REG_PWM_CDTYUPD2 (0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 123 | #define REG_PWM_CPRD2 (0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ |
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0:01f31e923fe2 | 124 | #define REG_PWM_CPRDUPD2 (0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 125 | #define REG_PWM_CCNT2 (0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ |
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0:01f31e923fe2 | 126 | #define REG_PWM_DT2 (0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ |
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0:01f31e923fe2 | 127 | #define REG_PWM_DTUPD2 (0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 128 | #define REG_PWM_CMR3 (0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ |
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0:01f31e923fe2 | 129 | #define REG_PWM_CDTY3 (0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ |
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0:01f31e923fe2 | 130 | #define REG_PWM_CDTYUPD3 (0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 131 | #define REG_PWM_CPRD3 (0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ |
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0:01f31e923fe2 | 132 | #define REG_PWM_CPRDUPD3 (0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 133 | #define REG_PWM_CCNT3 (0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ |
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0:01f31e923fe2 | 134 | #define REG_PWM_DT3 (0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ |
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0:01f31e923fe2 | 135 | #define REG_PWM_DTUPD3 (0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 136 | #else |
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0:01f31e923fe2 | 137 | #define REG_PWM_CLK (*(RwReg*)0x4008C000U) /**< \brief (PWM) PWM Clock Register */ |
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0:01f31e923fe2 | 138 | #define REG_PWM_ENA (*(WoReg*)0x4008C004U) /**< \brief (PWM) PWM Enable Register */ |
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0:01f31e923fe2 | 139 | #define REG_PWM_DIS (*(WoReg*)0x4008C008U) /**< \brief (PWM) PWM Disable Register */ |
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0:01f31e923fe2 | 140 | #define REG_PWM_SR (*(RoReg*)0x4008C00CU) /**< \brief (PWM) PWM Status Register */ |
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0:01f31e923fe2 | 141 | #define REG_PWM_IER1 (*(WoReg*)0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ |
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0:01f31e923fe2 | 142 | #define REG_PWM_IDR1 (*(WoReg*)0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ |
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0:01f31e923fe2 | 143 | #define REG_PWM_IMR1 (*(RoReg*)0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ |
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0:01f31e923fe2 | 144 | #define REG_PWM_ISR1 (*(RoReg*)0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ |
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0:01f31e923fe2 | 145 | #define REG_PWM_SCM (*(RwReg*)0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ |
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0:01f31e923fe2 | 146 | #define REG_PWM_SCUC (*(RwReg*)0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ |
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0:01f31e923fe2 | 147 | #define REG_PWM_SCUP (*(RwReg*)0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ |
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0:01f31e923fe2 | 148 | #define REG_PWM_SCUPUPD (*(WoReg*)0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ |
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0:01f31e923fe2 | 149 | #define REG_PWM_IER2 (*(WoReg*)0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ |
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0:01f31e923fe2 | 150 | #define REG_PWM_IDR2 (*(WoReg*)0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ |
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0:01f31e923fe2 | 151 | #define REG_PWM_IMR2 (*(RoReg*)0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ |
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0:01f31e923fe2 | 152 | #define REG_PWM_ISR2 (*(RoReg*)0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ |
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0:01f31e923fe2 | 153 | #define REG_PWM_OOV (*(RwReg*)0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ |
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0:01f31e923fe2 | 154 | #define REG_PWM_OS (*(RwReg*)0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ |
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0:01f31e923fe2 | 155 | #define REG_PWM_OSS (*(WoReg*)0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ |
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0:01f31e923fe2 | 156 | #define REG_PWM_OSC (*(WoReg*)0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ |
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0:01f31e923fe2 | 157 | #define REG_PWM_OSSUPD (*(WoReg*)0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ |
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0:01f31e923fe2 | 158 | #define REG_PWM_OSCUPD (*(WoReg*)0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ |
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0:01f31e923fe2 | 159 | #define REG_PWM_FMR (*(RwReg*)0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ |
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0:01f31e923fe2 | 160 | #define REG_PWM_FSR (*(RoReg*)0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ |
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0:01f31e923fe2 | 161 | #define REG_PWM_FCR (*(WoReg*)0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ |
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0:01f31e923fe2 | 162 | #define REG_PWM_FPV (*(RwReg*)0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ |
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0:01f31e923fe2 | 163 | #define REG_PWM_FPE (*(RwReg*)0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ |
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0:01f31e923fe2 | 164 | #define REG_PWM_ELMR (*(RwReg*)0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ |
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0:01f31e923fe2 | 165 | #define REG_PWM_SMMR (*(RwReg*)0x4008C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ |
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0:01f31e923fe2 | 166 | #define REG_PWM_WPCR (*(WoReg*)0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ |
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0:01f31e923fe2 | 167 | #define REG_PWM_WPSR (*(RoReg*)0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ |
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0:01f31e923fe2 | 168 | #define REG_PWM_TPR (*(RwReg*)0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ |
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0:01f31e923fe2 | 169 | #define REG_PWM_TCR (*(RwReg*)0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ |
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0:01f31e923fe2 | 170 | #define REG_PWM_TNPR (*(RwReg*)0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ |
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0:01f31e923fe2 | 171 | #define REG_PWM_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ |
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0:01f31e923fe2 | 172 | #define REG_PWM_PTCR (*(WoReg*)0x4008C120U) /**< \brief (PWM) Transfer Control Register */ |
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0:01f31e923fe2 | 173 | #define REG_PWM_PTSR (*(RoReg*)0x4008C124U) /**< \brief (PWM) Transfer Status Register */ |
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0:01f31e923fe2 | 174 | #define REG_PWM_CMPV0 (*(RwReg*)0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ |
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0:01f31e923fe2 | 175 | #define REG_PWM_CMPVUPD0 (*(WoReg*)0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ |
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0:01f31e923fe2 | 176 | #define REG_PWM_CMPM0 (*(RwReg*)0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ |
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0:01f31e923fe2 | 177 | #define REG_PWM_CMPMUPD0 (*(WoReg*)0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ |
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0:01f31e923fe2 | 178 | #define REG_PWM_CMPV1 (*(RwReg*)0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ |
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0:01f31e923fe2 | 179 | #define REG_PWM_CMPVUPD1 (*(WoReg*)0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ |
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0:01f31e923fe2 | 180 | #define REG_PWM_CMPM1 (*(RwReg*)0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ |
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0:01f31e923fe2 | 181 | #define REG_PWM_CMPMUPD1 (*(WoReg*)0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ |
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0:01f31e923fe2 | 182 | #define REG_PWM_CMPV2 (*(RwReg*)0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ |
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0:01f31e923fe2 | 183 | #define REG_PWM_CMPVUPD2 (*(WoReg*)0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ |
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0:01f31e923fe2 | 184 | #define REG_PWM_CMPM2 (*(RwReg*)0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ |
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0:01f31e923fe2 | 185 | #define REG_PWM_CMPMUPD2 (*(WoReg*)0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ |
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0:01f31e923fe2 | 186 | #define REG_PWM_CMPV3 (*(RwReg*)0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ |
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0:01f31e923fe2 | 187 | #define REG_PWM_CMPVUPD3 (*(WoReg*)0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ |
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0:01f31e923fe2 | 188 | #define REG_PWM_CMPM3 (*(RwReg*)0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ |
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0:01f31e923fe2 | 189 | #define REG_PWM_CMPMUPD3 (*(WoReg*)0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ |
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0:01f31e923fe2 | 190 | #define REG_PWM_CMPV4 (*(RwReg*)0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ |
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0:01f31e923fe2 | 191 | #define REG_PWM_CMPVUPD4 (*(WoReg*)0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ |
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0:01f31e923fe2 | 192 | #define REG_PWM_CMPM4 (*(RwReg*)0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ |
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0:01f31e923fe2 | 193 | #define REG_PWM_CMPMUPD4 (*(WoReg*)0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ |
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0:01f31e923fe2 | 194 | #define REG_PWM_CMPV5 (*(RwReg*)0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ |
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0:01f31e923fe2 | 195 | #define REG_PWM_CMPVUPD5 (*(WoReg*)0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ |
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0:01f31e923fe2 | 196 | #define REG_PWM_CMPM5 (*(RwReg*)0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ |
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0:01f31e923fe2 | 197 | #define REG_PWM_CMPMUPD5 (*(WoReg*)0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ |
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0:01f31e923fe2 | 198 | #define REG_PWM_CMPV6 (*(RwReg*)0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ |
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0:01f31e923fe2 | 199 | #define REG_PWM_CMPVUPD6 (*(WoReg*)0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ |
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0:01f31e923fe2 | 200 | #define REG_PWM_CMPM6 (*(RwReg*)0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ |
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0:01f31e923fe2 | 201 | #define REG_PWM_CMPMUPD6 (*(WoReg*)0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ |
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0:01f31e923fe2 | 202 | #define REG_PWM_CMPV7 (*(RwReg*)0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ |
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0:01f31e923fe2 | 203 | #define REG_PWM_CMPVUPD7 (*(WoReg*)0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ |
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0:01f31e923fe2 | 204 | #define REG_PWM_CMPM7 (*(RwReg*)0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ |
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0:01f31e923fe2 | 205 | #define REG_PWM_CMPMUPD7 (*(WoReg*)0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ |
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0:01f31e923fe2 | 206 | #define REG_PWM_CMR0 (*(RwReg*)0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ |
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0:01f31e923fe2 | 207 | #define REG_PWM_CDTY0 (*(RwReg*)0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ |
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0:01f31e923fe2 | 208 | #define REG_PWM_CDTYUPD0 (*(WoReg*)0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 209 | #define REG_PWM_CPRD0 (*(RwReg*)0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ |
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0:01f31e923fe2 | 210 | #define REG_PWM_CPRDUPD0 (*(WoReg*)0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 211 | #define REG_PWM_CCNT0 (*(RoReg*)0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ |
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0:01f31e923fe2 | 212 | #define REG_PWM_DT0 (*(RwReg*)0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ |
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0:01f31e923fe2 | 213 | #define REG_PWM_DTUPD0 (*(WoReg*)0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ |
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0:01f31e923fe2 | 214 | #define REG_PWM_CMR1 (*(RwReg*)0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ |
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0:01f31e923fe2 | 215 | #define REG_PWM_CDTY1 (*(RwReg*)0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ |
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0:01f31e923fe2 | 216 | #define REG_PWM_CDTYUPD1 (*(WoReg*)0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 217 | #define REG_PWM_CPRD1 (*(RwReg*)0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ |
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0:01f31e923fe2 | 218 | #define REG_PWM_CPRDUPD1 (*(WoReg*)0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 219 | #define REG_PWM_CCNT1 (*(RoReg*)0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ |
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0:01f31e923fe2 | 220 | #define REG_PWM_DT1 (*(RwReg*)0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ |
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0:01f31e923fe2 | 221 | #define REG_PWM_DTUPD1 (*(WoReg*)0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ |
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0:01f31e923fe2 | 222 | #define REG_PWM_CMR2 (*(RwReg*)0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ |
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0:01f31e923fe2 | 223 | #define REG_PWM_CDTY2 (*(RwReg*)0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ |
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0:01f31e923fe2 | 224 | #define REG_PWM_CDTYUPD2 (*(WoReg*)0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 225 | #define REG_PWM_CPRD2 (*(RwReg*)0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ |
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0:01f31e923fe2 | 226 | #define REG_PWM_CPRDUPD2 (*(WoReg*)0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 227 | #define REG_PWM_CCNT2 (*(RoReg*)0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ |
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0:01f31e923fe2 | 228 | #define REG_PWM_DT2 (*(RwReg*)0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ |
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0:01f31e923fe2 | 229 | #define REG_PWM_DTUPD2 (*(WoReg*)0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ |
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0:01f31e923fe2 | 230 | #define REG_PWM_CMR3 (*(RwReg*)0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ |
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0:01f31e923fe2 | 231 | #define REG_PWM_CDTY3 (*(RwReg*)0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ |
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0:01f31e923fe2 | 232 | #define REG_PWM_CDTYUPD3 (*(WoReg*)0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 233 | #define REG_PWM_CPRD3 (*(RwReg*)0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ |
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0:01f31e923fe2 | 234 | #define REG_PWM_CPRDUPD3 (*(WoReg*)0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 235 | #define REG_PWM_CCNT3 (*(RoReg*)0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ |
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0:01f31e923fe2 | 236 | #define REG_PWM_DT3 (*(RwReg*)0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ |
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0:01f31e923fe2 | 237 | #define REG_PWM_DTUPD3 (*(WoReg*)0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ |
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0:01f31e923fe2 | 238 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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0:01f31e923fe2 | 239 | |
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0:01f31e923fe2 | 240 | #endif /* _SAM3U_PWM_INSTANCE_ */ |