Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/pmc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_PMC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_PMC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for PMC peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_CKGR_UCKR (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 56 #else
Pawel Zarembski 0:01f31e923fe2 57 #define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_CKGR_UCKR (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_CKGR_MCFR (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 #endif /* _SAM3U_PMC_INSTANCE_ */