Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/dmac.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_DMAC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_DMAC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for DMAC peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_DMAC_GCFG (0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_DMAC_EN (0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_DMAC_SREQ (0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_DMAC_CREQ (0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_DMAC_LAST (0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_DMAC_EBCIER (0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_DMAC_EBCIDR (0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_DMAC_EBCIMR (0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_DMAC_EBCISR (0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_DMAC_CHER (0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_DMAC_CHDR (0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_DMAC_CHSR (0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_DMAC_SADDR0 (0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_DMAC_DADDR0 (0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_DMAC_DSCR0 (0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_DMAC_CTRLA0 (0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_DMAC_CTRLB0 (0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_DMAC_CFG0 (0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_DMAC_SADDR1 (0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_DMAC_DADDR1 (0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_DMAC_DSCR1 (0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 56 #define REG_DMAC_CTRLA1 (0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 57 #define REG_DMAC_CTRLB1 (0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_DMAC_CFG1 (0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_DMAC_SADDR2 (0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_DMAC_DADDR2 (0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_DMAC_DSCR2 (0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_DMAC_CTRLA2 (0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_DMAC_CTRLB2 (0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_DMAC_CFG2 (0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_DMAC_SADDR3 (0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_DMAC_DADDR3 (0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_DMAC_DSCR3 (0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_DMAC_CTRLA3 (0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_DMAC_CTRLB3 (0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_DMAC_CFG3 (0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_DMAC_WPMR (0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_DMAC_WPSR (0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 73 #else
Pawel Zarembski 0:01f31e923fe2 74 #define REG_DMAC_GCFG (*(RwReg*)0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_DMAC_EN (*(RwReg*)0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_DMAC_SREQ (*(RwReg*)0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_DMAC_CREQ (*(RwReg*)0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
Pawel Zarembski 0:01f31e923fe2 78 #define REG_DMAC_LAST (*(RwReg*)0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
Pawel Zarembski 0:01f31e923fe2 79 #define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
Pawel Zarembski 0:01f31e923fe2 80 #define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
Pawel Zarembski 0:01f31e923fe2 81 #define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
Pawel Zarembski 0:01f31e923fe2 82 #define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
Pawel Zarembski 0:01f31e923fe2 83 #define REG_DMAC_CHER (*(WoReg*)0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
Pawel Zarembski 0:01f31e923fe2 84 #define REG_DMAC_CHDR (*(WoReg*)0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
Pawel Zarembski 0:01f31e923fe2 85 #define REG_DMAC_CHSR (*(RoReg*)0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
Pawel Zarembski 0:01f31e923fe2 86 #define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 87 #define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 88 #define REG_DMAC_DSCR0 (*(RwReg*)0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 89 #define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 90 #define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 91 #define REG_DMAC_CFG0 (*(RwReg*)0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
Pawel Zarembski 0:01f31e923fe2 92 #define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 93 #define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 94 #define REG_DMAC_DSCR1 (*(RwReg*)0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 95 #define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 96 #define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 97 #define REG_DMAC_CFG1 (*(RwReg*)0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
Pawel Zarembski 0:01f31e923fe2 98 #define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 99 #define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 100 #define REG_DMAC_DSCR2 (*(RwReg*)0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 101 #define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 102 #define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 103 #define REG_DMAC_CFG2 (*(RwReg*)0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
Pawel Zarembski 0:01f31e923fe2 104 #define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 105 #define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 106 #define REG_DMAC_DSCR3 (*(RwReg*)0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 107 #define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 108 #define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 109 #define REG_DMAC_CFG3 (*(RwReg*)0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
Pawel Zarembski 0:01f31e923fe2 110 #define REG_DMAC_WPMR (*(RwReg*)0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 111 #define REG_DMAC_WPSR (*(RoReg*)0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 112 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 113
Pawel Zarembski 0:01f31e923fe2 114 #endif /* _SAM3U_DMAC_INSTANCE_ */