Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/udphs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_UDPHS_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_UDPHS_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR USB High Speed Device Port */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_UDPHS USB High Speed Device Port */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief UdphsDma hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | } UdphsDma; |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | /** \brief UdphsEpt hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | RoReg Reserved1[1]; |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | } UdphsEpt; |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | /** \brief Udphs hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define UDPHSEPT_NUMBER 7 |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | #define UDPHSDMA_NUMBER 6 |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | RoReg Reserved1[2]; |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | RoReg Reserved2[48]; |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | RoReg Reserved3[7]; |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | RoReg Reserved4[72]; |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | } Udphs; |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | /* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define UDPHS_CTRL_DEV_ADDR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | #define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | #define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | /* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | #define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define UDPHS_FNUM_FRAME_NUMBER_Pos 3 |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | /* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | #define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | #define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | #define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | /* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | /* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | /* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | /* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define UDPHS_TST_SPEED_CFG_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | /* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define UDPHS_EPTCFG_EPT_SIZE_Pos 0 |
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0:01f31e923fe2 | 163 | #define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define UDPHS_EPTCFG_EPT_TYPE_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define UDPHS_EPTCFG_BK_NUMBER_Pos 6 |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define UDPHS_EPTCFG_NB_TRANS_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | /* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define UDPHS_EPTCTLENB_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | #define UDPHS_EPTCTLENB_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | #define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define UDPHS_EPTCTLENB_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Error Flow Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define UDPHS_EPTCTLENB_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) ISO CRC Error/Number of Transaction Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | #define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) Bank Flush Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | /* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define UDPHS_EPTCTLDIS_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | #define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define UDPHS_EPTCTLDIS_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define UDPHS_EPTCTLDIS_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Error Flow Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define UDPHS_EPTCTLDIS_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) ISO CRC Error/Number of Transaction Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) bank flush error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | /* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | #define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | #define UDPHS_EPTCTL_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define UDPHS_EPTCTL_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | #define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define UDPHS_EPTCTL_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Error Flow Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define UDPHS_EPTCTL_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTL) ISO CRC Error/Number of Transaction Error Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) Bank Flush Error Interrupt Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | /* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define UDPHS_EPTSETSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | #define UDPHS_EPTSETSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | #define UDPHS_EPTSETSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | /* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define UDPHS_EPTCLRSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Error Flow Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | #define UDPHS_EPTCLRSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Number of Transaction Error Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | #define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) Bank Flush Error Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | /* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6 |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | #define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define UDPHS_EPTSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | #define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define UDPHS_EPTSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | #define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define UDPHS_EPTSTA_CURBK_CTLDIR_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | #define UDPHS_EPTSTA_CURBK_CTLDIR_Msk (0x3u << UDPHS_EPTSTA_CURBK_CTLDIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | #define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18 |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | #define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | #define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | #define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | #define UDPHS_EPTSTA_BYTE_COUNT_Pos 20 |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | #define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | #define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */ |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | #define UDPHS_EPTSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | #define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Error Flow */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define UDPHS_EPTSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTSTA) CRC ISO Error/Number of Transaction Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | #define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) Bank Flush Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define UDPHS_EPTSTA_CURBK_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | #define UDPHS_EPTSTA_CURBK_Msk (0x3u << UDPHS_EPTSTA_CURBK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank */ |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | #define UDPHS_EPTSTA_CURBK_BANK0 (0x0u << 16) /**< \brief (UDPHS_EPTSTA) Bank 0 (or single bank) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define UDPHS_EPTSTA_CURBK_BANK1 (0x1u << 16) /**< \brief (UDPHS_EPTSTA) Bank 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define UDPHS_EPTSTA_CURBK_BANK2 (0x2u << 16) /**< \brief (UDPHS_EPTSTA) Bank 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | /* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | #define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) Next Descriptor Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | #define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | /* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | #define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | #define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) Buffer Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | #define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | /* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | #define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) (Channel Enable Command) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 314 | #define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 315 | #define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 316 | #define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 317 | #define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 318 | #define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 319 | #define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 320 | #define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 321 | #define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 322 | #define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 323 | #define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 324 | /* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 325 | #define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 326 | #define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 327 | #define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 328 | #define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 329 | #define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 330 | #define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 331 | #define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 332 | #define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 333 | |
| Pawel Zarembski |
0:01f31e923fe2 | 334 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 335 | |
| Pawel Zarembski |
0:01f31e923fe2 | 336 | |
| Pawel Zarembski |
0:01f31e923fe2 | 337 | #endif /* _SAM3U_UDPHS_COMPONENT_ */ |