Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/uart.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_UART_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_UART_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Uart hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
Pawel Zarembski 0:01f31e923fe2 44 WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 45 WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 46 RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 47 RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
Pawel Zarembski 0:01f31e923fe2 48 RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
Pawel Zarembski 0:01f31e923fe2 49 WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
Pawel Zarembski 0:01f31e923fe2 50 RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
Pawel Zarembski 0:01f31e923fe2 51 RoReg Reserved1[55];
Pawel Zarembski 0:01f31e923fe2 52 RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 53 RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 54 RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 55 RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 56 RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 57 RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 58 RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 59 RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 60 WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 61 RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 62 } Uart;
Pawel Zarembski 0:01f31e923fe2 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 64 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 65 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
Pawel Zarembski 0:01f31e923fe2 66 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
Pawel Zarembski 0:01f31e923fe2 67 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
Pawel Zarembski 0:01f31e923fe2 68 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
Pawel Zarembski 0:01f31e923fe2 69 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
Pawel Zarembski 0:01f31e923fe2 70 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
Pawel Zarembski 0:01f31e923fe2 71 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
Pawel Zarembski 0:01f31e923fe2 72 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 73 #define UART_MR_PAR_Pos 9
Pawel Zarembski 0:01f31e923fe2 74 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
Pawel Zarembski 0:01f31e923fe2 75 #define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
Pawel Zarembski 0:01f31e923fe2 76 #define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
Pawel Zarembski 0:01f31e923fe2 77 #define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
Pawel Zarembski 0:01f31e923fe2 78 #define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
Pawel Zarembski 0:01f31e923fe2 79 #define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
Pawel Zarembski 0:01f31e923fe2 80 #define UART_MR_CHMODE_Pos 14
Pawel Zarembski 0:01f31e923fe2 81 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
Pawel Zarembski 0:01f31e923fe2 82 #define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
Pawel Zarembski 0:01f31e923fe2 83 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
Pawel Zarembski 0:01f31e923fe2 84 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
Pawel Zarembski 0:01f31e923fe2 85 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
Pawel Zarembski 0:01f31e923fe2 86 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 87 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 88 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 89 #define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
Pawel Zarembski 0:01f31e923fe2 90 #define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
Pawel Zarembski 0:01f31e923fe2 91 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 92 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 93 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 94 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
Pawel Zarembski 0:01f31e923fe2 95 #define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
Pawel Zarembski 0:01f31e923fe2 96 #define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
Pawel Zarembski 0:01f31e923fe2 97 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 98 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 99 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 100 #define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
Pawel Zarembski 0:01f31e923fe2 101 #define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
Pawel Zarembski 0:01f31e923fe2 102 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 103 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 104 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 105 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
Pawel Zarembski 0:01f31e923fe2 106 #define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
Pawel Zarembski 0:01f31e923fe2 107 #define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
Pawel Zarembski 0:01f31e923fe2 108 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 109 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 110 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
Pawel Zarembski 0:01f31e923fe2 111 #define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
Pawel Zarembski 0:01f31e923fe2 112 #define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
Pawel Zarembski 0:01f31e923fe2 113 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 114 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 115 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
Pawel Zarembski 0:01f31e923fe2 116 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
Pawel Zarembski 0:01f31e923fe2 117 #define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
Pawel Zarembski 0:01f31e923fe2 118 #define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
Pawel Zarembski 0:01f31e923fe2 119 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 120 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
Pawel Zarembski 0:01f31e923fe2 121 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
Pawel Zarembski 0:01f31e923fe2 122 #define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
Pawel Zarembski 0:01f31e923fe2 123 #define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
Pawel Zarembski 0:01f31e923fe2 124 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
Pawel Zarembski 0:01f31e923fe2 125 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
Pawel Zarembski 0:01f31e923fe2 126 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
Pawel Zarembski 0:01f31e923fe2 127 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
Pawel Zarembski 0:01f31e923fe2 128 #define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
Pawel Zarembski 0:01f31e923fe2 129 #define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
Pawel Zarembski 0:01f31e923fe2 130 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 131 #define UART_RHR_RXCHR_Pos 0
Pawel Zarembski 0:01f31e923fe2 132 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
Pawel Zarembski 0:01f31e923fe2 133 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 134 #define UART_THR_TXCHR_Pos 0
Pawel Zarembski 0:01f31e923fe2 135 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
Pawel Zarembski 0:01f31e923fe2 136 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
Pawel Zarembski 0:01f31e923fe2 137 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
Pawel Zarembski 0:01f31e923fe2 138 #define UART_BRGR_CD_Pos 0
Pawel Zarembski 0:01f31e923fe2 139 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
Pawel Zarembski 0:01f31e923fe2 140 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
Pawel Zarembski 0:01f31e923fe2 141 /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 142 #define UART_RPR_RXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 143 #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 144 #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 145 /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 146 #define UART_RCR_RXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 147 #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 148 #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 149 /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 150 #define UART_TPR_TXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 151 #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 152 #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 153 /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 154 #define UART_TCR_TXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 155 #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 156 #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 157 /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 158 #define UART_RNPR_RXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 159 #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
Pawel Zarembski 0:01f31e923fe2 160 #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 161 /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 162 #define UART_RNCR_RXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 163 #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
Pawel Zarembski 0:01f31e923fe2 164 #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 165 /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 166 #define UART_TNPR_TXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 167 #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
Pawel Zarembski 0:01f31e923fe2 168 #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 169 /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 170 #define UART_TNCR_TXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 171 #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
Pawel Zarembski 0:01f31e923fe2 172 #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 173 /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 174 #define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 175 #define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 176 #define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 177 #define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 178 /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 179 #define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 180 #define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 181
Pawel Zarembski 0:01f31e923fe2 182 /*@}*/
Pawel Zarembski 0:01f31e923fe2 183
Pawel Zarembski 0:01f31e923fe2 184
Pawel Zarembski 0:01f31e923fe2 185 #endif /* _SAM3U_UART_COMPONENT_ */