Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/twi.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 29 | |
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0:01f31e923fe2 | 30 | #ifndef _SAM3U_TWI_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_TWI_COMPONENT_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | /* ============================================================================= */ |
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0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR Two-wire Interface */ |
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0:01f31e923fe2 | 35 | /* ============================================================================= */ |
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0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_TWI Two-wire Interface */ |
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0:01f31e923fe2 | 37 | /*@{*/ |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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0:01f31e923fe2 | 40 | /** \brief Twi hardware registers */ |
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0:01f31e923fe2 | 41 | typedef struct { |
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0:01f31e923fe2 | 42 | WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ |
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0:01f31e923fe2 | 46 | RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ |
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0:01f31e923fe2 | 47 | RoReg Reserved1[3]; |
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0:01f31e923fe2 | 48 | RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ |
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0:01f31e923fe2 | 49 | WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ |
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0:01f31e923fe2 | 50 | WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ |
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0:01f31e923fe2 | 51 | RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ |
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0:01f31e923fe2 | 52 | RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ |
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0:01f31e923fe2 | 53 | WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ |
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0:01f31e923fe2 | 54 | RoReg Reserved2[50]; |
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0:01f31e923fe2 | 55 | RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ |
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0:01f31e923fe2 | 56 | RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ |
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0:01f31e923fe2 | 57 | RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ |
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0:01f31e923fe2 | 58 | RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ |
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0:01f31e923fe2 | 59 | RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ |
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0:01f31e923fe2 | 60 | RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ |
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0:01f31e923fe2 | 61 | RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ |
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0:01f31e923fe2 | 62 | RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ |
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0:01f31e923fe2 | 63 | WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ |
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0:01f31e923fe2 | 64 | RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ |
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0:01f31e923fe2 | 65 | } Twi; |
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0:01f31e923fe2 | 66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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0:01f31e923fe2 | 67 | /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ |
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0:01f31e923fe2 | 68 | #define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ |
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0:01f31e923fe2 | 69 | #define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ |
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0:01f31e923fe2 | 70 | #define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ |
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0:01f31e923fe2 | 71 | #define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ |
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0:01f31e923fe2 | 72 | #define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ |
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0:01f31e923fe2 | 73 | #define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ |
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0:01f31e923fe2 | 74 | #define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ |
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0:01f31e923fe2 | 75 | #define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ |
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0:01f31e923fe2 | 76 | /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ |
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0:01f31e923fe2 | 77 | #define TWI_MMR_IADRSZ_Pos 8 |
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0:01f31e923fe2 | 78 | #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ |
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0:01f31e923fe2 | 79 | #define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ |
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0:01f31e923fe2 | 80 | #define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ |
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0:01f31e923fe2 | 81 | #define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ |
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0:01f31e923fe2 | 82 | #define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ |
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0:01f31e923fe2 | 83 | #define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ |
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0:01f31e923fe2 | 84 | #define TWI_MMR_DADR_Pos 16 |
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0:01f31e923fe2 | 85 | #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ |
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0:01f31e923fe2 | 86 | #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) |
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0:01f31e923fe2 | 87 | /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ |
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0:01f31e923fe2 | 88 | #define TWI_SMR_SADR_Pos 16 |
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0:01f31e923fe2 | 89 | #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ |
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0:01f31e923fe2 | 90 | #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) |
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0:01f31e923fe2 | 91 | /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ |
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0:01f31e923fe2 | 92 | #define TWI_IADR_IADR_Pos 0 |
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0:01f31e923fe2 | 93 | #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ |
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0:01f31e923fe2 | 94 | #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) |
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0:01f31e923fe2 | 95 | /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ |
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0:01f31e923fe2 | 96 | #define TWI_CWGR_CLDIV_Pos 0 |
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0:01f31e923fe2 | 97 | #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ |
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0:01f31e923fe2 | 98 | #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) |
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0:01f31e923fe2 | 99 | #define TWI_CWGR_CHDIV_Pos 8 |
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0:01f31e923fe2 | 100 | #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ |
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0:01f31e923fe2 | 101 | #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) |
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0:01f31e923fe2 | 102 | #define TWI_CWGR_CKDIV_Pos 16 |
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0:01f31e923fe2 | 103 | #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ |
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0:01f31e923fe2 | 104 | #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) |
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0:01f31e923fe2 | 105 | /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ |
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0:01f31e923fe2 | 106 | #define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ |
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0:01f31e923fe2 | 107 | #define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ |
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0:01f31e923fe2 | 108 | #define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ |
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0:01f31e923fe2 | 109 | #define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ |
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0:01f31e923fe2 | 110 | #define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ |
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0:01f31e923fe2 | 111 | #define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ |
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0:01f31e923fe2 | 112 | #define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ |
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0:01f31e923fe2 | 113 | #define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ |
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0:01f31e923fe2 | 114 | #define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ |
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0:01f31e923fe2 | 115 | #define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ |
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0:01f31e923fe2 | 116 | #define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ |
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0:01f31e923fe2 | 117 | #define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ |
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0:01f31e923fe2 | 118 | #define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ |
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0:01f31e923fe2 | 119 | #define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ |
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0:01f31e923fe2 | 120 | #define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ |
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0:01f31e923fe2 | 121 | /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ |
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0:01f31e923fe2 | 122 | #define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ |
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0:01f31e923fe2 | 123 | #define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ |
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0:01f31e923fe2 | 124 | #define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ |
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0:01f31e923fe2 | 125 | #define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ |
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0:01f31e923fe2 | 126 | #define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ |
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0:01f31e923fe2 | 127 | #define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ |
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0:01f31e923fe2 | 128 | #define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ |
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0:01f31e923fe2 | 129 | #define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ |
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0:01f31e923fe2 | 130 | #define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ |
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0:01f31e923fe2 | 131 | #define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ |
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0:01f31e923fe2 | 132 | #define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ |
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0:01f31e923fe2 | 133 | #define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ |
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0:01f31e923fe2 | 134 | #define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ |
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0:01f31e923fe2 | 135 | #define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ |
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0:01f31e923fe2 | 136 | /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ |
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0:01f31e923fe2 | 137 | #define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ |
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0:01f31e923fe2 | 138 | #define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ |
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0:01f31e923fe2 | 139 | #define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ |
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0:01f31e923fe2 | 140 | #define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ |
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0:01f31e923fe2 | 141 | #define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ |
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0:01f31e923fe2 | 142 | #define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ |
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0:01f31e923fe2 | 143 | #define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ |
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0:01f31e923fe2 | 144 | #define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ |
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0:01f31e923fe2 | 145 | #define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ |
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0:01f31e923fe2 | 146 | #define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ |
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0:01f31e923fe2 | 147 | #define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ |
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0:01f31e923fe2 | 148 | #define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ |
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0:01f31e923fe2 | 149 | #define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ |
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0:01f31e923fe2 | 150 | #define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ |
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0:01f31e923fe2 | 151 | /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ |
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0:01f31e923fe2 | 152 | #define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ |
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0:01f31e923fe2 | 153 | #define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ |
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0:01f31e923fe2 | 154 | #define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ |
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0:01f31e923fe2 | 155 | #define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ |
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0:01f31e923fe2 | 156 | #define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ |
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0:01f31e923fe2 | 157 | #define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ |
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0:01f31e923fe2 | 158 | #define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ |
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0:01f31e923fe2 | 159 | #define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ |
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0:01f31e923fe2 | 160 | #define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ |
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0:01f31e923fe2 | 161 | #define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ |
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0:01f31e923fe2 | 162 | #define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ |
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0:01f31e923fe2 | 163 | #define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ |
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0:01f31e923fe2 | 164 | #define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ |
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0:01f31e923fe2 | 165 | #define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ |
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0:01f31e923fe2 | 166 | /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ |
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0:01f31e923fe2 | 167 | #define TWI_RHR_RXDATA_Pos 0 |
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0:01f31e923fe2 | 168 | #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ |
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0:01f31e923fe2 | 169 | /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ |
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0:01f31e923fe2 | 170 | #define TWI_THR_TXDATA_Pos 0 |
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0:01f31e923fe2 | 171 | #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ |
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0:01f31e923fe2 | 172 | #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) |
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0:01f31e923fe2 | 173 | /* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ |
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0:01f31e923fe2 | 174 | #define TWI_RPR_RXPTR_Pos 0 |
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0:01f31e923fe2 | 175 | #define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ |
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0:01f31e923fe2 | 176 | #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) |
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0:01f31e923fe2 | 177 | /* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ |
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0:01f31e923fe2 | 178 | #define TWI_RCR_RXCTR_Pos 0 |
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0:01f31e923fe2 | 179 | #define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ |
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0:01f31e923fe2 | 180 | #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) |
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0:01f31e923fe2 | 181 | /* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ |
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0:01f31e923fe2 | 182 | #define TWI_TPR_TXPTR_Pos 0 |
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0:01f31e923fe2 | 183 | #define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ |
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0:01f31e923fe2 | 184 | #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) |
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0:01f31e923fe2 | 185 | /* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ |
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0:01f31e923fe2 | 186 | #define TWI_TCR_TXCTR_Pos 0 |
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0:01f31e923fe2 | 187 | #define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ |
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0:01f31e923fe2 | 188 | #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) |
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0:01f31e923fe2 | 189 | /* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ |
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0:01f31e923fe2 | 190 | #define TWI_RNPR_RXNPTR_Pos 0 |
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0:01f31e923fe2 | 191 | #define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ |
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0:01f31e923fe2 | 192 | #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) |
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0:01f31e923fe2 | 193 | /* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ |
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0:01f31e923fe2 | 194 | #define TWI_RNCR_RXNCTR_Pos 0 |
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0:01f31e923fe2 | 195 | #define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ |
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0:01f31e923fe2 | 196 | #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) |
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0:01f31e923fe2 | 197 | /* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ |
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0:01f31e923fe2 | 198 | #define TWI_TNPR_TXNPTR_Pos 0 |
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0:01f31e923fe2 | 199 | #define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ |
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0:01f31e923fe2 | 200 | #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) |
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0:01f31e923fe2 | 201 | /* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ |
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0:01f31e923fe2 | 202 | #define TWI_TNCR_TXNCTR_Pos 0 |
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0:01f31e923fe2 | 203 | #define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ |
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0:01f31e923fe2 | 204 | #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) |
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0:01f31e923fe2 | 205 | /* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ |
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0:01f31e923fe2 | 206 | #define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ |
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0:01f31e923fe2 | 207 | #define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ |
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0:01f31e923fe2 | 208 | #define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ |
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0:01f31e923fe2 | 209 | #define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ |
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0:01f31e923fe2 | 210 | /* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ |
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0:01f31e923fe2 | 211 | #define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ |
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0:01f31e923fe2 | 212 | #define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ |
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0:01f31e923fe2 | 213 | |
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0:01f31e923fe2 | 214 | /*@}*/ |
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0:01f31e923fe2 | 215 | |
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0:01f31e923fe2 | 216 | |
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0:01f31e923fe2 | 217 | #endif /* _SAM3U_TWI_COMPONENT_ */ |