Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/tc.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_TC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_TC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR Timer Counter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_TC Timer Counter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief TcChannel hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RoReg Reserved1[2]; |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | RoReg Reserved2[4]; |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | } TcChannel; |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | /** \brief Tc hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define TCCHANNEL_NUMBER 3 |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | } Tc; |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define TC_CMR_TCCLKS_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define TC_CMR_BURST_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define TC_CMR_ETRGEDG_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define TC_CMR_LDRA_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | #define TC_CMR_LDRB_Pos 18 |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define TC_CMR_EEVTEDG_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define TC_CMR_EEVT_Pos 10 |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define TC_CMR_WAVSEL_Pos 13 |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define TC_CMR_ACPA_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define TC_CMR_ACPC_Pos 18 |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define TC_CMR_AEEVT_Pos 20 |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define TC_CMR_ASWTRG_Pos 22 |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define TC_CMR_BCPB_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define TC_CMR_BCPC_Pos 26 |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define TC_CMR_BEEVT_Pos 28 |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define TC_CMR_BSWTRG_Pos 30 |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define TC_CV_CV_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define TC_RA_RA_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define TC_RB_RB_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define TC_RC_RC_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define TC_BMR_TC0XC0S_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define TC_BMR_TC1XC1S_Pos 2 |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define TC_BMR_TC2XC2S_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | #define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define TC_BMR_MAXFILT_Pos 20 |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #endif /* _SAM3U_TC_COMPONENT_ */ |