Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/supc.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_SUPC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_SUPC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR Supply Controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_SUPC Supply Controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief Supc hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | } Supc; |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | /* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | #define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | #define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | #define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | #define SUPC_CR_KEY_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | /* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | #define SUPC_SMMR_SMTH_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | #define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | #define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | #define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | #define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | #define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | #define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | #define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | #define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | #define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | #define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | #define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | #define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | #define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | #define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | #define SUPC_SMMR_SMSMPL_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | #define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | #define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | #define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | /* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | #define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | #define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define SUPC_MR_KEY_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | /* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define SUPC_WUMR_FWUPDBC_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define SUPC_WUMR_WKUPDBC_Pos 12 |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | /* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | #define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | #define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | #define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | #define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | /* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | #define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | #define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | #define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | #define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ |
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0:01f31e923fe2 | 255 | #define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ |
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0:01f31e923fe2 | 256 | #define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */ |
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0:01f31e923fe2 | 259 | #define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 262 | #define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | #define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 268 | #define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | #define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ |
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0:01f31e923fe2 | 270 | #define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | #define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | #define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 280 | #define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 281 | #define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ |
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0:01f31e923fe2 | 282 | #define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 283 | #define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 284 | #define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | #define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | #define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | #define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | #define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | #define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | #define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | #define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | #define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | #define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | #define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 298 | #define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | #define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 301 | #define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | #define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | #define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | #define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ |
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0:01f31e923fe2 | 308 | |
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0:01f31e923fe2 | 309 | /*@}*/ |
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0:01f31e923fe2 | 310 | |
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0:01f31e923fe2 | 311 | |
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0:01f31e923fe2 | 312 | #endif /* _SAM3U_SUPC_COMPONENT_ */ |