Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/ssc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_SSC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_SSC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_SSC Synchronous Serial Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Ssc hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
Pawel Zarembski 0:01f31e923fe2 44 RoReg Reserved1[2];
Pawel Zarembski 0:01f31e923fe2 45 RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
Pawel Zarembski 0:01f31e923fe2 46 RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
Pawel Zarembski 0:01f31e923fe2 47 RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
Pawel Zarembski 0:01f31e923fe2 48 RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
Pawel Zarembski 0:01f31e923fe2 49 RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
Pawel Zarembski 0:01f31e923fe2 50 WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
Pawel Zarembski 0:01f31e923fe2 51 RoReg Reserved2[2];
Pawel Zarembski 0:01f31e923fe2 52 RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
Pawel Zarembski 0:01f31e923fe2 53 RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
Pawel Zarembski 0:01f31e923fe2 54 RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
Pawel Zarembski 0:01f31e923fe2 55 RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
Pawel Zarembski 0:01f31e923fe2 56 RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
Pawel Zarembski 0:01f31e923fe2 57 WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 58 WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 59 RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 60 RoReg Reserved3[37];
Pawel Zarembski 0:01f31e923fe2 61 RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 62 RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 63 } Ssc;
Pawel Zarembski 0:01f31e923fe2 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 65 /* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 66 #define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
Pawel Zarembski 0:01f31e923fe2 67 #define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
Pawel Zarembski 0:01f31e923fe2 68 #define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
Pawel Zarembski 0:01f31e923fe2 69 #define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
Pawel Zarembski 0:01f31e923fe2 70 #define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
Pawel Zarembski 0:01f31e923fe2 71 /* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 72 #define SSC_CMR_DIV_Pos 0
Pawel Zarembski 0:01f31e923fe2 73 #define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
Pawel Zarembski 0:01f31e923fe2 74 #define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
Pawel Zarembski 0:01f31e923fe2 75 /* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 76 #define SSC_RCMR_CKS_Pos 0
Pawel Zarembski 0:01f31e923fe2 77 #define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
Pawel Zarembski 0:01f31e923fe2 78 #define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
Pawel Zarembski 0:01f31e923fe2 79 #define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
Pawel Zarembski 0:01f31e923fe2 80 #define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
Pawel Zarembski 0:01f31e923fe2 81 #define SSC_RCMR_CKO_Pos 2
Pawel Zarembski 0:01f31e923fe2 82 #define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
Pawel Zarembski 0:01f31e923fe2 83 #define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
Pawel Zarembski 0:01f31e923fe2 84 #define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
Pawel Zarembski 0:01f31e923fe2 85 #define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
Pawel Zarembski 0:01f31e923fe2 86 #define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
Pawel Zarembski 0:01f31e923fe2 87 #define SSC_RCMR_CKG_Pos 6
Pawel Zarembski 0:01f31e923fe2 88 #define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
Pawel Zarembski 0:01f31e923fe2 89 #define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
Pawel Zarembski 0:01f31e923fe2 90 #define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
Pawel Zarembski 0:01f31e923fe2 91 #define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
Pawel Zarembski 0:01f31e923fe2 92 #define SSC_RCMR_START_Pos 8
Pawel Zarembski 0:01f31e923fe2 93 #define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
Pawel Zarembski 0:01f31e923fe2 94 #define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
Pawel Zarembski 0:01f31e923fe2 95 #define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
Pawel Zarembski 0:01f31e923fe2 96 #define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
Pawel Zarembski 0:01f31e923fe2 97 #define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
Pawel Zarembski 0:01f31e923fe2 98 #define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
Pawel Zarembski 0:01f31e923fe2 99 #define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
Pawel Zarembski 0:01f31e923fe2 100 #define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
Pawel Zarembski 0:01f31e923fe2 101 #define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
Pawel Zarembski 0:01f31e923fe2 102 #define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
Pawel Zarembski 0:01f31e923fe2 103 #define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
Pawel Zarembski 0:01f31e923fe2 104 #define SSC_RCMR_STTDLY_Pos 16
Pawel Zarembski 0:01f31e923fe2 105 #define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
Pawel Zarembski 0:01f31e923fe2 106 #define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
Pawel Zarembski 0:01f31e923fe2 107 #define SSC_RCMR_PERIOD_Pos 24
Pawel Zarembski 0:01f31e923fe2 108 #define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
Pawel Zarembski 0:01f31e923fe2 109 #define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
Pawel Zarembski 0:01f31e923fe2 110 /* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 111 #define SSC_RFMR_DATLEN_Pos 0
Pawel Zarembski 0:01f31e923fe2 112 #define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
Pawel Zarembski 0:01f31e923fe2 113 #define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
Pawel Zarembski 0:01f31e923fe2 114 #define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
Pawel Zarembski 0:01f31e923fe2 115 #define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
Pawel Zarembski 0:01f31e923fe2 116 #define SSC_RFMR_DATNB_Pos 8
Pawel Zarembski 0:01f31e923fe2 117 #define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
Pawel Zarembski 0:01f31e923fe2 118 #define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
Pawel Zarembski 0:01f31e923fe2 119 #define SSC_RFMR_FSLEN_Pos 16
Pawel Zarembski 0:01f31e923fe2 120 #define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
Pawel Zarembski 0:01f31e923fe2 121 #define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
Pawel Zarembski 0:01f31e923fe2 122 #define SSC_RFMR_FSOS_Pos 20
Pawel Zarembski 0:01f31e923fe2 123 #define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
Pawel Zarembski 0:01f31e923fe2 124 #define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
Pawel Zarembski 0:01f31e923fe2 125 #define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
Pawel Zarembski 0:01f31e923fe2 126 #define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
Pawel Zarembski 0:01f31e923fe2 127 #define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
Pawel Zarembski 0:01f31e923fe2 128 #define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
Pawel Zarembski 0:01f31e923fe2 129 #define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
Pawel Zarembski 0:01f31e923fe2 130 #define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
Pawel Zarembski 0:01f31e923fe2 131 #define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
Pawel Zarembski 0:01f31e923fe2 132 #define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
Pawel Zarembski 0:01f31e923fe2 133 #define SSC_RFMR_FSLEN_EXT_Pos 28
Pawel Zarembski 0:01f31e923fe2 134 #define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
Pawel Zarembski 0:01f31e923fe2 135 #define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
Pawel Zarembski 0:01f31e923fe2 136 /* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 137 #define SSC_TCMR_CKS_Pos 0
Pawel Zarembski 0:01f31e923fe2 138 #define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
Pawel Zarembski 0:01f31e923fe2 139 #define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
Pawel Zarembski 0:01f31e923fe2 140 #define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
Pawel Zarembski 0:01f31e923fe2 141 #define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
Pawel Zarembski 0:01f31e923fe2 142 #define SSC_TCMR_CKO_Pos 2
Pawel Zarembski 0:01f31e923fe2 143 #define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
Pawel Zarembski 0:01f31e923fe2 144 #define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
Pawel Zarembski 0:01f31e923fe2 145 #define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
Pawel Zarembski 0:01f31e923fe2 146 #define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
Pawel Zarembski 0:01f31e923fe2 147 #define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
Pawel Zarembski 0:01f31e923fe2 148 #define SSC_TCMR_CKG_Pos 6
Pawel Zarembski 0:01f31e923fe2 149 #define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
Pawel Zarembski 0:01f31e923fe2 150 #define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
Pawel Zarembski 0:01f31e923fe2 151 #define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
Pawel Zarembski 0:01f31e923fe2 152 #define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
Pawel Zarembski 0:01f31e923fe2 153 #define SSC_TCMR_START_Pos 8
Pawel Zarembski 0:01f31e923fe2 154 #define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
Pawel Zarembski 0:01f31e923fe2 155 #define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
Pawel Zarembski 0:01f31e923fe2 156 #define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
Pawel Zarembski 0:01f31e923fe2 157 #define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
Pawel Zarembski 0:01f31e923fe2 158 #define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
Pawel Zarembski 0:01f31e923fe2 159 #define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
Pawel Zarembski 0:01f31e923fe2 160 #define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
Pawel Zarembski 0:01f31e923fe2 161 #define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
Pawel Zarembski 0:01f31e923fe2 162 #define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
Pawel Zarembski 0:01f31e923fe2 163 #define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
Pawel Zarembski 0:01f31e923fe2 164 #define SSC_TCMR_STTDLY_Pos 16
Pawel Zarembski 0:01f31e923fe2 165 #define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
Pawel Zarembski 0:01f31e923fe2 166 #define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
Pawel Zarembski 0:01f31e923fe2 167 #define SSC_TCMR_PERIOD_Pos 24
Pawel Zarembski 0:01f31e923fe2 168 #define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
Pawel Zarembski 0:01f31e923fe2 169 #define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
Pawel Zarembski 0:01f31e923fe2 170 /* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 171 #define SSC_TFMR_DATLEN_Pos 0
Pawel Zarembski 0:01f31e923fe2 172 #define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
Pawel Zarembski 0:01f31e923fe2 173 #define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
Pawel Zarembski 0:01f31e923fe2 174 #define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
Pawel Zarembski 0:01f31e923fe2 175 #define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
Pawel Zarembski 0:01f31e923fe2 176 #define SSC_TFMR_DATNB_Pos 8
Pawel Zarembski 0:01f31e923fe2 177 #define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
Pawel Zarembski 0:01f31e923fe2 178 #define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
Pawel Zarembski 0:01f31e923fe2 179 #define SSC_TFMR_FSLEN_Pos 16
Pawel Zarembski 0:01f31e923fe2 180 #define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
Pawel Zarembski 0:01f31e923fe2 181 #define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
Pawel Zarembski 0:01f31e923fe2 182 #define SSC_TFMR_FSOS_Pos 20
Pawel Zarembski 0:01f31e923fe2 183 #define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
Pawel Zarembski 0:01f31e923fe2 184 #define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
Pawel Zarembski 0:01f31e923fe2 185 #define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
Pawel Zarembski 0:01f31e923fe2 186 #define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
Pawel Zarembski 0:01f31e923fe2 187 #define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
Pawel Zarembski 0:01f31e923fe2 188 #define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
Pawel Zarembski 0:01f31e923fe2 189 #define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
Pawel Zarembski 0:01f31e923fe2 190 #define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
Pawel Zarembski 0:01f31e923fe2 191 #define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
Pawel Zarembski 0:01f31e923fe2 192 #define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
Pawel Zarembski 0:01f31e923fe2 193 #define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
Pawel Zarembski 0:01f31e923fe2 194 #define SSC_TFMR_FSLEN_EXT_Pos 28
Pawel Zarembski 0:01f31e923fe2 195 #define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
Pawel Zarembski 0:01f31e923fe2 196 #define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
Pawel Zarembski 0:01f31e923fe2 197 /* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 198 #define SSC_RHR_RDAT_Pos 0
Pawel Zarembski 0:01f31e923fe2 199 #define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
Pawel Zarembski 0:01f31e923fe2 200 /* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 201 #define SSC_THR_TDAT_Pos 0
Pawel Zarembski 0:01f31e923fe2 202 #define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
Pawel Zarembski 0:01f31e923fe2 203 #define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
Pawel Zarembski 0:01f31e923fe2 204 /* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 205 #define SSC_RSHR_RSDAT_Pos 0
Pawel Zarembski 0:01f31e923fe2 206 #define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
Pawel Zarembski 0:01f31e923fe2 207 /* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
Pawel Zarembski 0:01f31e923fe2 208 #define SSC_TSHR_TSDAT_Pos 0
Pawel Zarembski 0:01f31e923fe2 209 #define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
Pawel Zarembski 0:01f31e923fe2 210 #define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
Pawel Zarembski 0:01f31e923fe2 211 /* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
Pawel Zarembski 0:01f31e923fe2 212 #define SSC_RC0R_CP0_Pos 0
Pawel Zarembski 0:01f31e923fe2 213 #define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
Pawel Zarembski 0:01f31e923fe2 214 #define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
Pawel Zarembski 0:01f31e923fe2 215 /* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
Pawel Zarembski 0:01f31e923fe2 216 #define SSC_RC1R_CP1_Pos 0
Pawel Zarembski 0:01f31e923fe2 217 #define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
Pawel Zarembski 0:01f31e923fe2 218 #define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
Pawel Zarembski 0:01f31e923fe2 219 /* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 220 #define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
Pawel Zarembski 0:01f31e923fe2 221 #define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
Pawel Zarembski 0:01f31e923fe2 222 #define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
Pawel Zarembski 0:01f31e923fe2 223 #define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
Pawel Zarembski 0:01f31e923fe2 224 #define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
Pawel Zarembski 0:01f31e923fe2 225 #define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
Pawel Zarembski 0:01f31e923fe2 226 #define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
Pawel Zarembski 0:01f31e923fe2 227 #define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
Pawel Zarembski 0:01f31e923fe2 228 #define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
Pawel Zarembski 0:01f31e923fe2 229 #define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
Pawel Zarembski 0:01f31e923fe2 230 /* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 231 #define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 232 #define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 233 #define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 234 #define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 235 #define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 236 #define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 237 #define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 238 #define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 239 /* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 240 #define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 241 #define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 242 #define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 243 #define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 244 #define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 245 #define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 246 #define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 247 #define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 248 /* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 249 #define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 250 #define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 251 #define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 252 #define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 253 #define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 254 #define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 255 #define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 256 #define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 257 /* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 258 #define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
Pawel Zarembski 0:01f31e923fe2 259 #define SSC_WPMR_WPKEY_Pos 8
Pawel Zarembski 0:01f31e923fe2 260 #define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
Pawel Zarembski 0:01f31e923fe2 261 #define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 262 /* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 263 #define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
Pawel Zarembski 0:01f31e923fe2 264 #define SSC_WPSR_WPVSRC_Pos 8
Pawel Zarembski 0:01f31e923fe2 265 #define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
Pawel Zarembski 0:01f31e923fe2 266
Pawel Zarembski 0:01f31e923fe2 267 /*@}*/
Pawel Zarembski 0:01f31e923fe2 268
Pawel Zarembski 0:01f31e923fe2 269
Pawel Zarembski 0:01f31e923fe2 270 #endif /* _SAM3U_SSC_COMPONENT_ */