Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/rtc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_RTC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_RTC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Real-time Clock */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_RTC Real-time Clock */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Rtc hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
Pawel Zarembski 0:01f31e923fe2 44 RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
Pawel Zarembski 0:01f31e923fe2 45 RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
Pawel Zarembski 0:01f31e923fe2 46 RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
Pawel Zarembski 0:01f31e923fe2 47 RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
Pawel Zarembski 0:01f31e923fe2 48 RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
Pawel Zarembski 0:01f31e923fe2 49 WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
Pawel Zarembski 0:01f31e923fe2 50 WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 51 WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 52 RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 53 RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
Pawel Zarembski 0:01f31e923fe2 54 RoReg Reserved1[45];
Pawel Zarembski 0:01f31e923fe2 55 RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 56 } Rtc;
Pawel Zarembski 0:01f31e923fe2 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 58 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 59 #define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
Pawel Zarembski 0:01f31e923fe2 60 #define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
Pawel Zarembski 0:01f31e923fe2 61 #define RTC_CR_TIMEVSEL_Pos 8
Pawel Zarembski 0:01f31e923fe2 62 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
Pawel Zarembski 0:01f31e923fe2 63 #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
Pawel Zarembski 0:01f31e923fe2 64 #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
Pawel Zarembski 0:01f31e923fe2 65 #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
Pawel Zarembski 0:01f31e923fe2 66 #define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
Pawel Zarembski 0:01f31e923fe2 67 #define RTC_CR_CALEVSEL_Pos 16
Pawel Zarembski 0:01f31e923fe2 68 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
Pawel Zarembski 0:01f31e923fe2 69 #define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
Pawel Zarembski 0:01f31e923fe2 70 #define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
Pawel Zarembski 0:01f31e923fe2 71 #define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
Pawel Zarembski 0:01f31e923fe2 72 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 73 #define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
Pawel Zarembski 0:01f31e923fe2 74 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
Pawel Zarembski 0:01f31e923fe2 75 #define RTC_TIMR_SEC_Pos 0
Pawel Zarembski 0:01f31e923fe2 76 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
Pawel Zarembski 0:01f31e923fe2 77 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
Pawel Zarembski 0:01f31e923fe2 78 #define RTC_TIMR_MIN_Pos 8
Pawel Zarembski 0:01f31e923fe2 79 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
Pawel Zarembski 0:01f31e923fe2 80 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
Pawel Zarembski 0:01f31e923fe2 81 #define RTC_TIMR_HOUR_Pos 16
Pawel Zarembski 0:01f31e923fe2 82 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
Pawel Zarembski 0:01f31e923fe2 83 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
Pawel Zarembski 0:01f31e923fe2 84 #define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
Pawel Zarembski 0:01f31e923fe2 85 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
Pawel Zarembski 0:01f31e923fe2 86 #define RTC_CALR_CENT_Pos 0
Pawel Zarembski 0:01f31e923fe2 87 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
Pawel Zarembski 0:01f31e923fe2 88 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
Pawel Zarembski 0:01f31e923fe2 89 #define RTC_CALR_YEAR_Pos 8
Pawel Zarembski 0:01f31e923fe2 90 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
Pawel Zarembski 0:01f31e923fe2 91 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
Pawel Zarembski 0:01f31e923fe2 92 #define RTC_CALR_MONTH_Pos 16
Pawel Zarembski 0:01f31e923fe2 93 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
Pawel Zarembski 0:01f31e923fe2 94 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
Pawel Zarembski 0:01f31e923fe2 95 #define RTC_CALR_DAY_Pos 21
Pawel Zarembski 0:01f31e923fe2 96 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
Pawel Zarembski 0:01f31e923fe2 97 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
Pawel Zarembski 0:01f31e923fe2 98 #define RTC_CALR_DATE_Pos 24
Pawel Zarembski 0:01f31e923fe2 99 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
Pawel Zarembski 0:01f31e923fe2 100 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
Pawel Zarembski 0:01f31e923fe2 101 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
Pawel Zarembski 0:01f31e923fe2 102 #define RTC_TIMALR_SEC_Pos 0
Pawel Zarembski 0:01f31e923fe2 103 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
Pawel Zarembski 0:01f31e923fe2 104 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
Pawel Zarembski 0:01f31e923fe2 105 #define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
Pawel Zarembski 0:01f31e923fe2 106 #define RTC_TIMALR_MIN_Pos 8
Pawel Zarembski 0:01f31e923fe2 107 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
Pawel Zarembski 0:01f31e923fe2 108 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
Pawel Zarembski 0:01f31e923fe2 109 #define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
Pawel Zarembski 0:01f31e923fe2 110 #define RTC_TIMALR_HOUR_Pos 16
Pawel Zarembski 0:01f31e923fe2 111 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
Pawel Zarembski 0:01f31e923fe2 112 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
Pawel Zarembski 0:01f31e923fe2 113 #define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
Pawel Zarembski 0:01f31e923fe2 114 #define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
Pawel Zarembski 0:01f31e923fe2 115 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
Pawel Zarembski 0:01f31e923fe2 116 #define RTC_CALALR_MONTH_Pos 16
Pawel Zarembski 0:01f31e923fe2 117 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
Pawel Zarembski 0:01f31e923fe2 118 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
Pawel Zarembski 0:01f31e923fe2 119 #define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
Pawel Zarembski 0:01f31e923fe2 120 #define RTC_CALALR_DATE_Pos 24
Pawel Zarembski 0:01f31e923fe2 121 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
Pawel Zarembski 0:01f31e923fe2 122 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
Pawel Zarembski 0:01f31e923fe2 123 #define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
Pawel Zarembski 0:01f31e923fe2 124 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 125 #define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
Pawel Zarembski 0:01f31e923fe2 126 #define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
Pawel Zarembski 0:01f31e923fe2 127 #define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
Pawel Zarembski 0:01f31e923fe2 128 #define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
Pawel Zarembski 0:01f31e923fe2 129 #define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
Pawel Zarembski 0:01f31e923fe2 130 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
Pawel Zarembski 0:01f31e923fe2 131 #define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
Pawel Zarembski 0:01f31e923fe2 132 #define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
Pawel Zarembski 0:01f31e923fe2 133 #define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
Pawel Zarembski 0:01f31e923fe2 134 #define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
Pawel Zarembski 0:01f31e923fe2 135 #define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
Pawel Zarembski 0:01f31e923fe2 136 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 137 #define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 138 #define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 139 #define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 140 #define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 141 #define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 142 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 143 #define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 144 #define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 145 #define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 146 #define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 147 #define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 148 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 149 #define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 150 #define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 151 #define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 152 #define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 153 #define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 154 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
Pawel Zarembski 0:01f31e923fe2 155 #define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
Pawel Zarembski 0:01f31e923fe2 156 #define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
Pawel Zarembski 0:01f31e923fe2 157 #define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
Pawel Zarembski 0:01f31e923fe2 158 #define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
Pawel Zarembski 0:01f31e923fe2 159 /* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 160 #define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
Pawel Zarembski 0:01f31e923fe2 161 #define RTC_WPMR_WPKEY_Pos 8
Pawel Zarembski 0:01f31e923fe2 162 #define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
Pawel Zarembski 0:01f31e923fe2 163 #define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 164
Pawel Zarembski 0:01f31e923fe2 165 /*@}*/
Pawel Zarembski 0:01f31e923fe2 166
Pawel Zarembski 0:01f31e923fe2 167
Pawel Zarembski 0:01f31e923fe2 168 #endif /* _SAM3U_RTC_COMPONENT_ */