Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/rstc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_RSTC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_RSTC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Reset Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_RSTC Reset Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Rstc hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
Pawel Zarembski 0:01f31e923fe2 44 RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
Pawel Zarembski 0:01f31e923fe2 45 } Rstc;
Pawel Zarembski 0:01f31e923fe2 46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 47 /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 48 #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
Pawel Zarembski 0:01f31e923fe2 49 #define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
Pawel Zarembski 0:01f31e923fe2 50 #define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
Pawel Zarembski 0:01f31e923fe2 51 #define RSTC_CR_KEY_Pos 24
Pawel Zarembski 0:01f31e923fe2 52 #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
Pawel Zarembski 0:01f31e923fe2 53 #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 54 /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 55 #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
Pawel Zarembski 0:01f31e923fe2 56 #define RSTC_SR_RSTTYP_Pos 8
Pawel Zarembski 0:01f31e923fe2 57 #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
Pawel Zarembski 0:01f31e923fe2 58 #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
Pawel Zarembski 0:01f31e923fe2 59 #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
Pawel Zarembski 0:01f31e923fe2 60 /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 61 #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
Pawel Zarembski 0:01f31e923fe2 62 #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 63 #define RSTC_MR_ERSTL_Pos 8
Pawel Zarembski 0:01f31e923fe2 64 #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
Pawel Zarembski 0:01f31e923fe2 65 #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
Pawel Zarembski 0:01f31e923fe2 66 #define RSTC_MR_KEY_Pos 24
Pawel Zarembski 0:01f31e923fe2 67 #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
Pawel Zarembski 0:01f31e923fe2 68 #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /*@}*/
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 #endif /* _SAM3U_RSTC_COMPONENT_ */