Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/pwm.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_PWM_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_PWM_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_PWM Pulse Width Modulation Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief PwmCh_num hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
Pawel Zarembski 0:01f31e923fe2 44 RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
Pawel Zarembski 0:01f31e923fe2 45 RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
Pawel Zarembski 0:01f31e923fe2 46 RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
Pawel Zarembski 0:01f31e923fe2 47 RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
Pawel Zarembski 0:01f31e923fe2 48 RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
Pawel Zarembski 0:01f31e923fe2 49 RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
Pawel Zarembski 0:01f31e923fe2 50 } PwmCh_num;
Pawel Zarembski 0:01f31e923fe2 51 /** \brief PwmCmp hardware registers */
Pawel Zarembski 0:01f31e923fe2 52 typedef struct {
Pawel Zarembski 0:01f31e923fe2 53 RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
Pawel Zarembski 0:01f31e923fe2 54 RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
Pawel Zarembski 0:01f31e923fe2 55 RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
Pawel Zarembski 0:01f31e923fe2 56 RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
Pawel Zarembski 0:01f31e923fe2 57 } PwmCmp;
Pawel Zarembski 0:01f31e923fe2 58 /** \brief Pwm hardware registers */
Pawel Zarembski 0:01f31e923fe2 59 #define PWMCMP_NUMBER 8
Pawel Zarembski 0:01f31e923fe2 60 #define PWMCH_NUM_NUMBER 4
Pawel Zarembski 0:01f31e923fe2 61 typedef struct {
Pawel Zarembski 0:01f31e923fe2 62 RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
Pawel Zarembski 0:01f31e923fe2 63 WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
Pawel Zarembski 0:01f31e923fe2 64 WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
Pawel Zarembski 0:01f31e923fe2 65 RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
Pawel Zarembski 0:01f31e923fe2 66 WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
Pawel Zarembski 0:01f31e923fe2 67 WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
Pawel Zarembski 0:01f31e923fe2 68 RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
Pawel Zarembski 0:01f31e923fe2 69 RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
Pawel Zarembski 0:01f31e923fe2 70 RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
Pawel Zarembski 0:01f31e923fe2 71 RoReg Reserved1[1];
Pawel Zarembski 0:01f31e923fe2 72 RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
Pawel Zarembski 0:01f31e923fe2 73 RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
Pawel Zarembski 0:01f31e923fe2 74 WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
Pawel Zarembski 0:01f31e923fe2 75 WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
Pawel Zarembski 0:01f31e923fe2 76 WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
Pawel Zarembski 0:01f31e923fe2 77 RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
Pawel Zarembski 0:01f31e923fe2 78 RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
Pawel Zarembski 0:01f31e923fe2 79 RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
Pawel Zarembski 0:01f31e923fe2 80 RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
Pawel Zarembski 0:01f31e923fe2 81 WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
Pawel Zarembski 0:01f31e923fe2 82 WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
Pawel Zarembski 0:01f31e923fe2 83 WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
Pawel Zarembski 0:01f31e923fe2 84 WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
Pawel Zarembski 0:01f31e923fe2 85 RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
Pawel Zarembski 0:01f31e923fe2 86 RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
Pawel Zarembski 0:01f31e923fe2 87 WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
Pawel Zarembski 0:01f31e923fe2 88 RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
Pawel Zarembski 0:01f31e923fe2 89 RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
Pawel Zarembski 0:01f31e923fe2 90 RoReg Reserved2[3];
Pawel Zarembski 0:01f31e923fe2 91 RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
Pawel Zarembski 0:01f31e923fe2 92 RoReg Reserved3[11];
Pawel Zarembski 0:01f31e923fe2 93 RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
Pawel Zarembski 0:01f31e923fe2 94 RoReg Reserved4[12];
Pawel Zarembski 0:01f31e923fe2 95 WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
Pawel Zarembski 0:01f31e923fe2 96 RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 97 RoReg Reserved5[7];
Pawel Zarembski 0:01f31e923fe2 98 RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 99 RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 100 RoReg Reserved6[2];
Pawel Zarembski 0:01f31e923fe2 101 RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 102 RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 103 WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 104 RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 105 RoReg Reserved7[2];
Pawel Zarembski 0:01f31e923fe2 106 PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
Pawel Zarembski 0:01f31e923fe2 107 RoReg Reserved8[20];
Pawel Zarembski 0:01f31e923fe2 108 PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
Pawel Zarembski 0:01f31e923fe2 109 } Pwm;
Pawel Zarembski 0:01f31e923fe2 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 111 /* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
Pawel Zarembski 0:01f31e923fe2 112 #define PWM_CLK_DIVA_Pos 0
Pawel Zarembski 0:01f31e923fe2 113 #define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
Pawel Zarembski 0:01f31e923fe2 114 #define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
Pawel Zarembski 0:01f31e923fe2 115 #define PWM_CLK_PREA_Pos 8
Pawel Zarembski 0:01f31e923fe2 116 #define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
Pawel Zarembski 0:01f31e923fe2 117 #define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
Pawel Zarembski 0:01f31e923fe2 118 #define PWM_CLK_DIVB_Pos 16
Pawel Zarembski 0:01f31e923fe2 119 #define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
Pawel Zarembski 0:01f31e923fe2 120 #define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
Pawel Zarembski 0:01f31e923fe2 121 #define PWM_CLK_PREB_Pos 24
Pawel Zarembski 0:01f31e923fe2 122 #define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
Pawel Zarembski 0:01f31e923fe2 123 #define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
Pawel Zarembski 0:01f31e923fe2 124 /* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 125 #define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
Pawel Zarembski 0:01f31e923fe2 126 #define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
Pawel Zarembski 0:01f31e923fe2 127 #define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
Pawel Zarembski 0:01f31e923fe2 128 #define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
Pawel Zarembski 0:01f31e923fe2 129 /* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 130 #define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
Pawel Zarembski 0:01f31e923fe2 131 #define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
Pawel Zarembski 0:01f31e923fe2 132 #define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
Pawel Zarembski 0:01f31e923fe2 133 #define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
Pawel Zarembski 0:01f31e923fe2 134 /* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 135 #define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
Pawel Zarembski 0:01f31e923fe2 136 #define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
Pawel Zarembski 0:01f31e923fe2 137 #define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
Pawel Zarembski 0:01f31e923fe2 138 #define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
Pawel Zarembski 0:01f31e923fe2 139 /* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
Pawel Zarembski 0:01f31e923fe2 140 #define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 141 #define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 142 #define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 143 #define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 144 #define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 145 #define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 146 #define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 147 #define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 148 /* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
Pawel Zarembski 0:01f31e923fe2 149 #define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 150 #define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 151 #define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 152 #define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 153 #define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 154 #define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 155 #define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 156 #define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 157 /* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
Pawel Zarembski 0:01f31e923fe2 158 #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 159 #define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 160 #define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 161 #define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 162 #define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 163 #define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 164 #define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 165 #define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 166 /* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
Pawel Zarembski 0:01f31e923fe2 167 #define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
Pawel Zarembski 0:01f31e923fe2 168 #define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
Pawel Zarembski 0:01f31e923fe2 169 #define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
Pawel Zarembski 0:01f31e923fe2 170 #define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
Pawel Zarembski 0:01f31e923fe2 171 #define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
Pawel Zarembski 0:01f31e923fe2 172 #define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
Pawel Zarembski 0:01f31e923fe2 173 #define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
Pawel Zarembski 0:01f31e923fe2 174 #define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
Pawel Zarembski 0:01f31e923fe2 175 /* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 176 #define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
Pawel Zarembski 0:01f31e923fe2 177 #define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
Pawel Zarembski 0:01f31e923fe2 178 #define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
Pawel Zarembski 0:01f31e923fe2 179 #define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
Pawel Zarembski 0:01f31e923fe2 180 #define PWM_SCM_UPDM_Pos 16
Pawel Zarembski 0:01f31e923fe2 181 #define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
Pawel Zarembski 0:01f31e923fe2 182 #define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
Pawel Zarembski 0:01f31e923fe2 183 #define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
Pawel Zarembski 0:01f31e923fe2 184 #define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
Pawel Zarembski 0:01f31e923fe2 185 #define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
Pawel Zarembski 0:01f31e923fe2 186 #define PWM_SCM_PTRCS_Pos 21
Pawel Zarembski 0:01f31e923fe2 187 #define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
Pawel Zarembski 0:01f31e923fe2 188 #define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
Pawel Zarembski 0:01f31e923fe2 189 /* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 190 #define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
Pawel Zarembski 0:01f31e923fe2 191 /* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
Pawel Zarembski 0:01f31e923fe2 192 #define PWM_SCUP_UPR_Pos 0
Pawel Zarembski 0:01f31e923fe2 193 #define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
Pawel Zarembski 0:01f31e923fe2 194 #define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
Pawel Zarembski 0:01f31e923fe2 195 #define PWM_SCUP_UPRCNT_Pos 4
Pawel Zarembski 0:01f31e923fe2 196 #define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
Pawel Zarembski 0:01f31e923fe2 197 #define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
Pawel Zarembski 0:01f31e923fe2 198 /* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 199 #define PWM_SCUPUPD_UPRUPD_Pos 0
Pawel Zarembski 0:01f31e923fe2 200 #define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
Pawel Zarembski 0:01f31e923fe2 201 #define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 202 /* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
Pawel Zarembski 0:01f31e923fe2 203 #define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 204 #define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 205 #define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 206 #define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 207 #define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 208 #define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 209 #define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 210 #define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 211 #define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 212 #define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 213 #define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 214 #define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 215 #define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 216 #define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 217 #define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 218 #define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 219 #define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 220 #define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 221 #define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 222 #define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 223 /* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
Pawel Zarembski 0:01f31e923fe2 224 #define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 225 #define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 226 #define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 227 #define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 228 #define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 229 #define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 230 #define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 231 #define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 232 #define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 233 #define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 234 #define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 235 #define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 236 #define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 237 #define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 238 #define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 239 #define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 240 #define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 241 #define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 242 #define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 243 #define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 244 /* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
Pawel Zarembski 0:01f31e923fe2 245 #define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 246 #define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 247 #define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 248 #define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 249 #define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 250 #define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 251 #define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 252 #define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 253 #define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 254 #define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 255 #define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 256 #define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 257 #define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 258 #define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 259 #define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 260 #define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 261 #define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 262 #define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 263 #define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 264 #define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 265 /* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
Pawel Zarembski 0:01f31e923fe2 266 #define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
Pawel Zarembski 0:01f31e923fe2 267 #define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
Pawel Zarembski 0:01f31e923fe2 268 #define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
Pawel Zarembski 0:01f31e923fe2 269 #define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
Pawel Zarembski 0:01f31e923fe2 270 #define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
Pawel Zarembski 0:01f31e923fe2 271 #define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
Pawel Zarembski 0:01f31e923fe2 272 #define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
Pawel Zarembski 0:01f31e923fe2 273 #define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
Pawel Zarembski 0:01f31e923fe2 274 #define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
Pawel Zarembski 0:01f31e923fe2 275 #define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
Pawel Zarembski 0:01f31e923fe2 276 #define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
Pawel Zarembski 0:01f31e923fe2 277 #define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
Pawel Zarembski 0:01f31e923fe2 278 #define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
Pawel Zarembski 0:01f31e923fe2 279 #define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
Pawel Zarembski 0:01f31e923fe2 280 #define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
Pawel Zarembski 0:01f31e923fe2 281 #define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
Pawel Zarembski 0:01f31e923fe2 282 #define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
Pawel Zarembski 0:01f31e923fe2 283 #define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
Pawel Zarembski 0:01f31e923fe2 284 #define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
Pawel Zarembski 0:01f31e923fe2 285 #define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
Pawel Zarembski 0:01f31e923fe2 286 /* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
Pawel Zarembski 0:01f31e923fe2 287 #define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 288 #define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 289 #define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 290 #define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 291 #define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 292 #define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 293 #define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 294 #define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 295 /* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
Pawel Zarembski 0:01f31e923fe2 296 #define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 297 #define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 298 #define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 299 #define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 300 #define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 301 #define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 302 #define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 303 #define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 304 /* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
Pawel Zarembski 0:01f31e923fe2 305 #define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 306 #define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 307 #define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 308 #define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 309 #define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 310 #define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 311 #define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 312 #define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 313 /* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
Pawel Zarembski 0:01f31e923fe2 314 #define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 315 #define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 316 #define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 317 #define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 318 #define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 319 #define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 320 #define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 321 #define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 322 /* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 323 #define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 324 #define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 325 #define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 326 #define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 327 #define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 328 #define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 329 #define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 330 #define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 331 /* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 332 #define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 333 #define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 334 #define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 335 #define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 336 #define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
Pawel Zarembski 0:01f31e923fe2 337 #define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
Pawel Zarembski 0:01f31e923fe2 338 #define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
Pawel Zarembski 0:01f31e923fe2 339 #define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
Pawel Zarembski 0:01f31e923fe2 340 /* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 341 #define PWM_FMR_FPOL_Pos 0
Pawel Zarembski 0:01f31e923fe2 342 #define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 343 #define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
Pawel Zarembski 0:01f31e923fe2 344 #define PWM_FMR_FMOD_Pos 8
Pawel Zarembski 0:01f31e923fe2 345 #define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 346 #define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
Pawel Zarembski 0:01f31e923fe2 347 #define PWM_FMR_FFIL_Pos 16
Pawel Zarembski 0:01f31e923fe2 348 #define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 349 #define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
Pawel Zarembski 0:01f31e923fe2 350 /* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 351 #define PWM_FSR_FIV_Pos 0
Pawel Zarembski 0:01f31e923fe2 352 #define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 353 #define PWM_FSR_FS_Pos 8
Pawel Zarembski 0:01f31e923fe2 354 #define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 355 /* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
Pawel Zarembski 0:01f31e923fe2 356 #define PWM_FCR_FCLR_Pos 0
Pawel Zarembski 0:01f31e923fe2 357 #define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 358 #define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
Pawel Zarembski 0:01f31e923fe2 359 /* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
Pawel Zarembski 0:01f31e923fe2 360 #define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
Pawel Zarembski 0:01f31e923fe2 361 #define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
Pawel Zarembski 0:01f31e923fe2 362 #define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
Pawel Zarembski 0:01f31e923fe2 363 #define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
Pawel Zarembski 0:01f31e923fe2 364 #define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
Pawel Zarembski 0:01f31e923fe2 365 #define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
Pawel Zarembski 0:01f31e923fe2 366 #define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
Pawel Zarembski 0:01f31e923fe2 367 #define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
Pawel Zarembski 0:01f31e923fe2 368 /* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 369 #define PWM_FPE_FPE0_Pos 0
Pawel Zarembski 0:01f31e923fe2 370 #define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 371 #define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
Pawel Zarembski 0:01f31e923fe2 372 #define PWM_FPE_FPE1_Pos 8
Pawel Zarembski 0:01f31e923fe2 373 #define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 374 #define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
Pawel Zarembski 0:01f31e923fe2 375 #define PWM_FPE_FPE2_Pos 16
Pawel Zarembski 0:01f31e923fe2 376 #define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 377 #define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
Pawel Zarembski 0:01f31e923fe2 378 #define PWM_FPE_FPE3_Pos 24
Pawel Zarembski 0:01f31e923fe2 379 #define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) */
Pawel Zarembski 0:01f31e923fe2 380 #define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
Pawel Zarembski 0:01f31e923fe2 381 /* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 382 #define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
Pawel Zarembski 0:01f31e923fe2 383 #define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
Pawel Zarembski 0:01f31e923fe2 384 #define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
Pawel Zarembski 0:01f31e923fe2 385 #define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
Pawel Zarembski 0:01f31e923fe2 386 #define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
Pawel Zarembski 0:01f31e923fe2 387 #define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
Pawel Zarembski 0:01f31e923fe2 388 #define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
Pawel Zarembski 0:01f31e923fe2 389 #define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
Pawel Zarembski 0:01f31e923fe2 390 /* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 391 #define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
Pawel Zarembski 0:01f31e923fe2 392 #define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
Pawel Zarembski 0:01f31e923fe2 393 #define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
Pawel Zarembski 0:01f31e923fe2 394 #define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
Pawel Zarembski 0:01f31e923fe2 395 /* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 396 #define PWM_WPCR_WPCMD_Pos 0
Pawel Zarembski 0:01f31e923fe2 397 #define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
Pawel Zarembski 0:01f31e923fe2 398 #define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
Pawel Zarembski 0:01f31e923fe2 399 #define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
Pawel Zarembski 0:01f31e923fe2 400 #define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
Pawel Zarembski 0:01f31e923fe2 401 #define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
Pawel Zarembski 0:01f31e923fe2 402 #define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
Pawel Zarembski 0:01f31e923fe2 403 #define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
Pawel Zarembski 0:01f31e923fe2 404 #define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
Pawel Zarembski 0:01f31e923fe2 405 #define PWM_WPCR_WPKEY_Pos 8
Pawel Zarembski 0:01f31e923fe2 406 #define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
Pawel Zarembski 0:01f31e923fe2 407 #define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 408 /* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 409 #define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 410 #define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 411 #define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 412 #define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 413 #define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 414 #define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
Pawel Zarembski 0:01f31e923fe2 415 #define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
Pawel Zarembski 0:01f31e923fe2 416 #define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 417 #define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 418 #define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 419 #define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 420 #define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 421 #define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
Pawel Zarembski 0:01f31e923fe2 422 #define PWM_WPSR_WPVSRC_Pos 16
Pawel Zarembski 0:01f31e923fe2 423 #define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
Pawel Zarembski 0:01f31e923fe2 424 /* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 425 #define PWM_TPR_TXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 426 #define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 427 #define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 428 /* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 429 #define PWM_TCR_TXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 430 #define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 431 #define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 432 /* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 433 #define PWM_TNPR_TXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 434 #define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
Pawel Zarembski 0:01f31e923fe2 435 #define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 436 /* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 437 #define PWM_TNCR_TXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 438 #define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
Pawel Zarembski 0:01f31e923fe2 439 #define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 440 /* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 441 #define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 442 #define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 443 #define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 444 #define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 445 /* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 446 #define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 447 #define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 448 /* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
Pawel Zarembski 0:01f31e923fe2 449 #define PWM_CMPV_CV_Pos 0
Pawel Zarembski 0:01f31e923fe2 450 #define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
Pawel Zarembski 0:01f31e923fe2 451 #define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
Pawel Zarembski 0:01f31e923fe2 452 #define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
Pawel Zarembski 0:01f31e923fe2 453 /* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 454 #define PWM_CMPVUPD_CVUPD_Pos 0
Pawel Zarembski 0:01f31e923fe2 455 #define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
Pawel Zarembski 0:01f31e923fe2 456 #define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 457 #define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
Pawel Zarembski 0:01f31e923fe2 458 /* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 459 #define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
Pawel Zarembski 0:01f31e923fe2 460 #define PWM_CMPM_CTR_Pos 4
Pawel Zarembski 0:01f31e923fe2 461 #define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
Pawel Zarembski 0:01f31e923fe2 462 #define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 463 #define PWM_CMPM_CPR_Pos 8
Pawel Zarembski 0:01f31e923fe2 464 #define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
Pawel Zarembski 0:01f31e923fe2 465 #define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
Pawel Zarembski 0:01f31e923fe2 466 #define PWM_CMPM_CPRCNT_Pos 12
Pawel Zarembski 0:01f31e923fe2 467 #define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
Pawel Zarembski 0:01f31e923fe2 468 #define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
Pawel Zarembski 0:01f31e923fe2 469 #define PWM_CMPM_CUPR_Pos 16
Pawel Zarembski 0:01f31e923fe2 470 #define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
Pawel Zarembski 0:01f31e923fe2 471 #define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
Pawel Zarembski 0:01f31e923fe2 472 #define PWM_CMPM_CUPRCNT_Pos 20
Pawel Zarembski 0:01f31e923fe2 473 #define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
Pawel Zarembski 0:01f31e923fe2 474 #define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
Pawel Zarembski 0:01f31e923fe2 475 /* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 476 #define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
Pawel Zarembski 0:01f31e923fe2 477 #define PWM_CMPMUPD_CTRUPD_Pos 4
Pawel Zarembski 0:01f31e923fe2 478 #define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
Pawel Zarembski 0:01f31e923fe2 479 #define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 480 #define PWM_CMPMUPD_CPRUPD_Pos 8
Pawel Zarembski 0:01f31e923fe2 481 #define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
Pawel Zarembski 0:01f31e923fe2 482 #define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 483 #define PWM_CMPMUPD_CUPRUPD_Pos 16
Pawel Zarembski 0:01f31e923fe2 484 #define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
Pawel Zarembski 0:01f31e923fe2 485 #define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 486 /* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 487 #define PWM_CMR_CPRE_Pos 0
Pawel Zarembski 0:01f31e923fe2 488 #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
Pawel Zarembski 0:01f31e923fe2 489 #define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
Pawel Zarembski 0:01f31e923fe2 490 #define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
Pawel Zarembski 0:01f31e923fe2 491 #define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
Pawel Zarembski 0:01f31e923fe2 492 #define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
Pawel Zarembski 0:01f31e923fe2 493 #define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
Pawel Zarembski 0:01f31e923fe2 494 #define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
Pawel Zarembski 0:01f31e923fe2 495 #define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
Pawel Zarembski 0:01f31e923fe2 496 #define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
Pawel Zarembski 0:01f31e923fe2 497 #define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
Pawel Zarembski 0:01f31e923fe2 498 #define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
Pawel Zarembski 0:01f31e923fe2 499 #define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
Pawel Zarembski 0:01f31e923fe2 500 #define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
Pawel Zarembski 0:01f31e923fe2 501 #define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
Pawel Zarembski 0:01f31e923fe2 502 #define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
Pawel Zarembski 0:01f31e923fe2 503 #define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
Pawel Zarembski 0:01f31e923fe2 504 #define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
Pawel Zarembski 0:01f31e923fe2 505 #define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
Pawel Zarembski 0:01f31e923fe2 506 #define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
Pawel Zarembski 0:01f31e923fe2 507 #define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
Pawel Zarembski 0:01f31e923fe2 508 /* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
Pawel Zarembski 0:01f31e923fe2 509 #define PWM_CDTY_CDTY_Pos 0
Pawel Zarembski 0:01f31e923fe2 510 #define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
Pawel Zarembski 0:01f31e923fe2 511 #define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
Pawel Zarembski 0:01f31e923fe2 512 /* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 513 #define PWM_CDTYUPD_CDTYUPD_Pos 0
Pawel Zarembski 0:01f31e923fe2 514 #define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
Pawel Zarembski 0:01f31e923fe2 515 #define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 516 /* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
Pawel Zarembski 0:01f31e923fe2 517 #define PWM_CPRD_CPRD_Pos 0
Pawel Zarembski 0:01f31e923fe2 518 #define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
Pawel Zarembski 0:01f31e923fe2 519 #define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
Pawel Zarembski 0:01f31e923fe2 520 /* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 521 #define PWM_CPRDUPD_CPRDUPD_Pos 0
Pawel Zarembski 0:01f31e923fe2 522 #define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
Pawel Zarembski 0:01f31e923fe2 523 #define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 524 /* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 525 #define PWM_CCNT_CNT_Pos 0
Pawel Zarembski 0:01f31e923fe2 526 #define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
Pawel Zarembski 0:01f31e923fe2 527 /* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
Pawel Zarembski 0:01f31e923fe2 528 #define PWM_DT_DTH_Pos 0
Pawel Zarembski 0:01f31e923fe2 529 #define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
Pawel Zarembski 0:01f31e923fe2 530 #define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
Pawel Zarembski 0:01f31e923fe2 531 #define PWM_DT_DTL_Pos 16
Pawel Zarembski 0:01f31e923fe2 532 #define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
Pawel Zarembski 0:01f31e923fe2 533 #define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
Pawel Zarembski 0:01f31e923fe2 534 /* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
Pawel Zarembski 0:01f31e923fe2 535 #define PWM_DTUPD_DTHUPD_Pos 0
Pawel Zarembski 0:01f31e923fe2 536 #define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
Pawel Zarembski 0:01f31e923fe2 537 #define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 538 #define PWM_DTUPD_DTLUPD_Pos 16
Pawel Zarembski 0:01f31e923fe2 539 #define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
Pawel Zarembski 0:01f31e923fe2 540 #define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
Pawel Zarembski 0:01f31e923fe2 541
Pawel Zarembski 0:01f31e923fe2 542 /*@}*/
Pawel Zarembski 0:01f31e923fe2 543
Pawel Zarembski 0:01f31e923fe2 544
Pawel Zarembski 0:01f31e923fe2 545 #endif /* _SAM3U_PWM_COMPONENT_ */