Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/pio.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 29 | |
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0:01f31e923fe2 | 30 | #ifndef _SAM3U_PIO_COMPONENT_ |
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0:01f31e923fe2 | 31 | #define _SAM3U_PIO_COMPONENT_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | /* ============================================================================= */ |
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0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ |
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0:01f31e923fe2 | 35 | /* ============================================================================= */ |
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0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_PIO Parallel Input/Output Controller */ |
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0:01f31e923fe2 | 37 | /*@{*/ |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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0:01f31e923fe2 | 40 | /** \brief Pio hardware registers */ |
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0:01f31e923fe2 | 41 | typedef struct { |
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0:01f31e923fe2 | 42 | WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ |
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0:01f31e923fe2 | 43 | WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ |
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0:01f31e923fe2 | 44 | RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ |
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0:01f31e923fe2 | 45 | RoReg Reserved1[1]; |
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0:01f31e923fe2 | 46 | WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ |
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0:01f31e923fe2 | 47 | WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ |
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0:01f31e923fe2 | 48 | RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ |
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0:01f31e923fe2 | 49 | RoReg Reserved2[1]; |
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0:01f31e923fe2 | 50 | WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ |
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0:01f31e923fe2 | 51 | WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ |
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0:01f31e923fe2 | 52 | RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ |
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0:01f31e923fe2 | 53 | RoReg Reserved3[1]; |
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0:01f31e923fe2 | 54 | WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ |
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0:01f31e923fe2 | 55 | WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ |
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0:01f31e923fe2 | 56 | RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ |
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0:01f31e923fe2 | 57 | RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ |
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0:01f31e923fe2 | 58 | WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ |
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0:01f31e923fe2 | 59 | WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ |
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0:01f31e923fe2 | 60 | RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ |
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0:01f31e923fe2 | 61 | RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ |
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0:01f31e923fe2 | 62 | WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ |
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0:01f31e923fe2 | 63 | WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ |
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0:01f31e923fe2 | 64 | RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ |
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0:01f31e923fe2 | 65 | RoReg Reserved4[1]; |
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0:01f31e923fe2 | 66 | WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ |
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0:01f31e923fe2 | 67 | WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ |
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0:01f31e923fe2 | 68 | RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ |
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0:01f31e923fe2 | 69 | RoReg Reserved5[1]; |
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0:01f31e923fe2 | 70 | RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */ |
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0:01f31e923fe2 | 71 | RoReg Reserved6[3]; |
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0:01f31e923fe2 | 72 | WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ |
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0:01f31e923fe2 | 73 | WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ |
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0:01f31e923fe2 | 74 | RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ |
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0:01f31e923fe2 | 75 | RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ |
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0:01f31e923fe2 | 76 | RoReg Reserved7[4]; |
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0:01f31e923fe2 | 77 | WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ |
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0:01f31e923fe2 | 78 | WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ |
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0:01f31e923fe2 | 79 | RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ |
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0:01f31e923fe2 | 80 | RoReg Reserved8[1]; |
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0:01f31e923fe2 | 81 | WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ |
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0:01f31e923fe2 | 82 | WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ |
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0:01f31e923fe2 | 83 | RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ |
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0:01f31e923fe2 | 84 | RoReg Reserved9[1]; |
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0:01f31e923fe2 | 85 | WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ |
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0:01f31e923fe2 | 86 | WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ |
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0:01f31e923fe2 | 87 | RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ |
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0:01f31e923fe2 | 88 | RoReg Reserved10[1]; |
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0:01f31e923fe2 | 89 | WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ |
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0:01f31e923fe2 | 90 | WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ |
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0:01f31e923fe2 | 91 | RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ |
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0:01f31e923fe2 | 92 | RoReg Reserved11[1]; |
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0:01f31e923fe2 | 93 | RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ |
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0:01f31e923fe2 | 94 | RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ |
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0:01f31e923fe2 | 95 | RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ |
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0:01f31e923fe2 | 96 | } Pio; |
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0:01f31e923fe2 | 97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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0:01f31e923fe2 | 98 | /* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ |
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0:01f31e923fe2 | 99 | #define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 100 | #define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 101 | #define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 102 | #define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 103 | #define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 104 | #define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 105 | #define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 106 | #define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 107 | #define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 108 | #define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 109 | #define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 110 | #define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 111 | #define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 112 | #define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 113 | #define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 114 | #define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 115 | #define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 116 | #define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 117 | #define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 118 | #define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 119 | #define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 120 | #define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 121 | #define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 122 | #define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 123 | #define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 124 | #define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 125 | #define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 126 | #define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 127 | #define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 128 | #define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 129 | #define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 130 | #define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ |
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0:01f31e923fe2 | 131 | /* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ |
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0:01f31e923fe2 | 132 | #define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 133 | #define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 134 | #define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 135 | #define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 136 | #define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 137 | #define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 138 | #define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 139 | #define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 140 | #define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 141 | #define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 142 | #define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 143 | #define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 144 | #define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 145 | #define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 146 | #define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 147 | #define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 148 | #define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 149 | #define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 150 | #define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 151 | #define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 152 | #define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 153 | #define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 154 | #define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 155 | #define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 156 | #define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 157 | #define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 158 | #define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 159 | #define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 160 | #define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 161 | #define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 162 | #define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 163 | #define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ |
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0:01f31e923fe2 | 164 | /* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ |
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0:01f31e923fe2 | 165 | #define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 166 | #define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 167 | #define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 168 | #define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 169 | #define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 170 | #define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 171 | #define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 172 | #define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 173 | #define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 174 | #define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 175 | #define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 176 | #define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 177 | #define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 178 | #define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 179 | #define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 180 | #define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 181 | #define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 182 | #define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 183 | #define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 184 | #define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 185 | #define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 186 | #define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 187 | #define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 188 | #define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 189 | #define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 190 | #define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 191 | #define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 192 | #define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 193 | #define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 194 | #define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 195 | #define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 196 | #define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ |
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0:01f31e923fe2 | 197 | /* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ |
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0:01f31e923fe2 | 198 | #define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 199 | #define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 200 | #define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 201 | #define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 202 | #define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 203 | #define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 204 | #define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 205 | #define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 206 | #define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 207 | #define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 208 | #define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 209 | #define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 210 | #define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 211 | #define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 212 | #define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 213 | #define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 214 | #define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 215 | #define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 216 | #define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 217 | #define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 218 | #define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 219 | #define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 220 | #define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 221 | #define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 222 | #define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 223 | #define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 224 | #define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 225 | #define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 226 | #define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 227 | #define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 228 | #define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 229 | #define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ |
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0:01f31e923fe2 | 230 | /* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ |
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0:01f31e923fe2 | 231 | #define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 232 | #define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 233 | #define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 234 | #define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 235 | #define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 236 | #define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 237 | #define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 238 | #define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 239 | #define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 240 | #define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 241 | #define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 242 | #define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 243 | #define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 244 | #define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 245 | #define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 246 | #define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 247 | #define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 248 | #define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 249 | #define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 250 | #define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 251 | #define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 252 | #define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 253 | #define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 254 | #define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 255 | #define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 256 | #define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 257 | #define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 258 | #define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 259 | #define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 260 | #define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 261 | #define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 262 | #define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ |
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0:01f31e923fe2 | 263 | /* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ |
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0:01f31e923fe2 | 264 | #define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 265 | #define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 266 | #define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 267 | #define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 268 | #define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 269 | #define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 270 | #define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 271 | #define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 272 | #define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 273 | #define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 274 | #define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 275 | #define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 276 | #define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 277 | #define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 278 | #define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 279 | #define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 280 | #define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 281 | #define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 282 | #define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 283 | #define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 284 | #define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 285 | #define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 286 | #define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 287 | #define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 288 | #define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 289 | #define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 290 | #define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 291 | #define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 292 | #define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 293 | #define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 294 | #define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 295 | #define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ |
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0:01f31e923fe2 | 296 | /* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ |
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0:01f31e923fe2 | 297 | #define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 298 | #define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 299 | #define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 300 | #define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 301 | #define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 302 | #define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 303 | #define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 304 | #define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 305 | #define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 306 | #define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 307 | #define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 308 | #define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 309 | #define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 310 | #define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 311 | #define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 312 | #define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 313 | #define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 314 | #define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 315 | #define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 316 | #define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 317 | #define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 318 | #define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 319 | #define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 320 | #define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 321 | #define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 322 | #define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 323 | #define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 324 | #define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 325 | #define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 326 | #define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 327 | #define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 328 | #define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ |
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0:01f31e923fe2 | 329 | /* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ |
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0:01f31e923fe2 | 330 | #define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 331 | #define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 332 | #define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 333 | #define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 334 | #define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 335 | #define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 336 | #define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 337 | #define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 338 | #define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 339 | #define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 340 | #define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 341 | #define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 342 | #define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 343 | #define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 344 | #define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 345 | #define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 346 | #define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 347 | #define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 348 | #define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 349 | #define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 350 | #define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 351 | #define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 352 | #define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 353 | #define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 354 | #define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 355 | #define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 356 | #define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 357 | #define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 358 | #define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 359 | #define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 360 | #define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 361 | #define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ |
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0:01f31e923fe2 | 362 | /* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ |
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0:01f31e923fe2 | 363 | #define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 364 | #define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 365 | #define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 366 | #define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 367 | #define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 368 | #define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 369 | #define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 370 | #define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 371 | #define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 372 | #define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 373 | #define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 374 | #define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 375 | #define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 376 | #define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 377 | #define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 378 | #define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 379 | #define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 380 | #define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 381 | #define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 382 | #define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 383 | #define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 384 | #define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 385 | #define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 386 | #define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 387 | #define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 388 | #define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 389 | #define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 390 | #define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 391 | #define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 392 | #define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 393 | #define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 394 | #define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ |
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0:01f31e923fe2 | 395 | /* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ |
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0:01f31e923fe2 | 396 | #define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 397 | #define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 398 | #define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 399 | #define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 400 | #define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 401 | #define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 402 | #define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 403 | #define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 404 | #define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 405 | #define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 406 | #define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 407 | #define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 408 | #define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 409 | #define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 410 | #define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 411 | #define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 412 | #define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 413 | #define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 414 | #define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 415 | #define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 416 | #define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 417 | #define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 418 | #define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 419 | #define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 420 | #define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 421 | #define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 422 | #define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 423 | #define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 424 | #define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 425 | #define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 426 | #define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 427 | #define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ |
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0:01f31e923fe2 | 428 | /* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ |
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0:01f31e923fe2 | 429 | #define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 430 | #define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 431 | #define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 432 | #define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 433 | #define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 434 | #define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 435 | #define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 436 | #define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 437 | #define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 438 | #define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 439 | #define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 440 | #define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 441 | #define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 442 | #define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 443 | #define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 444 | #define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 445 | #define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 446 | #define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 447 | #define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 448 | #define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 449 | #define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 450 | #define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 451 | #define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 452 | #define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 453 | #define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 454 | #define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 455 | #define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 456 | #define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 457 | #define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 458 | #define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 459 | #define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 460 | #define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ |
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0:01f31e923fe2 | 461 | /* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ |
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0:01f31e923fe2 | 462 | #define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 463 | #define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 464 | #define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 465 | #define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 466 | #define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 467 | #define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 468 | #define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 469 | #define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 470 | #define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 471 | #define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 472 | #define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 473 | #define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 474 | #define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 475 | #define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 476 | #define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 477 | #define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 478 | #define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 479 | #define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 480 | #define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 481 | #define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 482 | #define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 483 | #define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 484 | #define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 485 | #define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 486 | #define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 487 | #define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 488 | #define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 489 | #define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 490 | #define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 491 | #define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 492 | #define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 493 | #define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ |
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0:01f31e923fe2 | 494 | /* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ |
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0:01f31e923fe2 | 495 | #define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 496 | #define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 497 | #define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 498 | #define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 499 | #define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 500 | #define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 501 | #define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 502 | #define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 503 | #define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 504 | #define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 505 | #define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 506 | #define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 507 | #define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 508 | #define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 509 | #define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 510 | #define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 511 | #define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 512 | #define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 513 | #define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 514 | #define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 515 | #define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 516 | #define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 517 | #define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 518 | #define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 519 | #define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 520 | #define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 521 | #define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 522 | #define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 523 | #define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 524 | #define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 525 | #define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 526 | #define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ |
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0:01f31e923fe2 | 527 | /* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ |
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0:01f31e923fe2 | 528 | #define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 529 | #define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 530 | #define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 531 | #define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 532 | #define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 533 | #define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 534 | #define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 535 | #define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 536 | #define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 537 | #define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 538 | #define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 539 | #define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 540 | #define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 541 | #define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 542 | #define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 543 | #define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 544 | #define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 545 | #define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 546 | #define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 547 | #define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 548 | #define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 549 | #define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 550 | #define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 551 | #define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 552 | #define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 553 | #define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 554 | #define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 555 | #define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 556 | #define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 557 | #define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 558 | #define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 559 | #define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ |
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0:01f31e923fe2 | 560 | /* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ |
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0:01f31e923fe2 | 561 | #define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 562 | #define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 563 | #define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 564 | #define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 565 | #define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 566 | #define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 567 | #define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 568 | #define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 569 | #define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 570 | #define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 571 | #define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 572 | #define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 573 | #define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 574 | #define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 575 | #define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 576 | #define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 577 | #define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 578 | #define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 579 | #define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 580 | #define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 581 | #define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 582 | #define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 583 | #define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 584 | #define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 585 | #define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 586 | #define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 587 | #define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 588 | #define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 589 | #define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 590 | #define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 591 | #define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 592 | #define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ |
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0:01f31e923fe2 | 593 | /* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ |
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0:01f31e923fe2 | 594 | #define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 595 | #define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 596 | #define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 597 | #define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 598 | #define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 599 | #define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 600 | #define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 601 | #define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 602 | #define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 603 | #define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 604 | #define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 605 | #define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 606 | #define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 607 | #define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 608 | #define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 609 | #define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 610 | #define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 611 | #define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 612 | #define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 613 | #define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 614 | #define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 615 | #define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 616 | #define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 617 | #define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 618 | #define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 619 | #define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 620 | #define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 621 | #define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 622 | #define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 623 | #define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 624 | #define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 625 | #define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ |
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0:01f31e923fe2 | 626 | /* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ |
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0:01f31e923fe2 | 627 | #define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 628 | #define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 629 | #define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 630 | #define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 631 | #define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 632 | #define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 633 | #define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 634 | #define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 635 | #define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 636 | #define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 637 | #define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 638 | #define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 639 | #define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 640 | #define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 641 | #define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 642 | #define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 643 | #define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 644 | #define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 645 | #define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 646 | #define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 647 | #define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 648 | #define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 649 | #define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 650 | #define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 651 | #define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 652 | #define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 653 | #define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 654 | #define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 655 | #define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 656 | #define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 657 | #define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 658 | #define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ |
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0:01f31e923fe2 | 659 | /* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ |
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0:01f31e923fe2 | 660 | #define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 661 | #define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 662 | #define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 663 | #define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 664 | #define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 665 | #define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 666 | #define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 667 | #define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 668 | #define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 669 | #define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 670 | #define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 671 | #define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 672 | #define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 673 | #define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 674 | #define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 675 | #define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 676 | #define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 677 | #define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 678 | #define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 679 | #define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 680 | #define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 681 | #define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 682 | #define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 683 | #define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 684 | #define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 685 | #define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 686 | #define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 687 | #define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 688 | #define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 689 | #define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 690 | #define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 691 | #define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ |
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0:01f31e923fe2 | 692 | /* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ |
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0:01f31e923fe2 | 693 | #define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
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0:01f31e923fe2 | 694 | #define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
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0:01f31e923fe2 | 695 | #define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
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0:01f31e923fe2 | 696 | #define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 697 | #define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 698 | #define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 699 | #define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 700 | #define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 701 | #define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 702 | #define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 703 | #define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 704 | #define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 705 | #define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 706 | #define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 707 | #define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 708 | #define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 709 | #define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 710 | #define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 711 | #define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 712 | #define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 713 | #define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 714 | #define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 715 | #define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 716 | #define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 717 | #define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 718 | #define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 719 | #define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 720 | #define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 721 | #define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 722 | #define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 723 | #define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 724 | #define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 725 | /* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 726 | #define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 727 | #define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 728 | #define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 729 | #define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 730 | #define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 731 | #define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 732 | #define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 733 | #define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 734 | #define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 735 | #define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 736 | #define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 737 | #define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 738 | #define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 739 | #define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 740 | #define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 741 | #define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 742 | #define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 743 | #define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 744 | #define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 745 | #define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 746 | #define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 747 | #define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 748 | #define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 749 | #define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 750 | #define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 751 | #define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 752 | #define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 753 | #define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 754 | #define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 755 | #define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 756 | #define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 757 | #define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 758 | /* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 759 | #define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 760 | #define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 761 | #define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 762 | #define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 763 | #define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 764 | #define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 765 | #define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 766 | #define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 767 | #define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 768 | #define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 769 | #define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 770 | #define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 771 | #define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 772 | #define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 773 | #define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 774 | #define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 775 | #define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 776 | #define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 777 | #define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 778 | #define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 779 | #define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 780 | #define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 781 | #define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 782 | #define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 783 | #define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 784 | #define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 785 | #define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 786 | #define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 787 | #define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 788 | #define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 789 | #define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 790 | #define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 791 | /* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 792 | #define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 793 | #define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 794 | #define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 795 | #define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 796 | #define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 797 | #define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 798 | #define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 799 | #define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 800 | #define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 801 | #define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 802 | #define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 803 | #define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 804 | #define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 805 | #define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 806 | #define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 807 | #define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 808 | #define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 809 | #define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 810 | #define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 811 | #define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 812 | #define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 813 | #define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 814 | #define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 815 | #define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 816 | #define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 817 | #define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 818 | #define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 819 | #define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 820 | #define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 821 | #define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 822 | #define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 823 | #define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 824 | /* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 825 | #define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 826 | #define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 827 | #define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 828 | #define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 829 | #define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 830 | #define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 831 | #define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 832 | #define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 833 | #define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 834 | #define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 835 | #define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 836 | #define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 837 | #define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 838 | #define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 839 | #define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 840 | #define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 841 | #define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 842 | #define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 843 | #define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 844 | #define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 845 | #define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 846 | #define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 847 | #define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 848 | #define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 849 | #define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 850 | #define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 851 | #define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 852 | #define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 853 | #define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 854 | #define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 855 | #define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 856 | #define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 857 | /* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 858 | #define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 859 | #define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 860 | #define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 861 | #define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 862 | #define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 863 | #define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 864 | #define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 865 | #define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 866 | #define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 867 | #define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 868 | #define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 869 | #define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 870 | #define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 871 | #define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 872 | #define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 873 | #define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 874 | #define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 875 | #define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 876 | #define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 877 | #define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 878 | #define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 879 | #define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 880 | #define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 881 | #define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 882 | #define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 883 | #define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 884 | #define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 885 | #define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 886 | #define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 887 | #define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 888 | #define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 889 | #define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 890 | /* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 891 | #define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 892 | #define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 893 | #define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 894 | #define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 895 | #define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 896 | #define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 897 | #define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 898 | #define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 899 | #define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 900 | #define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 901 | #define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 902 | #define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 903 | #define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 904 | #define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 905 | #define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 906 | #define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 907 | #define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 908 | #define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 909 | #define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 910 | #define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 911 | #define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 912 | #define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 913 | #define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 914 | #define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 915 | #define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 916 | #define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 917 | #define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 918 | #define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 919 | #define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 920 | #define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 921 | #define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 922 | #define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 923 | /* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 924 | #define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 925 | #define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 926 | #define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 927 | #define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 928 | #define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 929 | #define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 930 | #define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 931 | #define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 932 | #define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 933 | #define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 934 | #define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 935 | #define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 936 | #define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 937 | #define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 938 | #define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 939 | #define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 940 | #define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 941 | #define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 942 | #define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 943 | #define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 944 | #define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 945 | #define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 946 | #define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 947 | #define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 948 | #define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 949 | #define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 950 | #define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 951 | #define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 952 | #define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 953 | #define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 954 | #define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 955 | #define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 956 | /* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 957 | #define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 958 | #define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 959 | #define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 960 | #define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 961 | #define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 962 | #define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 963 | #define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 964 | #define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 965 | #define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 966 | #define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 967 | #define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 968 | #define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 969 | #define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 970 | #define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 971 | #define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 972 | #define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 973 | #define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 974 | #define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 975 | #define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 976 | #define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 977 | #define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 978 | #define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 979 | #define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 980 | #define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 981 | #define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 982 | #define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 983 | #define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 984 | #define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 985 | #define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 986 | #define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 987 | #define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 988 | #define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 989 | /* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 990 | #define PIO_SCDR_DIV_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 991 | #define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ |
| Pawel Zarembski |
0:01f31e923fe2 | 992 | #define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 993 | /* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 994 | #define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 995 | #define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 996 | #define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 997 | #define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 998 | #define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 999 | #define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1000 | #define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1001 | #define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1002 | #define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1003 | #define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1004 | #define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1005 | #define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1006 | #define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1007 | #define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1008 | #define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1009 | #define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1010 | #define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1011 | #define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1012 | #define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1013 | #define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1014 | #define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1015 | #define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1016 | #define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1017 | #define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1018 | #define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1019 | #define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1020 | #define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1021 | #define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1022 | #define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1023 | #define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1024 | #define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1025 | #define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1026 | /* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1027 | #define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1028 | #define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1029 | #define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1030 | #define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1031 | #define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1032 | #define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1033 | #define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1034 | #define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1035 | #define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1036 | #define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1037 | #define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1038 | #define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1039 | #define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1040 | #define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1041 | #define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1042 | #define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1043 | #define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1044 | #define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1045 | #define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1046 | #define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1047 | #define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1048 | #define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1049 | #define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1050 | #define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1051 | #define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1052 | #define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1053 | #define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1054 | #define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1055 | #define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1056 | #define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1057 | #define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1058 | #define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1059 | /* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1060 | #define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1061 | #define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1062 | #define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1063 | #define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1064 | #define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1065 | #define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1066 | #define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1067 | #define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1068 | #define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1069 | #define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1070 | #define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1071 | #define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1072 | #define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1073 | #define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1074 | #define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1075 | #define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1076 | #define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1077 | #define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1078 | #define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1079 | #define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1080 | #define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1081 | #define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1082 | #define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1083 | #define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1084 | #define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1085 | #define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1086 | #define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1087 | #define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1088 | #define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1089 | #define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1090 | #define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1091 | #define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1092 | /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1093 | #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1094 | #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1095 | #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1096 | #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1097 | #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1098 | #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1099 | #define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1100 | #define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1101 | #define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1102 | #define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1103 | #define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1104 | #define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1105 | #define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1106 | #define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1107 | #define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1108 | #define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1109 | #define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1110 | #define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1111 | #define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1112 | #define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1113 | #define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1114 | #define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1115 | #define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1116 | #define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1117 | #define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1118 | #define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1119 | #define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1120 | #define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1121 | #define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1122 | #define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1123 | #define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1124 | #define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1125 | /* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1126 | #define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1127 | #define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1128 | #define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1129 | #define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1130 | #define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1131 | #define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1132 | #define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1133 | #define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1134 | #define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1135 | #define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1136 | #define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1137 | #define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1138 | #define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1139 | #define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1140 | #define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1141 | #define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1142 | #define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1143 | #define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1144 | #define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1145 | #define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1146 | #define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1147 | #define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1148 | #define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1149 | #define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1150 | #define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1151 | #define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1152 | #define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1153 | #define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1154 | #define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1155 | #define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1156 | #define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1157 | #define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1158 | /* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1159 | #define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1160 | #define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1161 | #define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1162 | #define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1163 | #define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1164 | #define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1165 | #define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1166 | #define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1167 | #define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1168 | #define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1169 | #define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1170 | #define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1171 | #define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1172 | #define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1173 | #define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1174 | #define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1175 | #define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1176 | #define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1177 | #define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1178 | #define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1179 | #define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1180 | #define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1181 | #define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1182 | #define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1183 | #define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1184 | #define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1185 | #define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1186 | #define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1187 | #define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1188 | #define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1189 | #define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1190 | #define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1191 | /* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1192 | #define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1193 | #define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1194 | #define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1195 | #define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1196 | #define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1197 | #define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1198 | #define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1199 | #define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1200 | #define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1201 | #define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1202 | #define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1203 | #define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1204 | #define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1205 | #define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1206 | #define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1207 | #define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1208 | #define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1209 | #define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1210 | #define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1211 | #define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1212 | #define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1213 | #define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1214 | #define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1215 | #define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1216 | #define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1217 | #define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1218 | #define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1219 | #define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1220 | #define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1221 | #define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1222 | #define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1223 | #define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1224 | /* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1225 | #define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1226 | #define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1227 | #define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1228 | #define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1229 | #define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1230 | #define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1231 | #define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1232 | #define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1233 | #define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1234 | #define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1235 | #define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1236 | #define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1237 | #define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1238 | #define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1239 | #define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1240 | #define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1241 | #define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1242 | #define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1243 | #define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1244 | #define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1245 | #define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1246 | #define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1247 | #define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1248 | #define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1249 | #define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1250 | #define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1251 | #define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1252 | #define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1253 | #define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1254 | #define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1255 | #define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1256 | #define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1257 | /* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1258 | #define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1259 | #define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1260 | #define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1261 | #define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1262 | #define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1263 | #define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1264 | #define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1265 | #define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1266 | #define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1267 | #define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1268 | #define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1269 | #define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1270 | #define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1271 | #define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1272 | #define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1273 | #define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1274 | #define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1275 | #define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1276 | #define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1277 | #define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1278 | #define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1279 | #define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1280 | #define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1281 | #define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1282 | #define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1283 | #define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1284 | #define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1285 | #define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1286 | #define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1287 | #define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1288 | #define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1289 | #define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1290 | /* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1291 | #define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1292 | #define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1293 | #define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1294 | #define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1295 | #define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1296 | #define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1297 | #define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1298 | #define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1299 | #define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1300 | #define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1301 | #define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1302 | #define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1303 | #define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1304 | #define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1305 | #define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1306 | #define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1307 | #define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1308 | #define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1309 | #define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1310 | #define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1311 | #define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1312 | #define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1313 | #define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1314 | #define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1315 | #define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1316 | #define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1317 | #define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1318 | #define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1319 | #define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1320 | #define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1321 | #define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1322 | #define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1323 | /* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1324 | #define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1325 | #define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1326 | #define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1327 | #define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1328 | #define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1329 | #define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1330 | #define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1331 | #define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1332 | #define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1333 | #define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1334 | #define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1335 | #define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1336 | #define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1337 | #define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1338 | #define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1339 | #define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1340 | #define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1341 | #define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1342 | #define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1343 | #define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1344 | #define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1345 | #define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1346 | #define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1347 | #define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1348 | #define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1349 | #define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1350 | #define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1351 | #define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1352 | #define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1353 | #define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1354 | #define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1355 | #define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1356 | /* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1357 | #define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1358 | #define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1359 | #define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1360 | #define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1361 | #define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1362 | #define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1363 | #define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1364 | #define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1365 | #define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1366 | #define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1367 | #define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1368 | #define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1369 | #define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1370 | #define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1371 | #define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1372 | #define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1373 | #define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1374 | #define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1375 | #define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1376 | #define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1377 | #define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1378 | #define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1379 | #define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1380 | #define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1381 | #define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1382 | #define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1383 | #define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1384 | #define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1385 | #define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1386 | #define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1387 | #define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1388 | #define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1389 | /* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1390 | #define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1391 | #define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1392 | #define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1393 | #define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1394 | #define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1395 | #define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1396 | #define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1397 | #define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1398 | #define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1399 | #define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1400 | #define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1401 | #define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1402 | #define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1403 | #define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1404 | #define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1405 | #define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1406 | #define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1407 | #define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1408 | #define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1409 | #define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1410 | #define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1411 | #define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1412 | #define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1413 | #define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1414 | #define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1415 | #define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1416 | #define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1417 | #define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1418 | #define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1419 | #define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1420 | #define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1421 | #define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1422 | /* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1423 | #define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1424 | #define PIO_WPMR_WPKEY_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 1425 | #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1426 | #define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 1427 | /* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1428 | #define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1429 | #define PIO_WPSR_WPVSRC_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 1430 | #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 1431 | |
| Pawel Zarembski |
0:01f31e923fe2 | 1432 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 1433 | |
| Pawel Zarembski |
0:01f31e923fe2 | 1434 | |
| Pawel Zarembski |
0:01f31e923fe2 | 1435 | #endif /* _SAM3U_PIO_COMPONENT_ */ |