Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/matrix.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
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0:01f31e923fe2 | 29 | |
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0:01f31e923fe2 | 30 | #ifndef _SAM3U_MATRIX_COMPONENT_ |
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0:01f31e923fe2 | 31 | #define _SAM3U_MATRIX_COMPONENT_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | /* ============================================================================= */ |
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0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ |
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0:01f31e923fe2 | 35 | /* ============================================================================= */ |
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0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_MATRIX AHB Bus Matrix */ |
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0:01f31e923fe2 | 37 | /*@{*/ |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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0:01f31e923fe2 | 40 | /** \brief Matrix hardware registers */ |
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0:01f31e923fe2 | 41 | typedef struct { |
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0:01f31e923fe2 | 42 | RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ |
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0:01f31e923fe2 | 43 | RoReg Reserved1[11]; |
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0:01f31e923fe2 | 44 | RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ |
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0:01f31e923fe2 | 45 | RoReg Reserved2[6]; |
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0:01f31e923fe2 | 46 | RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ |
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0:01f31e923fe2 | 47 | RoReg Reserved3[1]; |
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0:01f31e923fe2 | 48 | RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ |
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0:01f31e923fe2 | 49 | RoReg Reserved4[1]; |
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0:01f31e923fe2 | 50 | RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ |
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0:01f31e923fe2 | 51 | RoReg Reserved5[1]; |
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0:01f31e923fe2 | 52 | RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ |
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0:01f31e923fe2 | 53 | RoReg Reserved6[1]; |
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0:01f31e923fe2 | 54 | RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ |
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0:01f31e923fe2 | 55 | RoReg Reserved7[1]; |
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0:01f31e923fe2 | 56 | RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ |
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0:01f31e923fe2 | 57 | RoReg Reserved8[1]; |
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0:01f31e923fe2 | 58 | RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ |
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0:01f31e923fe2 | 59 | RoReg Reserved9[1]; |
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0:01f31e923fe2 | 60 | RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ |
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0:01f31e923fe2 | 61 | RoReg Reserved10[1]; |
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0:01f31e923fe2 | 62 | RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ |
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0:01f31e923fe2 | 63 | RoReg Reserved11[1]; |
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0:01f31e923fe2 | 64 | RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */ |
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0:01f31e923fe2 | 65 | RoReg Reserved12[1]; |
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0:01f31e923fe2 | 66 | RoReg Reserved13[12]; |
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0:01f31e923fe2 | 67 | RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ |
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0:01f31e923fe2 | 68 | RoReg Reserved14[56]; |
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0:01f31e923fe2 | 69 | RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ |
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0:01f31e923fe2 | 70 | RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ |
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0:01f31e923fe2 | 71 | } Matrix; |
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0:01f31e923fe2 | 72 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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0:01f31e923fe2 | 73 | /* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ |
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0:01f31e923fe2 | 74 | #define MATRIX_MCFG_ULBT_Pos 0 |
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0:01f31e923fe2 | 75 | #define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */ |
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0:01f31e923fe2 | 76 | #define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) |
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0:01f31e923fe2 | 77 | /* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ |
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0:01f31e923fe2 | 78 | #define MATRIX_SCFG_SLOT_CYCLE_Pos 0 |
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0:01f31e923fe2 | 79 | #define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */ |
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0:01f31e923fe2 | 80 | #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) |
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0:01f31e923fe2 | 81 | #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 |
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0:01f31e923fe2 | 82 | #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[10]) Default Master Type */ |
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0:01f31e923fe2 | 83 | #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) |
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0:01f31e923fe2 | 84 | #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 |
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0:01f31e923fe2 | 85 | #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */ |
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0:01f31e923fe2 | 86 | #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) |
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0:01f31e923fe2 | 87 | #define MATRIX_SCFG_ARBT_Pos 24 |
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0:01f31e923fe2 | 88 | #define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */ |
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0:01f31e923fe2 | 89 | #define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) |
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0:01f31e923fe2 | 90 | /* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ |
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0:01f31e923fe2 | 91 | #define MATRIX_PRAS0_M0PR_Pos 0 |
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0:01f31e923fe2 | 92 | #define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ |
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0:01f31e923fe2 | 93 | #define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) |
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0:01f31e923fe2 | 94 | #define MATRIX_PRAS0_M1PR_Pos 4 |
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0:01f31e923fe2 | 95 | #define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ |
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0:01f31e923fe2 | 96 | #define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) |
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0:01f31e923fe2 | 97 | #define MATRIX_PRAS0_M2PR_Pos 8 |
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0:01f31e923fe2 | 98 | #define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ |
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0:01f31e923fe2 | 99 | #define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) |
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0:01f31e923fe2 | 100 | #define MATRIX_PRAS0_M3PR_Pos 12 |
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0:01f31e923fe2 | 101 | #define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ |
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0:01f31e923fe2 | 102 | #define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) |
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0:01f31e923fe2 | 103 | #define MATRIX_PRAS0_M4PR_Pos 16 |
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0:01f31e923fe2 | 104 | #define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ |
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0:01f31e923fe2 | 105 | #define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) |
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0:01f31e923fe2 | 106 | /* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ |
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0:01f31e923fe2 | 107 | #define MATRIX_PRAS1_M0PR_Pos 0 |
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0:01f31e923fe2 | 108 | #define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ |
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0:01f31e923fe2 | 109 | #define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) |
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0:01f31e923fe2 | 110 | #define MATRIX_PRAS1_M1PR_Pos 4 |
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0:01f31e923fe2 | 111 | #define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ |
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0:01f31e923fe2 | 112 | #define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) |
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0:01f31e923fe2 | 113 | #define MATRIX_PRAS1_M2PR_Pos 8 |
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0:01f31e923fe2 | 114 | #define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ |
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0:01f31e923fe2 | 115 | #define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) |
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0:01f31e923fe2 | 116 | #define MATRIX_PRAS1_M3PR_Pos 12 |
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0:01f31e923fe2 | 117 | #define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ |
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0:01f31e923fe2 | 118 | #define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) |
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0:01f31e923fe2 | 119 | #define MATRIX_PRAS1_M4PR_Pos 16 |
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0:01f31e923fe2 | 120 | #define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ |
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0:01f31e923fe2 | 121 | #define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) |
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0:01f31e923fe2 | 122 | /* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ |
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0:01f31e923fe2 | 123 | #define MATRIX_PRAS2_M0PR_Pos 0 |
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0:01f31e923fe2 | 124 | #define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ |
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0:01f31e923fe2 | 125 | #define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) |
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0:01f31e923fe2 | 126 | #define MATRIX_PRAS2_M1PR_Pos 4 |
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0:01f31e923fe2 | 127 | #define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ |
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0:01f31e923fe2 | 128 | #define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) |
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0:01f31e923fe2 | 129 | #define MATRIX_PRAS2_M2PR_Pos 8 |
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0:01f31e923fe2 | 130 | #define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ |
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0:01f31e923fe2 | 131 | #define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) |
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0:01f31e923fe2 | 132 | #define MATRIX_PRAS2_M3PR_Pos 12 |
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0:01f31e923fe2 | 133 | #define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ |
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0:01f31e923fe2 | 134 | #define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) |
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0:01f31e923fe2 | 135 | #define MATRIX_PRAS2_M4PR_Pos 16 |
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0:01f31e923fe2 | 136 | #define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ |
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0:01f31e923fe2 | 137 | #define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) |
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0:01f31e923fe2 | 138 | /* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ |
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0:01f31e923fe2 | 139 | #define MATRIX_PRAS3_M0PR_Pos 0 |
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0:01f31e923fe2 | 140 | #define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ |
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0:01f31e923fe2 | 141 | #define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) |
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0:01f31e923fe2 | 142 | #define MATRIX_PRAS3_M1PR_Pos 4 |
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0:01f31e923fe2 | 143 | #define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ |
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0:01f31e923fe2 | 144 | #define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) |
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0:01f31e923fe2 | 145 | #define MATRIX_PRAS3_M2PR_Pos 8 |
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0:01f31e923fe2 | 146 | #define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ |
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0:01f31e923fe2 | 147 | #define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) |
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0:01f31e923fe2 | 148 | #define MATRIX_PRAS3_M3PR_Pos 12 |
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0:01f31e923fe2 | 149 | #define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ |
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0:01f31e923fe2 | 150 | #define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) |
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0:01f31e923fe2 | 151 | #define MATRIX_PRAS3_M4PR_Pos 16 |
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0:01f31e923fe2 | 152 | #define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ |
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0:01f31e923fe2 | 153 | #define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) |
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0:01f31e923fe2 | 154 | /* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ |
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0:01f31e923fe2 | 155 | #define MATRIX_PRAS4_M0PR_Pos 0 |
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0:01f31e923fe2 | 156 | #define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ |
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0:01f31e923fe2 | 157 | #define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) |
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0:01f31e923fe2 | 158 | #define MATRIX_PRAS4_M1PR_Pos 4 |
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0:01f31e923fe2 | 159 | #define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ |
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0:01f31e923fe2 | 160 | #define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) |
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0:01f31e923fe2 | 161 | #define MATRIX_PRAS4_M2PR_Pos 8 |
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0:01f31e923fe2 | 162 | #define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ |
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0:01f31e923fe2 | 163 | #define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) |
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0:01f31e923fe2 | 164 | #define MATRIX_PRAS4_M3PR_Pos 12 |
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0:01f31e923fe2 | 165 | #define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ |
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0:01f31e923fe2 | 166 | #define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) |
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0:01f31e923fe2 | 167 | #define MATRIX_PRAS4_M4PR_Pos 16 |
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0:01f31e923fe2 | 168 | #define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ |
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0:01f31e923fe2 | 169 | #define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) |
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0:01f31e923fe2 | 170 | /* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ |
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0:01f31e923fe2 | 171 | #define MATRIX_PRAS5_M0PR_Pos 0 |
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0:01f31e923fe2 | 172 | #define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ |
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0:01f31e923fe2 | 173 | #define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) |
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0:01f31e923fe2 | 174 | #define MATRIX_PRAS5_M1PR_Pos 4 |
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0:01f31e923fe2 | 175 | #define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ |
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0:01f31e923fe2 | 176 | #define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) |
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0:01f31e923fe2 | 177 | #define MATRIX_PRAS5_M2PR_Pos 8 |
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0:01f31e923fe2 | 178 | #define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ |
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0:01f31e923fe2 | 179 | #define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) |
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0:01f31e923fe2 | 180 | #define MATRIX_PRAS5_M3PR_Pos 12 |
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0:01f31e923fe2 | 181 | #define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ |
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0:01f31e923fe2 | 182 | #define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) |
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0:01f31e923fe2 | 183 | #define MATRIX_PRAS5_M4PR_Pos 16 |
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0:01f31e923fe2 | 184 | #define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ |
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0:01f31e923fe2 | 185 | #define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) |
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0:01f31e923fe2 | 186 | /* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ |
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0:01f31e923fe2 | 187 | #define MATRIX_PRAS6_M0PR_Pos 0 |
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0:01f31e923fe2 | 188 | #define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ |
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0:01f31e923fe2 | 189 | #define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos))) |
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0:01f31e923fe2 | 190 | #define MATRIX_PRAS6_M1PR_Pos 4 |
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0:01f31e923fe2 | 191 | #define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ |
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0:01f31e923fe2 | 192 | #define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos))) |
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0:01f31e923fe2 | 193 | #define MATRIX_PRAS6_M2PR_Pos 8 |
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0:01f31e923fe2 | 194 | #define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ |
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0:01f31e923fe2 | 195 | #define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos))) |
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0:01f31e923fe2 | 196 | #define MATRIX_PRAS6_M3PR_Pos 12 |
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0:01f31e923fe2 | 197 | #define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ |
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0:01f31e923fe2 | 198 | #define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos))) |
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0:01f31e923fe2 | 199 | #define MATRIX_PRAS6_M4PR_Pos 16 |
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0:01f31e923fe2 | 200 | #define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ |
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0:01f31e923fe2 | 201 | #define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos))) |
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0:01f31e923fe2 | 202 | /* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ |
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0:01f31e923fe2 | 203 | #define MATRIX_PRAS7_M0PR_Pos 0 |
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0:01f31e923fe2 | 204 | #define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ |
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0:01f31e923fe2 | 205 | #define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos))) |
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0:01f31e923fe2 | 206 | #define MATRIX_PRAS7_M1PR_Pos 4 |
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0:01f31e923fe2 | 207 | #define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ |
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0:01f31e923fe2 | 208 | #define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos))) |
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0:01f31e923fe2 | 209 | #define MATRIX_PRAS7_M2PR_Pos 8 |
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0:01f31e923fe2 | 210 | #define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ |
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0:01f31e923fe2 | 211 | #define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos))) |
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0:01f31e923fe2 | 212 | #define MATRIX_PRAS7_M3PR_Pos 12 |
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0:01f31e923fe2 | 213 | #define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ |
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0:01f31e923fe2 | 214 | #define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos))) |
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0:01f31e923fe2 | 215 | #define MATRIX_PRAS7_M4PR_Pos 16 |
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0:01f31e923fe2 | 216 | #define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ |
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0:01f31e923fe2 | 217 | #define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos))) |
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0:01f31e923fe2 | 218 | /* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ |
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0:01f31e923fe2 | 219 | #define MATRIX_PRAS8_M0PR_Pos 0 |
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0:01f31e923fe2 | 220 | #define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ |
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0:01f31e923fe2 | 221 | #define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos))) |
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0:01f31e923fe2 | 222 | #define MATRIX_PRAS8_M1PR_Pos 4 |
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0:01f31e923fe2 | 223 | #define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ |
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0:01f31e923fe2 | 224 | #define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos))) |
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0:01f31e923fe2 | 225 | #define MATRIX_PRAS8_M2PR_Pos 8 |
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0:01f31e923fe2 | 226 | #define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ |
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0:01f31e923fe2 | 227 | #define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos))) |
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0:01f31e923fe2 | 228 | #define MATRIX_PRAS8_M3PR_Pos 12 |
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0:01f31e923fe2 | 229 | #define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ |
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0:01f31e923fe2 | 230 | #define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos))) |
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0:01f31e923fe2 | 231 | #define MATRIX_PRAS8_M4PR_Pos 16 |
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0:01f31e923fe2 | 232 | #define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ |
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0:01f31e923fe2 | 233 | #define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos))) |
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0:01f31e923fe2 | 234 | /* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */ |
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0:01f31e923fe2 | 235 | #define MATRIX_PRAS9_M0PR_Pos 0 |
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0:01f31e923fe2 | 236 | #define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) /**< \brief (MATRIX_PRAS9) Master 0 Priority */ |
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0:01f31e923fe2 | 237 | #define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos))) |
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0:01f31e923fe2 | 238 | #define MATRIX_PRAS9_M1PR_Pos 4 |
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0:01f31e923fe2 | 239 | #define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) /**< \brief (MATRIX_PRAS9) Master 1 Priority */ |
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0:01f31e923fe2 | 240 | #define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos))) |
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0:01f31e923fe2 | 241 | #define MATRIX_PRAS9_M2PR_Pos 8 |
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0:01f31e923fe2 | 242 | #define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) /**< \brief (MATRIX_PRAS9) Master 2 Priority */ |
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0:01f31e923fe2 | 243 | #define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos))) |
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0:01f31e923fe2 | 244 | #define MATRIX_PRAS9_M3PR_Pos 12 |
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0:01f31e923fe2 | 245 | #define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) /**< \brief (MATRIX_PRAS9) Master 3 Priority */ |
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0:01f31e923fe2 | 246 | #define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos))) |
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0:01f31e923fe2 | 247 | #define MATRIX_PRAS9_M4PR_Pos 16 |
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0:01f31e923fe2 | 248 | #define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) /**< \brief (MATRIX_PRAS9) Master 4 Priority */ |
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0:01f31e923fe2 | 249 | #define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos))) |
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0:01f31e923fe2 | 250 | /* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ |
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0:01f31e923fe2 | 251 | #define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */ |
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0:01f31e923fe2 | 252 | #define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */ |
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0:01f31e923fe2 | 253 | #define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */ |
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0:01f31e923fe2 | 254 | #define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */ |
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0:01f31e923fe2 | 255 | #define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */ |
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0:01f31e923fe2 | 256 | /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ |
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0:01f31e923fe2 | 257 | #define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ |
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0:01f31e923fe2 | 258 | #define MATRIX_WPMR_WPKEY_Pos 8 |
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0:01f31e923fe2 | 259 | #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ |
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0:01f31e923fe2 | 260 | #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) |
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0:01f31e923fe2 | 261 | /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ |
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0:01f31e923fe2 | 262 | #define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ |
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0:01f31e923fe2 | 263 | #define MATRIX_WPSR_WPVSRC_Pos 8 |
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0:01f31e923fe2 | 264 | #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ |
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0:01f31e923fe2 | 265 | |
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0:01f31e923fe2 | 266 | /*@}*/ |
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0:01f31e923fe2 | 267 | |
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0:01f31e923fe2 | 268 | |
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0:01f31e923fe2 | 269 | #endif /* _SAM3U_MATRIX_COMPONENT_ */ |