Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/hsmci.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_HSMCI_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_HSMCI_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_HSMCI High Speed MultiMedia Card Interface */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief Hsmci hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | RoReg Reserved1[2]; |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | RoReg Reserved2[35]; |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | RoReg Reserved3[69]; |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | } Hsmci; |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | /* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | #define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | #define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | #define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | #define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | /* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | #define HSMCI_MR_CLKDIV_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | #define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | #define HSMCI_MR_PWSDIV_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | #define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define HSMCI_DTOR_DTOCYC_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | #define HSMCI_DTOR_DTOMUL_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | #define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | #define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | /* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define HSMCI_SDCR_SDCSEL_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define HSMCI_SDCR_SDCBUS_Pos 6 |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | #define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | /* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define HSMCI_ARGR_ARG_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | /* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define HSMCI_CMDR_CMDNB_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define HSMCI_CMDR_RSPTYP_Pos 6 |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define HSMCI_CMDR_SPCMD_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define HSMCI_CMDR_TRCMD_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define HSMCI_CMDR_TRTYP_Pos 19 |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define HSMCI_CMDR_IOSPCMD_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | /* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define HSMCI_BLKR_BCNT_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define HSMCI_BLKR_BLKLEN_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | /* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define HSMCI_CSTOR_CSTOCYC_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define HSMCI_CSTOR_CSTOMUL_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | /* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define HSMCI_RSPR_RSP_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | /* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define HSMCI_RDR_DATA_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | /* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define HSMCI_TDR_DATA_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | /* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | #define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | #define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | #define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | /* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | #define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | #define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | #define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | /* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | #define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | #define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | #define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | #define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | #define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | #define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | /* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | #define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | #define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | #define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | #define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | #define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | #define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | #define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | #define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | #define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | #define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | #define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | #define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | #define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | #define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | /* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define HSMCI_DMA_OFFSET_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | #define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | #define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | #define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */ |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | #define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | #define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */ |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | /* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | #define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | #define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | #define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 314 | #define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ |
| Pawel Zarembski |
0:01f31e923fe2 | 315 | /* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 316 | #define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 317 | #define HSMCI_WPMR_WP_KEY_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 318 | #define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ |
| Pawel Zarembski |
0:01f31e923fe2 | 319 | #define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 320 | /* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 321 | #define HSMCI_WPSR_WP_VS_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 322 | #define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 323 | #define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 324 | #define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 325 | #define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ |
| Pawel Zarembski |
0:01f31e923fe2 | 326 | #define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 327 | #define HSMCI_WPSR_WP_VSRC_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 328 | #define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ |
| Pawel Zarembski |
0:01f31e923fe2 | 329 | /* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 330 | #define HSMCI_FIFO_DATA_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 331 | #define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ |
| Pawel Zarembski |
0:01f31e923fe2 | 332 | #define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 333 | |
| Pawel Zarembski |
0:01f31e923fe2 | 334 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 335 | |
| Pawel Zarembski |
0:01f31e923fe2 | 336 | |
| Pawel Zarembski |
0:01f31e923fe2 | 337 | #endif /* _SAM3U_HSMCI_COMPONENT_ */ |