Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/efc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_EFC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_EFC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_EFC Embedded Flash Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Efc hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
Pawel Zarembski 0:01f31e923fe2 43 WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
Pawel Zarembski 0:01f31e923fe2 44 RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
Pawel Zarembski 0:01f31e923fe2 45 RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
Pawel Zarembski 0:01f31e923fe2 46 } Efc;
Pawel Zarembski 0:01f31e923fe2 47 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 48 /* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 49 #define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 50 #define EEFC_FMR_FWS_Pos 8
Pawel Zarembski 0:01f31e923fe2 51 #define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
Pawel Zarembski 0:01f31e923fe2 52 #define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
Pawel Zarembski 0:01f31e923fe2 53 #define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
Pawel Zarembski 0:01f31e923fe2 54 #define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
Pawel Zarembski 0:01f31e923fe2 55 /* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
Pawel Zarembski 0:01f31e923fe2 56 #define EEFC_FCR_FCMD_Pos 0
Pawel Zarembski 0:01f31e923fe2 57 #define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
Pawel Zarembski 0:01f31e923fe2 58 #define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */
Pawel Zarembski 0:01f31e923fe2 59 #define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */
Pawel Zarembski 0:01f31e923fe2 60 #define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */
Pawel Zarembski 0:01f31e923fe2 61 #define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */
Pawel Zarembski 0:01f31e923fe2 62 #define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */
Pawel Zarembski 0:01f31e923fe2 63 #define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */
Pawel Zarembski 0:01f31e923fe2 64 #define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */
Pawel Zarembski 0:01f31e923fe2 65 #define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */
Pawel Zarembski 0:01f31e923fe2 66 #define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */
Pawel Zarembski 0:01f31e923fe2 67 #define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */
Pawel Zarembski 0:01f31e923fe2 68 #define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */
Pawel Zarembski 0:01f31e923fe2 69 #define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */
Pawel Zarembski 0:01f31e923fe2 70 #define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */
Pawel Zarembski 0:01f31e923fe2 71 #define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */
Pawel Zarembski 0:01f31e923fe2 72 #define EEFC_FCR_FARG_Pos 8
Pawel Zarembski 0:01f31e923fe2 73 #define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
Pawel Zarembski 0:01f31e923fe2 74 #define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
Pawel Zarembski 0:01f31e923fe2 75 #define EEFC_FCR_FKEY_Pos 24
Pawel Zarembski 0:01f31e923fe2 76 #define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
Pawel Zarembski 0:01f31e923fe2 77 #define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
Pawel Zarembski 0:01f31e923fe2 78 /* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 79 #define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
Pawel Zarembski 0:01f31e923fe2 80 #define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
Pawel Zarembski 0:01f31e923fe2 81 #define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
Pawel Zarembski 0:01f31e923fe2 82 /* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
Pawel Zarembski 0:01f31e923fe2 83 #define EEFC_FRR_FVALUE_Pos 0
Pawel Zarembski 0:01f31e923fe2 84 #define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
Pawel Zarembski 0:01f31e923fe2 85
Pawel Zarembski 0:01f31e923fe2 86 /*@}*/
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88
Pawel Zarembski 0:01f31e923fe2 89 #endif /* _SAM3U_EFC_COMPONENT_ */