Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/dmac.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_DMAC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_DMAC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR DMA Controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_DMAC DMA Controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief DmacCh_num hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | RoReg Reserved1[4]; |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | } DmacCh_num; |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | /** \brief Dmac hardware registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #define DMACCH_NUM_NUMBER 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | RoReg Reserved1[1]; |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | RoReg Reserved2[2]; |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | RoReg Reserved3[66]; |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | } Dmac; |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | /* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | #define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | #define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | /* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | /* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | #define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | #define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | /* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | #define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | /* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | #define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | /* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | /* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | /* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | /* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | /* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | /* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | /* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [3:0] */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | /* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #define DMAC_SADDR_SADDR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | /* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define DMAC_DADDR_DADDR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | /* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define DMAC_DSCR_DSCR_Pos 2 |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | /* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define DMAC_CTRLA_BTSIZE_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define DMAC_CTRLA_SCSIZE_Pos 16 |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | #define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define DMAC_CTRLA_DCSIZE_Pos 20 |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define DMAC_CTRLA_SRC_WIDTH_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | #define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | #define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define DMAC_CTRLA_DST_WIDTH_Pos 28 |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | /* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define DMAC_CTRLB_FC_Pos 21 |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | #define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | #define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | #define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define DMAC_CTRLB_SRC_INCR_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define DMAC_CTRLB_DST_INCR_Pos 28 |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */ |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */ |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | #define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | /* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | #define DMAC_CFG_SRC_PER_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define DMAC_CFG_DST_PER_Pos 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | #define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | #define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | #define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | #define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | #define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */ |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | #define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | #define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | #define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | #define DMAC_CFG_AHB_PROT_Pos 24 |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | #define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | #define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | #define DMAC_CFG_FIFOCFG_Pos 28 |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | #define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | #define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | /* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | #define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define DMAC_WPMR_WPKEY_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | #define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | /* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | #define DMAC_WPSR_WPVSRC_Pos 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | #define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | #endif /* _SAM3U_DMAC_COMPONENT_ */ |