Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/adc12b.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_ADC12B_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_ADC12B_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter 12bits */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_ADC12B Analog-to-Digital Converter 12bits */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Adc12b hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 WoReg ADC12B_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg ADC12B_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */
Pawel Zarembski 0:01f31e923fe2 44 RoReg Reserved1[2];
Pawel Zarembski 0:01f31e923fe2 45 WoReg ADC12B_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
Pawel Zarembski 0:01f31e923fe2 46 WoReg ADC12B_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
Pawel Zarembski 0:01f31e923fe2 47 RoReg ADC12B_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
Pawel Zarembski 0:01f31e923fe2 48 RoReg ADC12B_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */
Pawel Zarembski 0:01f31e923fe2 49 RoReg ADC12B_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
Pawel Zarembski 0:01f31e923fe2 50 WoReg ADC12B_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 51 WoReg ADC12B_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 52 RoReg ADC12B_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 53 RoReg ADC12B_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
Pawel Zarembski 0:01f31e923fe2 54 RoReg Reserved2[5];
Pawel Zarembski 0:01f31e923fe2 55 RwReg ADC12B_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
Pawel Zarembski 0:01f31e923fe2 56 RwReg ADC12B_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
Pawel Zarembski 0:01f31e923fe2 57 RoReg Reserved3[37];
Pawel Zarembski 0:01f31e923fe2 58 RwReg ADC12B_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 59 RwReg ADC12B_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 60 RoReg Reserved4[2];
Pawel Zarembski 0:01f31e923fe2 61 RwReg ADC12B_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 62 RwReg ADC12B_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 63 RoReg Reserved5[2];
Pawel Zarembski 0:01f31e923fe2 64 WoReg ADC12B_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 65 RoReg ADC12B_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 66 } Adc12b;
Pawel Zarembski 0:01f31e923fe2 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 68 /* -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 69 #define ADC12B_CR_SWRST (0x1u << 0) /**< \brief (ADC12B_CR) Software Reset */
Pawel Zarembski 0:01f31e923fe2 70 #define ADC12B_CR_START (0x1u << 1) /**< \brief (ADC12B_CR) Start Conversion */
Pawel Zarembski 0:01f31e923fe2 71 /* -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 72 #define ADC12B_MR_TRGEN (0x1u << 0) /**< \brief (ADC12B_MR) Trigger Enable */
Pawel Zarembski 0:01f31e923fe2 73 #define ADC12B_MR_TRGSEL_Pos 1
Pawel Zarembski 0:01f31e923fe2 74 #define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */
Pawel Zarembski 0:01f31e923fe2 75 #define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))
Pawel Zarembski 0:01f31e923fe2 76 #define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */
Pawel Zarembski 0:01f31e923fe2 77 #define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */
Pawel Zarembski 0:01f31e923fe2 78 #define ADC12B_MR_PRESCAL_Pos 8
Pawel Zarembski 0:01f31e923fe2 79 #define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */
Pawel Zarembski 0:01f31e923fe2 80 #define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))
Pawel Zarembski 0:01f31e923fe2 81 #define ADC12B_MR_STARTUP_Pos 16
Pawel Zarembski 0:01f31e923fe2 82 #define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) /**< \brief (ADC12B_MR) Start Up Time */
Pawel Zarembski 0:01f31e923fe2 83 #define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))
Pawel Zarembski 0:01f31e923fe2 84 #define ADC12B_MR_SHTIM_Pos 24
Pawel Zarembski 0:01f31e923fe2 85 #define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) /**< \brief (ADC12B_MR) Sample & Hold Time */
Pawel Zarembski 0:01f31e923fe2 86 #define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))
Pawel Zarembski 0:01f31e923fe2 87 /* -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 88 #define ADC12B_CHER_CH0 (0x1u << 0) /**< \brief (ADC12B_CHER) Channel 0 Enable */
Pawel Zarembski 0:01f31e923fe2 89 #define ADC12B_CHER_CH1 (0x1u << 1) /**< \brief (ADC12B_CHER) Channel 1 Enable */
Pawel Zarembski 0:01f31e923fe2 90 #define ADC12B_CHER_CH2 (0x1u << 2) /**< \brief (ADC12B_CHER) Channel 2 Enable */
Pawel Zarembski 0:01f31e923fe2 91 #define ADC12B_CHER_CH3 (0x1u << 3) /**< \brief (ADC12B_CHER) Channel 3 Enable */
Pawel Zarembski 0:01f31e923fe2 92 #define ADC12B_CHER_CH4 (0x1u << 4) /**< \brief (ADC12B_CHER) Channel 4 Enable */
Pawel Zarembski 0:01f31e923fe2 93 #define ADC12B_CHER_CH5 (0x1u << 5) /**< \brief (ADC12B_CHER) Channel 5 Enable */
Pawel Zarembski 0:01f31e923fe2 94 #define ADC12B_CHER_CH6 (0x1u << 6) /**< \brief (ADC12B_CHER) Channel 6 Enable */
Pawel Zarembski 0:01f31e923fe2 95 #define ADC12B_CHER_CH7 (0x1u << 7) /**< \brief (ADC12B_CHER) Channel 7 Enable */
Pawel Zarembski 0:01f31e923fe2 96 /* -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 97 #define ADC12B_CHDR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 98 #define ADC12B_CHDR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 99 #define ADC12B_CHDR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 100 #define ADC12B_CHDR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 101 #define ADC12B_CHDR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 102 #define ADC12B_CHDR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 103 #define ADC12B_CHDR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 104 #define ADC12B_CHDR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHDR) */
Pawel Zarembski 0:01f31e923fe2 105 /* -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 106 #define ADC12B_CHSR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHSR) Channel 0 Status */
Pawel Zarembski 0:01f31e923fe2 107 #define ADC12B_CHSR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHSR) Channel 1 Status */
Pawel Zarembski 0:01f31e923fe2 108 #define ADC12B_CHSR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHSR) Channel 2 Status */
Pawel Zarembski 0:01f31e923fe2 109 #define ADC12B_CHSR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHSR) Channel 3 Status */
Pawel Zarembski 0:01f31e923fe2 110 #define ADC12B_CHSR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHSR) Channel 4 Status */
Pawel Zarembski 0:01f31e923fe2 111 #define ADC12B_CHSR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHSR) Channel 5 Status */
Pawel Zarembski 0:01f31e923fe2 112 #define ADC12B_CHSR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHSR) Channel 6 Status */
Pawel Zarembski 0:01f31e923fe2 113 #define ADC12B_CHSR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHSR) Channel 7 Status */
Pawel Zarembski 0:01f31e923fe2 114 /* -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 115 #define ADC12B_SR_EOC0 (0x1u << 0) /**< \brief (ADC12B_SR) End of Conversion 0 */
Pawel Zarembski 0:01f31e923fe2 116 #define ADC12B_SR_EOC1 (0x1u << 1) /**< \brief (ADC12B_SR) End of Conversion 1 */
Pawel Zarembski 0:01f31e923fe2 117 #define ADC12B_SR_EOC2 (0x1u << 2) /**< \brief (ADC12B_SR) End of Conversion 2 */
Pawel Zarembski 0:01f31e923fe2 118 #define ADC12B_SR_EOC3 (0x1u << 3) /**< \brief (ADC12B_SR) End of Conversion 3 */
Pawel Zarembski 0:01f31e923fe2 119 #define ADC12B_SR_EOC4 (0x1u << 4) /**< \brief (ADC12B_SR) End of Conversion 4 */
Pawel Zarembski 0:01f31e923fe2 120 #define ADC12B_SR_EOC5 (0x1u << 5) /**< \brief (ADC12B_SR) End of Conversion 5 */
Pawel Zarembski 0:01f31e923fe2 121 #define ADC12B_SR_EOC6 (0x1u << 6) /**< \brief (ADC12B_SR) End of Conversion 6 */
Pawel Zarembski 0:01f31e923fe2 122 #define ADC12B_SR_EOC7 (0x1u << 7) /**< \brief (ADC12B_SR) End of Conversion 7 */
Pawel Zarembski 0:01f31e923fe2 123 #define ADC12B_SR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_SR) Overrun Error 0 */
Pawel Zarembski 0:01f31e923fe2 124 #define ADC12B_SR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_SR) Overrun Error 1 */
Pawel Zarembski 0:01f31e923fe2 125 #define ADC12B_SR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_SR) Overrun Error 2 */
Pawel Zarembski 0:01f31e923fe2 126 #define ADC12B_SR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_SR) Overrun Error 3 */
Pawel Zarembski 0:01f31e923fe2 127 #define ADC12B_SR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_SR) Overrun Error 4 */
Pawel Zarembski 0:01f31e923fe2 128 #define ADC12B_SR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_SR) Overrun Error 5 */
Pawel Zarembski 0:01f31e923fe2 129 #define ADC12B_SR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_SR) Overrun Error 6 */
Pawel Zarembski 0:01f31e923fe2 130 #define ADC12B_SR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_SR) Overrun Error 7 */
Pawel Zarembski 0:01f31e923fe2 131 #define ADC12B_SR_DRDY (0x1u << 16) /**< \brief (ADC12B_SR) Data Ready */
Pawel Zarembski 0:01f31e923fe2 132 #define ADC12B_SR_GOVRE (0x1u << 17) /**< \brief (ADC12B_SR) General Overrun Error */
Pawel Zarembski 0:01f31e923fe2 133 #define ADC12B_SR_ENDRX (0x1u << 18) /**< \brief (ADC12B_SR) End of RX Buffer */
Pawel Zarembski 0:01f31e923fe2 134 #define ADC12B_SR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_SR) RX Buffer Full */
Pawel Zarembski 0:01f31e923fe2 135 /* -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
Pawel Zarembski 0:01f31e923fe2 136 #define ADC12B_LCDR_LDATA_Pos 0
Pawel Zarembski 0:01f31e923fe2 137 #define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) /**< \brief (ADC12B_LCDR) Last Data Converted */
Pawel Zarembski 0:01f31e923fe2 138 /* -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 139 #define ADC12B_IER_EOC0 (0x1u << 0) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 0 */
Pawel Zarembski 0:01f31e923fe2 140 #define ADC12B_IER_EOC1 (0x1u << 1) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 1 */
Pawel Zarembski 0:01f31e923fe2 141 #define ADC12B_IER_EOC2 (0x1u << 2) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 2 */
Pawel Zarembski 0:01f31e923fe2 142 #define ADC12B_IER_EOC3 (0x1u << 3) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 3 */
Pawel Zarembski 0:01f31e923fe2 143 #define ADC12B_IER_EOC4 (0x1u << 4) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 4 */
Pawel Zarembski 0:01f31e923fe2 144 #define ADC12B_IER_EOC5 (0x1u << 5) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 5 */
Pawel Zarembski 0:01f31e923fe2 145 #define ADC12B_IER_EOC6 (0x1u << 6) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 6 */
Pawel Zarembski 0:01f31e923fe2 146 #define ADC12B_IER_EOC7 (0x1u << 7) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 7 */
Pawel Zarembski 0:01f31e923fe2 147 #define ADC12B_IER_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 0 */
Pawel Zarembski 0:01f31e923fe2 148 #define ADC12B_IER_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 1 */
Pawel Zarembski 0:01f31e923fe2 149 #define ADC12B_IER_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 2 */
Pawel Zarembski 0:01f31e923fe2 150 #define ADC12B_IER_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 3 */
Pawel Zarembski 0:01f31e923fe2 151 #define ADC12B_IER_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 4 */
Pawel Zarembski 0:01f31e923fe2 152 #define ADC12B_IER_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 5 */
Pawel Zarembski 0:01f31e923fe2 153 #define ADC12B_IER_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 6 */
Pawel Zarembski 0:01f31e923fe2 154 #define ADC12B_IER_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 7 */
Pawel Zarembski 0:01f31e923fe2 155 #define ADC12B_IER_DRDY (0x1u << 16) /**< \brief (ADC12B_IER) Data Ready Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 156 #define ADC12B_IER_GOVRE (0x1u << 17) /**< \brief (ADC12B_IER) General Overrun Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 157 #define ADC12B_IER_ENDRX (0x1u << 18) /**< \brief (ADC12B_IER) End of Receive Buffer Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 158 #define ADC12B_IER_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IER) Receive Buffer Full Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 159 /* -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 160 #define ADC12B_IDR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 0 */
Pawel Zarembski 0:01f31e923fe2 161 #define ADC12B_IDR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 1 */
Pawel Zarembski 0:01f31e923fe2 162 #define ADC12B_IDR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 2 */
Pawel Zarembski 0:01f31e923fe2 163 #define ADC12B_IDR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 3 */
Pawel Zarembski 0:01f31e923fe2 164 #define ADC12B_IDR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 4 */
Pawel Zarembski 0:01f31e923fe2 165 #define ADC12B_IDR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 5 */
Pawel Zarembski 0:01f31e923fe2 166 #define ADC12B_IDR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 6 */
Pawel Zarembski 0:01f31e923fe2 167 #define ADC12B_IDR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 7 */
Pawel Zarembski 0:01f31e923fe2 168 #define ADC12B_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 0 */
Pawel Zarembski 0:01f31e923fe2 169 #define ADC12B_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 1 */
Pawel Zarembski 0:01f31e923fe2 170 #define ADC12B_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 2 */
Pawel Zarembski 0:01f31e923fe2 171 #define ADC12B_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 3 */
Pawel Zarembski 0:01f31e923fe2 172 #define ADC12B_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 4 */
Pawel Zarembski 0:01f31e923fe2 173 #define ADC12B_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 5 */
Pawel Zarembski 0:01f31e923fe2 174 #define ADC12B_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 6 */
Pawel Zarembski 0:01f31e923fe2 175 #define ADC12B_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 7 */
Pawel Zarembski 0:01f31e923fe2 176 #define ADC12B_IDR_DRDY (0x1u << 16) /**< \brief (ADC12B_IDR) Data Ready Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 177 #define ADC12B_IDR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IDR) General Overrun Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 178 #define ADC12B_IDR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IDR) End of Receive Buffer Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 179 #define ADC12B_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IDR) Receive Buffer Full Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 180 /* -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 181 #define ADC12B_IMR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 0 */
Pawel Zarembski 0:01f31e923fe2 182 #define ADC12B_IMR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 1 */
Pawel Zarembski 0:01f31e923fe2 183 #define ADC12B_IMR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 2 */
Pawel Zarembski 0:01f31e923fe2 184 #define ADC12B_IMR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 3 */
Pawel Zarembski 0:01f31e923fe2 185 #define ADC12B_IMR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 4 */
Pawel Zarembski 0:01f31e923fe2 186 #define ADC12B_IMR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 5 */
Pawel Zarembski 0:01f31e923fe2 187 #define ADC12B_IMR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 6 */
Pawel Zarembski 0:01f31e923fe2 188 #define ADC12B_IMR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 7 */
Pawel Zarembski 0:01f31e923fe2 189 #define ADC12B_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 0 */
Pawel Zarembski 0:01f31e923fe2 190 #define ADC12B_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 1 */
Pawel Zarembski 0:01f31e923fe2 191 #define ADC12B_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 2 */
Pawel Zarembski 0:01f31e923fe2 192 #define ADC12B_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 3 */
Pawel Zarembski 0:01f31e923fe2 193 #define ADC12B_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 4 */
Pawel Zarembski 0:01f31e923fe2 194 #define ADC12B_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 5 */
Pawel Zarembski 0:01f31e923fe2 195 #define ADC12B_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 6 */
Pawel Zarembski 0:01f31e923fe2 196 #define ADC12B_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 7 */
Pawel Zarembski 0:01f31e923fe2 197 #define ADC12B_IMR_DRDY (0x1u << 16) /**< \brief (ADC12B_IMR) Data Ready Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 198 #define ADC12B_IMR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IMR) General Overrun Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 199 #define ADC12B_IMR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IMR) End of Receive Buffer Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 200 #define ADC12B_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IMR) Receive Buffer Full Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 201 /* -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
Pawel Zarembski 0:01f31e923fe2 202 #define ADC12B_CDR_DATA_Pos 0
Pawel Zarembski 0:01f31e923fe2 203 #define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) /**< \brief (ADC12B_CDR[8]) Converted Data */
Pawel Zarembski 0:01f31e923fe2 204 /* -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 205 #define ADC12B_ACR_GAIN_Pos 0
Pawel Zarembski 0:01f31e923fe2 206 #define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) /**< \brief (ADC12B_ACR) Input Gain */
Pawel Zarembski 0:01f31e923fe2 207 #define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))
Pawel Zarembski 0:01f31e923fe2 208 #define ADC12B_ACR_IBCTL_Pos 8
Pawel Zarembski 0:01f31e923fe2 209 #define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) /**< \brief (ADC12B_ACR) Bias Current Control */
Pawel Zarembski 0:01f31e923fe2 210 #define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))
Pawel Zarembski 0:01f31e923fe2 211 #define ADC12B_ACR_DIFF (0x1u << 16) /**< \brief (ADC12B_ACR) Differential Mode */
Pawel Zarembski 0:01f31e923fe2 212 #define ADC12B_ACR_OFFSET (0x1u << 17) /**< \brief (ADC12B_ACR) Input OFFSET */
Pawel Zarembski 0:01f31e923fe2 213 /* -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 214 #define ADC12B_EMR_OFFMODES (0x1u << 0) /**< \brief (ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1 */
Pawel Zarembski 0:01f31e923fe2 215 #define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16
Pawel Zarembski 0:01f31e923fe2 216 #define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) /**< \brief (ADC12B_EMR) Startup Time */
Pawel Zarembski 0:01f31e923fe2 217 #define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))
Pawel Zarembski 0:01f31e923fe2 218 /* -------- ADC12B_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 219 #define ADC12B_RPR_RXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 220 #define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) /**< \brief (ADC12B_RPR) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 221 #define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 222 /* -------- ADC12B_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 223 #define ADC12B_RCR_RXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 224 #define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) /**< \brief (ADC12B_RCR) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 225 #define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 226 /* -------- ADC12B_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 227 #define ADC12B_RNPR_RXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 228 #define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) /**< \brief (ADC12B_RNPR) Receive Next Pointer */
Pawel Zarembski 0:01f31e923fe2 229 #define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 230 /* -------- ADC12B_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 231 #define ADC12B_RNCR_RXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 232 #define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) /**< \brief (ADC12B_RNCR) Receive Next Counter */
Pawel Zarembski 0:01f31e923fe2 233 #define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 234 /* -------- ADC12B_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 235 #define ADC12B_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTCR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 236 #define ADC12B_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC12B_PTCR) Receiver Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 237 #define ADC12B_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTCR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 238 #define ADC12B_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC12B_PTCR) Transmitter Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 239 /* -------- ADC12B_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 240 #define ADC12B_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTSR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 241 #define ADC12B_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTSR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 /*@}*/
Pawel Zarembski 0:01f31e923fe2 244
Pawel Zarembski 0:01f31e923fe2 245
Pawel Zarembski 0:01f31e923fe2 246 #endif /* _SAM3U_ADC12B_COMPONENT_ */