Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/component/adc.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_ADC_COMPONENT_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_ADC_COMPONENT_ |
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0:01f31e923fe2 | 32 | |
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0:01f31e923fe2 | 33 | /* ============================================================================= */ |
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0:01f31e923fe2 | 34 | /** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | /* ============================================================================= */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | /** \addtogroup SAM3U_ADC Analog-to-Digital Converter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | /*@{*/ |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | /** \brief Adc hardware registers */ |
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0:01f31e923fe2 | 41 | typedef struct { |
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0:01f31e923fe2 | 42 | WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ |
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0:01f31e923fe2 | 44 | RoReg Reserved1[2]; |
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0:01f31e923fe2 | 45 | WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ |
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0:01f31e923fe2 | 46 | WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ |
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0:01f31e923fe2 | 48 | RoReg ADC_SR; /**< \brief (Adc Offset: 0x1C) Status Register */ |
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0:01f31e923fe2 | 49 | RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ |
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0:01f31e923fe2 | 50 | WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ |
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0:01f31e923fe2 | 51 | WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ |
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0:01f31e923fe2 | 53 | RoReg ADC_CDR[8]; /**< \brief (Adc Offset: 0x30) Channel Data Register */ |
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0:01f31e923fe2 | 54 | RoReg Reserved2[44]; |
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0:01f31e923fe2 | 55 | RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ |
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0:01f31e923fe2 | 56 | RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ |
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0:01f31e923fe2 | 57 | RoReg Reserved3[2]; |
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0:01f31e923fe2 | 58 | RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ |
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0:01f31e923fe2 | 60 | RoReg Reserved4[2]; |
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0:01f31e923fe2 | 61 | WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ |
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0:01f31e923fe2 | 62 | RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ |
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0:01f31e923fe2 | 63 | } Adc; |
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0:01f31e923fe2 | 64 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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0:01f31e923fe2 | 65 | /* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | #define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | #define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ |
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0:01f31e923fe2 | 68 | /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ |
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0:01f31e923fe2 | 69 | #define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ |
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0:01f31e923fe2 | 70 | #define ADC_MR_TRGSEL_Pos 1 |
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0:01f31e923fe2 | 71 | #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos))) |
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0:01f31e923fe2 | 73 | #define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ |
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0:01f31e923fe2 | 74 | #define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ |
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0:01f31e923fe2 | 75 | #define ADC_MR_PRESCAL_Pos 8 |
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0:01f31e923fe2 | 76 | #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ |
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0:01f31e923fe2 | 77 | #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) |
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0:01f31e923fe2 | 78 | #define ADC_MR_STARTUP_Pos 16 |
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0:01f31e923fe2 | 79 | #define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ |
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0:01f31e923fe2 | 80 | #define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos))) |
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0:01f31e923fe2 | 81 | #define ADC_MR_SHTIM_Pos 24 |
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0:01f31e923fe2 | 82 | #define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) /**< \brief (ADC_MR) Sample & Hold Time */ |
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0:01f31e923fe2 | 83 | #define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | /* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ |
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0:01f31e923fe2 | 85 | #define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ |
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0:01f31e923fe2 | 86 | #define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ |
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0:01f31e923fe2 | 87 | #define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ |
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0:01f31e923fe2 | 88 | #define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ |
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0:01f31e923fe2 | 89 | #define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ |
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0:01f31e923fe2 | 90 | #define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ |
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0:01f31e923fe2 | 91 | #define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ |
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0:01f31e923fe2 | 92 | #define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ |
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0:01f31e923fe2 | 93 | /* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ |
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0:01f31e923fe2 | 94 | #define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ |
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0:01f31e923fe2 | 95 | #define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ |
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0:01f31e923fe2 | 96 | #define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ |
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0:01f31e923fe2 | 97 | #define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ |
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0:01f31e923fe2 | 98 | #define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ |
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0:01f31e923fe2 | 99 | #define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ |
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0:01f31e923fe2 | 100 | #define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ |
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0:01f31e923fe2 | 101 | #define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ |
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0:01f31e923fe2 | 102 | /* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ |
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0:01f31e923fe2 | 103 | #define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ |
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0:01f31e923fe2 | 104 | #define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ |
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0:01f31e923fe2 | 105 | #define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ |
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0:01f31e923fe2 | 106 | #define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ |
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0:01f31e923fe2 | 107 | #define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ |
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0:01f31e923fe2 | 108 | #define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ |
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0:01f31e923fe2 | 109 | #define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ |
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0:01f31e923fe2 | 110 | #define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ |
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0:01f31e923fe2 | 111 | /* -------- ADC_SR : (ADC Offset: 0x1C) Status Register -------- */ |
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0:01f31e923fe2 | 112 | #define ADC_SR_EOC0 (0x1u << 0) /**< \brief (ADC_SR) End of Conversion 0 */ |
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0:01f31e923fe2 | 113 | #define ADC_SR_EOC1 (0x1u << 1) /**< \brief (ADC_SR) End of Conversion 1 */ |
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0:01f31e923fe2 | 114 | #define ADC_SR_EOC2 (0x1u << 2) /**< \brief (ADC_SR) End of Conversion 2 */ |
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0:01f31e923fe2 | 115 | #define ADC_SR_EOC3 (0x1u << 3) /**< \brief (ADC_SR) End of Conversion 3 */ |
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0:01f31e923fe2 | 116 | #define ADC_SR_EOC4 (0x1u << 4) /**< \brief (ADC_SR) End of Conversion 4 */ |
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0:01f31e923fe2 | 117 | #define ADC_SR_EOC5 (0x1u << 5) /**< \brief (ADC_SR) End of Conversion 5 */ |
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0:01f31e923fe2 | 118 | #define ADC_SR_EOC6 (0x1u << 6) /**< \brief (ADC_SR) End of Conversion 6 */ |
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0:01f31e923fe2 | 119 | #define ADC_SR_EOC7 (0x1u << 7) /**< \brief (ADC_SR) End of Conversion 7 */ |
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0:01f31e923fe2 | 120 | #define ADC_SR_OVRE0 (0x1u << 8) /**< \brief (ADC_SR) Overrun Error 0 */ |
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0:01f31e923fe2 | 121 | #define ADC_SR_OVRE1 (0x1u << 9) /**< \brief (ADC_SR) Overrun Error 1 */ |
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0:01f31e923fe2 | 122 | #define ADC_SR_OVRE2 (0x1u << 10) /**< \brief (ADC_SR) Overrun Error 2 */ |
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0:01f31e923fe2 | 123 | #define ADC_SR_OVRE3 (0x1u << 11) /**< \brief (ADC_SR) Overrun Error 3 */ |
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0:01f31e923fe2 | 124 | #define ADC_SR_OVRE4 (0x1u << 12) /**< \brief (ADC_SR) Overrun Error 4 */ |
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0:01f31e923fe2 | 125 | #define ADC_SR_OVRE5 (0x1u << 13) /**< \brief (ADC_SR) Overrun Error 5 */ |
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0:01f31e923fe2 | 126 | #define ADC_SR_OVRE6 (0x1u << 14) /**< \brief (ADC_SR) Overrun Error 6 */ |
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0:01f31e923fe2 | 127 | #define ADC_SR_OVRE7 (0x1u << 15) /**< \brief (ADC_SR) Overrun Error 7 */ |
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0:01f31e923fe2 | 128 | #define ADC_SR_DRDY (0x1u << 16) /**< \brief (ADC_SR) Data Ready */ |
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0:01f31e923fe2 | 129 | #define ADC_SR_GOVRE (0x1u << 17) /**< \brief (ADC_SR) General Overrun Error */ |
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0:01f31e923fe2 | 130 | #define ADC_SR_ENDRX (0x1u << 18) /**< \brief (ADC_SR) End of RX Buffer */ |
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0:01f31e923fe2 | 131 | #define ADC_SR_RXBUFF (0x1u << 19) /**< \brief (ADC_SR) RX Buffer Full */ |
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0:01f31e923fe2 | 132 | /* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ |
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0:01f31e923fe2 | 133 | #define ADC_LCDR_LDATA_Pos 0 |
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0:01f31e923fe2 | 134 | #define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ |
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0:01f31e923fe2 | 135 | /* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ |
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0:01f31e923fe2 | 136 | #define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ |
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0:01f31e923fe2 | 137 | #define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ |
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0:01f31e923fe2 | 138 | #define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ |
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0:01f31e923fe2 | 139 | #define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ |
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0:01f31e923fe2 | 140 | #define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ |
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0:01f31e923fe2 | 141 | #define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ |
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0:01f31e923fe2 | 142 | #define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ |
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0:01f31e923fe2 | 143 | #define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ |
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0:01f31e923fe2 | 144 | #define ADC_IER_OVRE0 (0x1u << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */ |
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0:01f31e923fe2 | 145 | #define ADC_IER_OVRE1 (0x1u << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */ |
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0:01f31e923fe2 | 146 | #define ADC_IER_OVRE2 (0x1u << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */ |
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0:01f31e923fe2 | 147 | #define ADC_IER_OVRE3 (0x1u << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */ |
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0:01f31e923fe2 | 148 | #define ADC_IER_OVRE4 (0x1u << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */ |
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0:01f31e923fe2 | 149 | #define ADC_IER_OVRE5 (0x1u << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */ |
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0:01f31e923fe2 | 150 | #define ADC_IER_OVRE6 (0x1u << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */ |
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0:01f31e923fe2 | 151 | #define ADC_IER_OVRE7 (0x1u << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */ |
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0:01f31e923fe2 | 152 | #define ADC_IER_DRDY (0x1u << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ |
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0:01f31e923fe2 | 153 | #define ADC_IER_GOVRE (0x1u << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ |
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0:01f31e923fe2 | 154 | #define ADC_IER_ENDRX (0x1u << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ |
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0:01f31e923fe2 | 155 | #define ADC_IER_RXBUFF (0x1u << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ |
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0:01f31e923fe2 | 156 | /* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define ADC_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define ADC_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define ADC_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define ADC_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define ADC_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define ADC_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define ADC_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define ADC_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define ADC_IDR_DRDY (0x1u << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define ADC_IDR_GOVRE (0x1u << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define ADC_IDR_ENDRX (0x1u << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define ADC_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | /* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define ADC_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define ADC_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define ADC_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define ADC_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define ADC_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */ |
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0:01f31e923fe2 | 191 | #define ADC_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define ADC_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define ADC_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define ADC_IMR_DRDY (0x1u << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define ADC_IMR_GOVRE (0x1u << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #define ADC_IMR_ENDRX (0x1u << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | #define ADC_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | /* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | #define ADC_CDR_DATA_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | #define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define ADC_RPR_RXPTR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | /* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define ADC_RCR_RXCTR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | /* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define ADC_RNPR_RXNPTR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | /* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define ADC_RNCR_RXNCTR_Pos 0 |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | /* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | /* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ |
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0:01f31e923fe2 | 225 | |
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0:01f31e923fe2 | 226 | /*@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | |
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0:01f31e923fe2 | 228 | |
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0:01f31e923fe2 | 229 | #endif /* _SAM3U_ADC_COMPONENT_ */ |