Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file DAP_config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 26 /**
Pawel Zarembski 0:01f31e923fe2 27 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
Pawel Zarembski 0:01f31e923fe2 28 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 29 @{
Pawel Zarembski 0:01f31e923fe2 30 Provides definitions about:
Pawel Zarembski 0:01f31e923fe2 31 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 32 - Debug Unit communication packet size.
Pawel Zarembski 0:01f31e923fe2 33 - Debug Access Port communication mode (JTAG or SWD).
Pawel Zarembski 0:01f31e923fe2 34 - Optional information about a connected Target Device (for Evaluation Boards).
Pawel Zarembski 0:01f31e923fe2 35 */
Pawel Zarembski 0:01f31e923fe2 36
Pawel Zarembski 0:01f31e923fe2 37 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 40 /// This value is used to calculate the SWD/JTAG clock speed.
Pawel Zarembski 0:01f31e923fe2 41 #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 /// Number of processor cycles for I/O Port write operations.
Pawel Zarembski 0:01f31e923fe2 44 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
Pawel Zarembski 0:01f31e923fe2 45 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
Pawel Zarembski 0:01f31e923fe2 46 /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
Pawel Zarembski 0:01f31e923fe2 47 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
Pawel Zarembski 0:01f31e923fe2 48 /// requrired.
Pawel Zarembski 0:01f31e923fe2 49 #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
Pawel Zarembski 0:01f31e923fe2 50
Pawel Zarembski 0:01f31e923fe2 51 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 52 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 53 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /// Indicate that JTAG communication mode is available at the Debug Port.
Pawel Zarembski 0:01f31e923fe2 56 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 57 #define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 60 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
Pawel Zarembski 0:01f31e923fe2 61 #define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /// Default communication mode on the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 64 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
Pawel Zarembski 0:01f31e923fe2 65 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
Pawel Zarembski 0:01f31e923fe2 68 /// Used to initialize the default SWD/JTAG clock frequency.
Pawel Zarembski 0:01f31e923fe2 69 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
Pawel Zarembski 0:01f31e923fe2 70 #define DAP_DEFAULT_SWJ_CLOCK 2000000 ///< Default SWD/JTAG clock frequency in Hz.
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72 /// Maximum Package Size for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 73 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 74 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 75 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 /// Maximum Package Buffers for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 78 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 79 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
Pawel Zarembski 0:01f31e923fe2 80 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 81 #define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 82
Pawel Zarembski 0:01f31e923fe2 83 /// Indicate that UART Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 84 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 85 #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 /// Maximum SWO UART Baudrate
Pawel Zarembski 0:01f31e923fe2 88 #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 91 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 92 #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 /// SWO Trace Buffer Size.
Pawel Zarembski 0:01f31e923fe2 95 #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 /// SWO Streaming Trace.
Pawel Zarembski 0:01f31e923fe2 98 #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
Pawel Zarembski 0:01f31e923fe2 101 #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
Pawel Zarembski 0:01f31e923fe2 102
Pawel Zarembski 0:01f31e923fe2 103
Pawel Zarembski 0:01f31e923fe2 104 /// Debug Unit is connected to fixed Target Device.
Pawel Zarembski 0:01f31e923fe2 105 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
Pawel Zarembski 0:01f31e923fe2 106 /// known device. In this case a Device Vendor and Device Name string is stored which
Pawel Zarembski 0:01f31e923fe2 107 /// may be used by the debugger or IDE to configure device parameters.
Pawel Zarembski 0:01f31e923fe2 108 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 #if TARGET_DEVICE_FIXED
Pawel Zarembski 0:01f31e923fe2 111 #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
Pawel Zarembski 0:01f31e923fe2 112 #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
Pawel Zarembski 0:01f31e923fe2 113 #endif
Pawel Zarembski 0:01f31e923fe2 114
Pawel Zarembski 0:01f31e923fe2 115 ///@}
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 119 /**
Pawel Zarembski 0:01f31e923fe2 120 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
Pawel Zarembski 0:01f31e923fe2 121 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 122 @{
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
Pawel Zarembski 0:01f31e923fe2 125 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
Pawel Zarembski 0:01f31e923fe2 126 interface of a device. The following I/O Pins are provided:
Pawel Zarembski 0:01f31e923fe2 127
Pawel Zarembski 0:01f31e923fe2 128 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
Pawel Zarembski 0:01f31e923fe2 129 ---------------------------- | -------------------- | ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 130 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 131 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
Pawel Zarembski 0:01f31e923fe2 132 TDI: Test Data Input | | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 133 TDO: Test Data Output | | Input
Pawel Zarembski 0:01f31e923fe2 134 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 135 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 136
Pawel Zarembski 0:01f31e923fe2 137
Pawel Zarembski 0:01f31e923fe2 138 DAP Hardware I/O Pin Access Functions
Pawel Zarembski 0:01f31e923fe2 139 -------------------------------------
Pawel Zarembski 0:01f31e923fe2 140 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
Pawel Zarembski 0:01f31e923fe2 141 these I/O Pins.
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
Pawel Zarembski 0:01f31e923fe2 144 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
Pawel Zarembski 0:01f31e923fe2 145 peripherals that can independently write/read a single I/O pin without affecting any other pins
Pawel Zarembski 0:01f31e923fe2 146 of the same I/O port. The following SWDIO I/O Pin functions are provided:
Pawel Zarembski 0:01f31e923fe2 147 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 148 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 149 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 150 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 151 */
Pawel Zarembski 0:01f31e923fe2 152
Pawel Zarembski 0:01f31e923fe2 153
Pawel Zarembski 0:01f31e923fe2 154 // Configure DAP I/O pins ------------------------------
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Pawel Zarembski 0:01f31e923fe2 157 Configures the DAP Hardware I/O pins for JTAG mode:
Pawel Zarembski 0:01f31e923fe2 158 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
Pawel Zarembski 0:01f31e923fe2 159 - TDO to input mode.
Pawel Zarembski 0:01f31e923fe2 160 */
Pawel Zarembski 0:01f31e923fe2 161 __STATIC_INLINE void PORT_JTAG_SETUP(void) {}
Pawel Zarembski 0:01f31e923fe2 162
Pawel Zarembski 0:01f31e923fe2 163 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Pawel Zarembski 0:01f31e923fe2 164 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
Pawel Zarembski 0:01f31e923fe2 165 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
Pawel Zarembski 0:01f31e923fe2 166 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
Pawel Zarembski 0:01f31e923fe2 167 */
Pawel Zarembski 0:01f31e923fe2 168 __STATIC_INLINE void PORT_SWD_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 169 {
Pawel Zarembski 0:01f31e923fe2 170 PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive
Pawel Zarembski 0:01f31e923fe2 173 PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 174 PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH
Pawel Zarembski 0:01f31e923fe2 175 PIN_nRESET_PORT->PIO_OER = PIN_nRESET; // output
Pawel Zarembski 0:01f31e923fe2 176 PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive
Pawel Zarembski 0:01f31e923fe2 179 PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 180 PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH
Pawel Zarembski 0:01f31e923fe2 181 PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; // output
Pawel Zarembski 0:01f31e923fe2 182 PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control
Pawel Zarembski 0:01f31e923fe2 183
Pawel Zarembski 0:01f31e923fe2 184 PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive
Pawel Zarembski 0:01f31e923fe2 185 PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 186 PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH
Pawel Zarembski 0:01f31e923fe2 187 PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; // output
Pawel Zarembski 0:01f31e923fe2 188 PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control
Pawel Zarembski 0:01f31e923fe2 189 }
Pawel Zarembski 0:01f31e923fe2 190
Pawel Zarembski 0:01f31e923fe2 191 /** Disable JTAG/SWD I/O Pins.
Pawel Zarembski 0:01f31e923fe2 192 Disables the DAP Hardware I/O pins which configures:
Pawel Zarembski 0:01f31e923fe2 193 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
Pawel Zarembski 0:01f31e923fe2 194 */
Pawel Zarembski 0:01f31e923fe2 195 __STATIC_INLINE void PORT_OFF(void)
Pawel Zarembski 0:01f31e923fe2 196 {
Pawel Zarembski 0:01f31e923fe2 197 PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 198 PIN_nRESET_PORT->PIO_ODR = PIN_nRESET; // input
Pawel Zarembski 0:01f31e923fe2 199 PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control
Pawel Zarembski 0:01f31e923fe2 200
Pawel Zarembski 0:01f31e923fe2 201 PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 202 PIN_SWCLK_PORT->PIO_ODR = PIN_SWCLK; // input
Pawel Zarembski 0:01f31e923fe2 203 PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control
Pawel Zarembski 0:01f31e923fe2 204
Pawel Zarembski 0:01f31e923fe2 205 PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
Pawel Zarembski 0:01f31e923fe2 206 PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; // input
Pawel Zarembski 0:01f31e923fe2 207 PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control
Pawel Zarembski 0:01f31e923fe2 208
Pawel Zarembski 0:01f31e923fe2 209 }
Pawel Zarembski 0:01f31e923fe2 210
Pawel Zarembski 0:01f31e923fe2 211 // SWCLK/TCK I/O pin -------------------------------------
Pawel Zarembski 0:01f31e923fe2 212
Pawel Zarembski 0:01f31e923fe2 213 /** SWCLK/TCK I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 214 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 215 */
Pawel Zarembski 0:01f31e923fe2 216 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
Pawel Zarembski 0:01f31e923fe2 217 {
Pawel Zarembski 0:01f31e923fe2 218 return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 219 }
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 /** SWCLK/TCK I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 222 Set the SWCLK/TCK DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 223 */
Pawel Zarembski 0:01f31e923fe2 224 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
Pawel Zarembski 0:01f31e923fe2 225 {
Pawel Zarembski 0:01f31e923fe2 226 PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 227 }
Pawel Zarembski 0:01f31e923fe2 228
Pawel Zarembski 0:01f31e923fe2 229 /** SWCLK/TCK I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 230 Set the SWCLK/TCK DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 231 */
Pawel Zarembski 0:01f31e923fe2 232 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
Pawel Zarembski 0:01f31e923fe2 233 {
Pawel Zarembski 0:01f31e923fe2 234 PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 235 }
Pawel Zarembski 0:01f31e923fe2 236
Pawel Zarembski 0:01f31e923fe2 237 // SWDIO/TMS Pin I/O --------------------------------------
Pawel Zarembski 0:01f31e923fe2 238
Pawel Zarembski 0:01f31e923fe2 239 /** SWDIO/TMS I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 240 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 241 */
Pawel Zarembski 0:01f31e923fe2 242 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
Pawel Zarembski 0:01f31e923fe2 243 {
Pawel Zarembski 0:01f31e923fe2 244 return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 245 }
Pawel Zarembski 0:01f31e923fe2 246
Pawel Zarembski 0:01f31e923fe2 247 /** SWDIO/TMS I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 248 Set the SWDIO/TMS DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 249 */
Pawel Zarembski 0:01f31e923fe2 250 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
Pawel Zarembski 0:01f31e923fe2 251 {
Pawel Zarembski 0:01f31e923fe2 252 PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 253 }
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 /** SWDIO/TMS I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 256 Set the SWDIO/TMS DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 257 */
Pawel Zarembski 0:01f31e923fe2 258 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
Pawel Zarembski 0:01f31e923fe2 259 {
Pawel Zarembski 0:01f31e923fe2 260 PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 261 }
Pawel Zarembski 0:01f31e923fe2 262
Pawel Zarembski 0:01f31e923fe2 263 /** SWDIO I/O pin: Get Input (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 264 \return Current status of the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 265 */
Pawel Zarembski 0:01f31e923fe2 266 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
Pawel Zarembski 0:01f31e923fe2 267 {
Pawel Zarembski 0:01f31e923fe2 268 return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 269 }
Pawel Zarembski 0:01f31e923fe2 270
Pawel Zarembski 0:01f31e923fe2 271 /** SWDIO I/O pin: Set Output (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 272 \param bit Output value for the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 273 */
Pawel Zarembski 0:01f31e923fe2 274 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 275 {
Pawel Zarembski 0:01f31e923fe2 276 if (bit & 1) {
Pawel Zarembski 0:01f31e923fe2 277 PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 278
Pawel Zarembski 0:01f31e923fe2 279 } else {
Pawel Zarembski 0:01f31e923fe2 280 PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 281 }
Pawel Zarembski 0:01f31e923fe2 282 }
Pawel Zarembski 0:01f31e923fe2 283
Pawel Zarembski 0:01f31e923fe2 284 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 285 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
Pawel Zarembski 0:01f31e923fe2 286 called prior \ref PIN_SWDIO_OUT function calls.
Pawel Zarembski 0:01f31e923fe2 287 */
Pawel Zarembski 0:01f31e923fe2 288 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
Pawel Zarembski 0:01f31e923fe2 289 {
Pawel Zarembski 0:01f31e923fe2 290 PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 291 }
Pawel Zarembski 0:01f31e923fe2 292
Pawel Zarembski 0:01f31e923fe2 293 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 294 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
Pawel Zarembski 0:01f31e923fe2 295 called prior \ref PIN_SWDIO_IN function calls.
Pawel Zarembski 0:01f31e923fe2 296 */
Pawel Zarembski 0:01f31e923fe2 297 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
Pawel Zarembski 0:01f31e923fe2 298 {
Pawel Zarembski 0:01f31e923fe2 299 PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 300 }
Pawel Zarembski 0:01f31e923fe2 301
Pawel Zarembski 0:01f31e923fe2 302
Pawel Zarembski 0:01f31e923fe2 303 // TDI Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 304
Pawel Zarembski 0:01f31e923fe2 305 /** TDI I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 306 \return Current status of the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 307 */
Pawel Zarembski 0:01f31e923fe2 308 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
Pawel Zarembski 0:01f31e923fe2 309 {
Pawel Zarembski 0:01f31e923fe2 310 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 311 }
Pawel Zarembski 0:01f31e923fe2 312
Pawel Zarembski 0:01f31e923fe2 313 /** TDI I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 314 \param bit Output value for the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 315 */
Pawel Zarembski 0:01f31e923fe2 316 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 317 {
Pawel Zarembski 0:01f31e923fe2 318 ; // Not available
Pawel Zarembski 0:01f31e923fe2 319 }
Pawel Zarembski 0:01f31e923fe2 320
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 // TDO Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 323
Pawel Zarembski 0:01f31e923fe2 324 /** TDO I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 325 \return Current status of the TDO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 326 */
Pawel Zarembski 0:01f31e923fe2 327 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
Pawel Zarembski 0:01f31e923fe2 328 {
Pawel Zarembski 0:01f31e923fe2 329 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 330 }
Pawel Zarembski 0:01f31e923fe2 331
Pawel Zarembski 0:01f31e923fe2 332
Pawel Zarembski 0:01f31e923fe2 333 // nTRST Pin I/O -------------------------------------------
Pawel Zarembski 0:01f31e923fe2 334
Pawel Zarembski 0:01f31e923fe2 335 /** nTRST I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 336 \return Current status of the nTRST DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 337 */
Pawel Zarembski 0:01f31e923fe2 338 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
Pawel Zarembski 0:01f31e923fe2 339 {
Pawel Zarembski 0:01f31e923fe2 340 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 341 }
Pawel Zarembski 0:01f31e923fe2 342
Pawel Zarembski 0:01f31e923fe2 343 /** nTRST I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 344 \param bit JTAG TRST Test Reset pin status:
Pawel Zarembski 0:01f31e923fe2 345 - 0: issue a JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 346 - 1: release JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 347 */
Pawel Zarembski 0:01f31e923fe2 348 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 349 {
Pawel Zarembski 0:01f31e923fe2 350 ; // Not available
Pawel Zarembski 0:01f31e923fe2 351 }
Pawel Zarembski 0:01f31e923fe2 352
Pawel Zarembski 0:01f31e923fe2 353 // nRESET Pin I/O------------------------------------------
Pawel Zarembski 0:01f31e923fe2 354
Pawel Zarembski 0:01f31e923fe2 355 /** nRESET I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 356 \return Current status of the nRESET DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 357 */
Pawel Zarembski 0:01f31e923fe2 358 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
Pawel Zarembski 0:01f31e923fe2 359 {
Pawel Zarembski 0:01f31e923fe2 360 return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 361 }
Pawel Zarembski 0:01f31e923fe2 362
Pawel Zarembski 0:01f31e923fe2 363 /** nRESET I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 364 \param bit target device hardware reset pin status:
Pawel Zarembski 0:01f31e923fe2 365 - 0: issue a device hardware reset.
Pawel Zarembski 0:01f31e923fe2 366 - 1: release device hardware reset.
Pawel Zarembski 0:01f31e923fe2 367 */
Pawel Zarembski 0:01f31e923fe2 368 // TODO - sw specific implementation should be created
Pawel Zarembski 0:01f31e923fe2 369 #if defined (DBG_NRF51822AA)
Pawel Zarembski 0:01f31e923fe2 370 __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 371 {
Pawel Zarembski 0:01f31e923fe2 372 /**There is no reset pin on the nRF51822, so we need to use a reset routine:
Pawel Zarembski 0:01f31e923fe2 373 Enable reset through the RESET register in the POWER peripheral.
Pawel Zarembski 0:01f31e923fe2 374 Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 us.
Pawel Zarembski 0:01f31e923fe2 375 */
Pawel Zarembski 0:01f31e923fe2 376 if (bit & 1) {
Pawel Zarembski 0:01f31e923fe2 377 PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 378
Pawel Zarembski 0:01f31e923fe2 379 PIN_SWDIO_PORT->PIO_MDER = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 380 PIN_SWCLK_PORT->PIO_MDER = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 381 PIN_nRESET_PORT->PIO_MDER = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 382
Pawel Zarembski 0:01f31e923fe2 383 } else {
Pawel Zarembski 0:01f31e923fe2 384 swd_init_debug();
Pawel Zarembski 0:01f31e923fe2 385
Pawel Zarembski 0:01f31e923fe2 386 //Set POWER->RESET on NRF to 1
Pawel Zarembski 0:01f31e923fe2 387 if (!swd_write_ap(AP_TAR, 0x40000000 + 0x544)) {
Pawel Zarembski 0:01f31e923fe2 388 return;
Pawel Zarembski 0:01f31e923fe2 389 }
Pawel Zarembski 0:01f31e923fe2 390
Pawel Zarembski 0:01f31e923fe2 391 if (!swd_write_ap(AP_DRW, 1)) {
Pawel Zarembski 0:01f31e923fe2 392 return;
Pawel Zarembski 0:01f31e923fe2 393 }
Pawel Zarembski 0:01f31e923fe2 394
Pawel Zarembski 0:01f31e923fe2 395 //Hold RESET and SWCLK low for a minimum of 100us
Pawel Zarembski 0:01f31e923fe2 396 PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 397 PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 398 PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 399 PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 400 osDelay(1);
Pawel Zarembski 0:01f31e923fe2 401 }
Pawel Zarembski 0:01f31e923fe2 402 }
Pawel Zarembski 0:01f31e923fe2 403 #else
Pawel Zarembski 0:01f31e923fe2 404 __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 405 {
Pawel Zarembski 0:01f31e923fe2 406 if (bit & 1) {
Pawel Zarembski 0:01f31e923fe2 407 PIN_nRESET_PORT->PIO_SODR = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 408
Pawel Zarembski 0:01f31e923fe2 409 } else {
Pawel Zarembski 0:01f31e923fe2 410 PIN_nRESET_PORT->PIO_CODR = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 411 }
Pawel Zarembski 0:01f31e923fe2 412 }
Pawel Zarembski 0:01f31e923fe2 413 #endif
Pawel Zarembski 0:01f31e923fe2 414 ///@}
Pawel Zarembski 0:01f31e923fe2 415
Pawel Zarembski 0:01f31e923fe2 416
Pawel Zarembski 0:01f31e923fe2 417 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 418 /**
Pawel Zarembski 0:01f31e923fe2 419 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
Pawel Zarembski 0:01f31e923fe2 420 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 421 @{
Pawel Zarembski 0:01f31e923fe2 422
Pawel Zarembski 0:01f31e923fe2 423 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 424
Pawel Zarembski 0:01f31e923fe2 425 It is recommended to provide the following LEDs for status indication:
Pawel Zarembski 0:01f31e923fe2 426 - Connect LED: is active when the DAP hardware is connected to a debugger.
Pawel Zarembski 0:01f31e923fe2 427 - Running LED: is active when the debugger has put the target device into running state.
Pawel Zarembski 0:01f31e923fe2 428 */
Pawel Zarembski 0:01f31e923fe2 429
Pawel Zarembski 0:01f31e923fe2 430 /** Debug Unit: Set status of Connected LED.
Pawel Zarembski 0:01f31e923fe2 431 \param bit status of the Connect LED.
Pawel Zarembski 0:01f31e923fe2 432 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 433 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 434 */
Pawel Zarembski 0:01f31e923fe2 435 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 436 {
Pawel Zarembski 0:01f31e923fe2 437 }
Pawel Zarembski 0:01f31e923fe2 438
Pawel Zarembski 0:01f31e923fe2 439 /** Debug Unit: Set status Target Running LED.
Pawel Zarembski 0:01f31e923fe2 440 \param bit status of the Target Running LED.
Pawel Zarembski 0:01f31e923fe2 441 - 1: Target Running LED ON: program execution in target started.
Pawel Zarembski 0:01f31e923fe2 442 - 0: Target Running LED OFF: program execution in target stopped.
Pawel Zarembski 0:01f31e923fe2 443 */
Pawel Zarembski 0:01f31e923fe2 444 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 445 {
Pawel Zarembski 0:01f31e923fe2 446 ; // Not available
Pawel Zarembski 0:01f31e923fe2 447 }
Pawel Zarembski 0:01f31e923fe2 448
Pawel Zarembski 0:01f31e923fe2 449 ///@}
Pawel Zarembski 0:01f31e923fe2 450
Pawel Zarembski 0:01f31e923fe2 451
Pawel Zarembski 0:01f31e923fe2 452 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 453 /**
Pawel Zarembski 0:01f31e923fe2 454 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
Pawel Zarembski 0:01f31e923fe2 455 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 456 @{
Pawel Zarembski 0:01f31e923fe2 457 Access function for Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 458
Pawel Zarembski 0:01f31e923fe2 459 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
Pawel Zarembski 0:01f31e923fe2 460 default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
Pawel Zarembski 0:01f31e923fe2 461
Pawel Zarembski 0:01f31e923fe2 462 */
Pawel Zarembski 0:01f31e923fe2 463
Pawel Zarembski 0:01f31e923fe2 464 /** Get timestamp of Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 465 \return Current timestamp value.
Pawel Zarembski 0:01f31e923fe2 466 */
Pawel Zarembski 0:01f31e923fe2 467 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
Pawel Zarembski 0:01f31e923fe2 468 return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
Pawel Zarembski 0:01f31e923fe2 469 }
Pawel Zarembski 0:01f31e923fe2 470
Pawel Zarembski 0:01f31e923fe2 471 ///@}
Pawel Zarembski 0:01f31e923fe2 472
Pawel Zarembski 0:01f31e923fe2 473
Pawel Zarembski 0:01f31e923fe2 474 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 475 /**
Pawel Zarembski 0:01f31e923fe2 476 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
Pawel Zarembski 0:01f31e923fe2 477 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 478 @{
Pawel Zarembski 0:01f31e923fe2 479
Pawel Zarembski 0:01f31e923fe2 480 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
Pawel Zarembski 0:01f31e923fe2 481 */
Pawel Zarembski 0:01f31e923fe2 482
Pawel Zarembski 0:01f31e923fe2 483 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
Pawel Zarembski 0:01f31e923fe2 484 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Pawel Zarembski 0:01f31e923fe2 485 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
Pawel Zarembski 0:01f31e923fe2 486 - I/O clock system enabled.
Pawel Zarembski 0:01f31e923fe2 487 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
Pawel Zarembski 0:01f31e923fe2 488 - for nTRST, nRESET a weak pull-up (if available) is enabled.
Pawel Zarembski 0:01f31e923fe2 489 - LED output pins are enabled and LEDs are turned off.
Pawel Zarembski 0:01f31e923fe2 490 */
Pawel Zarembski 0:01f31e923fe2 491 __STATIC_INLINE void DAP_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 492 {
Pawel Zarembski 0:01f31e923fe2 493 }
Pawel Zarembski 0:01f31e923fe2 494
Pawel Zarembski 0:01f31e923fe2 495 /** Reset Target Device with custom specific I/O pin or command sequence.
Pawel Zarembski 0:01f31e923fe2 496 This function allows the optional implementation of a device specific reset sequence.
Pawel Zarembski 0:01f31e923fe2 497 It is called when the command \ref DAP_ResetTarget and is for example required
Pawel Zarembski 0:01f31e923fe2 498 when a device needs a time-critical unlock sequence that enables the debug port.
Pawel Zarembski 0:01f31e923fe2 499 \return 0 = no device specific reset sequence is implemented.\n
Pawel Zarembski 0:01f31e923fe2 500 1 = a device specific reset sequence is implemented.
Pawel Zarembski 0:01f31e923fe2 501 */
Pawel Zarembski 0:01f31e923fe2 502 __STATIC_INLINE uint32_t RESET_TARGET(void)
Pawel Zarembski 0:01f31e923fe2 503 {
Pawel Zarembski 0:01f31e923fe2 504 return (0); // change to '1' when a device reset sequence is implemented
Pawel Zarembski 0:01f31e923fe2 505 }
Pawel Zarembski 0:01f31e923fe2 506
Pawel Zarembski 0:01f31e923fe2 507 ///@}
Pawel Zarembski 0:01f31e923fe2 508
Pawel Zarembski 0:01f31e923fe2 509
Pawel Zarembski 0:01f31e923fe2 510 #endif /* __DAP_CONFIG_H__ */