Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/family/arm/musca_b/target_reset.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file target_reset.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief Target reset for Musca B target
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "target_family.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "target_config.h" // for target_device
Pawel Zarembski 0:01f31e923fe2 24 #include "swd_host.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "i2c_gpio.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "debug_cm.h"
Pawel Zarembski 0:01f31e923fe2 28 #include "utils.h"
Pawel Zarembski 0:01f31e923fe2 29 #include "power_ctrl.h"
Pawel Zarembski 0:01f31e923fe2 30 #include "uart.h"
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 static void musca_b_target_before_init_debug(void)
Pawel Zarembski 0:01f31e923fe2 33 {
Pawel Zarembski 0:01f31e923fe2 34 uint8_t buf[12];
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 // go into controlled shutdown
Pawel Zarembski 0:01f31e923fe2 37 power_off_sequence();
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 // Drive SCC signals
Pawel Zarembski 0:01f31e923fe2 40 LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 41 LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 42 LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
Pawel Zarembski 0:01f31e923fe2 43 LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
Pawel Zarembski 0:01f31e923fe2 44 LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 45
Pawel Zarembski 0:01f31e923fe2 46 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 47 delay(10);
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 // Release CFG_nRST to allow SCC config
Pawel Zarembski 0:01f31e923fe2 50 LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
Pawel Zarembski 0:01f31e923fe2 51
Pawel Zarembski 0:01f31e923fe2 52 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 53 delay(10);
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 // Configure SCC
Pawel Zarembski 0:01f31e923fe2 56 configure_syscon(0x1A400000);
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 59 delay(10);
Pawel Zarembski 0:01f31e923fe2 60
Pawel Zarembski 0:01f31e923fe2 61 // Creating branch to self in SRAM
Pawel Zarembski 0:01f31e923fe2 62 buf[0] = 0x00;
Pawel Zarembski 0:01f31e923fe2 63 buf[1] = 0x00;
Pawel Zarembski 0:01f31e923fe2 64 buf[2] = 0x08;
Pawel Zarembski 0:01f31e923fe2 65 buf[3] = 0x30;
Pawel Zarembski 0:01f31e923fe2 66 buf[4] = 0x09;
Pawel Zarembski 0:01f31e923fe2 67 buf[5] = 0x00;
Pawel Zarembski 0:01f31e923fe2 68 buf[6] = 0x40;
Pawel Zarembski 0:01f31e923fe2 69 buf[7] = 0x1A;
Pawel Zarembski 0:01f31e923fe2 70 buf[8] = 0xFE;
Pawel Zarembski 0:01f31e923fe2 71 buf[9] = 0xE7;
Pawel Zarembski 0:01f31e923fe2 72 buf[10] = 0xFE;
Pawel Zarembski 0:01f31e923fe2 73 buf[11] = 0xE7;
Pawel Zarembski 0:01f31e923fe2 74
Pawel Zarembski 0:01f31e923fe2 75 swd_write_memory(0x1A400000, (uint8_t *)buf, 12);
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 // swd_write_word(0x1A400000, 0x30008000);
Pawel Zarembski 0:01f31e923fe2 78 // swd_write_word(0x1A400004, 0x1A400009);
Pawel Zarembski 0:01f31e923fe2 79 // swd_write_word(0x1A400008, 0xE7FEE7FE);
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 82 delay(10);
Pawel Zarembski 0:01f31e923fe2 83
Pawel Zarembski 0:01f31e923fe2 84 // Release SCC signals
Pawel Zarembski 0:01f31e923fe2 85 LPC_GPIO->DIR[PIN_SCC_CLK_PORT] &= ~PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 86 LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] &= ~PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 87 LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
Pawel Zarembski 0:01f31e923fe2 88 LPC_GPIO->DIR[PIN_SCC_WNR_PORT] &= ~PIN_SCC_WNR;
Pawel Zarembski 0:01f31e923fe2 89 LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] &= ~PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 92 delay(10);
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 // Release CB_nRST (nPORESET)
Pawel Zarembski 0:01f31e923fe2 95 LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 98 delay(10);
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 // Release CS_nSRST
Pawel Zarembski 0:01f31e923fe2 101 LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 102
Pawel Zarembski 0:01f31e923fe2 103 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 104 delay(10);
Pawel Zarembski 0:01f31e923fe2 105
Pawel Zarembski 0:01f31e923fe2 106 return;
Pawel Zarembski 0:01f31e923fe2 107 }
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 static uint8_t musca_b_target_set_state(target_state_t state)
Pawel Zarembski 0:01f31e923fe2 110 {
Pawel Zarembski 0:01f31e923fe2 111 if(state == RESET_RUN)
Pawel Zarembski 0:01f31e923fe2 112 {
Pawel Zarembski 0:01f31e923fe2 113 // go through controlled reset
Pawel Zarembski 0:01f31e923fe2 114 power_off_sequence();
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 power_on_sequence();
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 119 delay(10);
Pawel Zarembski 0:01f31e923fe2 120
Pawel Zarembski 0:01f31e923fe2 121 swd_off();
Pawel Zarembski 0:01f31e923fe2 122
Pawel Zarembski 0:01f31e923fe2 123 return 1;
Pawel Zarembski 0:01f31e923fe2 124 }
Pawel Zarembski 0:01f31e923fe2 125 if(state == SHUTDOWN)
Pawel Zarembski 0:01f31e923fe2 126 {
Pawel Zarembski 0:01f31e923fe2 127 // go through controlled shutdown
Pawel Zarembski 0:01f31e923fe2 128 power_off_sequence();
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 // Turn OFF power
Pawel Zarembski 0:01f31e923fe2 131 i2cio_power_off();
Pawel Zarembski 0:01f31e923fe2 132
Pawel Zarembski 0:01f31e923fe2 133 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 134 delay(10);
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 uart_reset();
Pawel Zarembski 0:01f31e923fe2 137
Pawel Zarembski 0:01f31e923fe2 138 return 1;
Pawel Zarembski 0:01f31e923fe2 139 }
Pawel Zarembski 0:01f31e923fe2 140 if(state == POWER_ON)
Pawel Zarembski 0:01f31e923fe2 141 {
Pawel Zarembski 0:01f31e923fe2 142 // Turn ON power
Pawel Zarembski 0:01f31e923fe2 143 i2cio_power_on();
Pawel Zarembski 0:01f31e923fe2 144
Pawel Zarembski 0:01f31e923fe2 145 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 146 delay(10);
Pawel Zarembski 0:01f31e923fe2 147
Pawel Zarembski 0:01f31e923fe2 148 // power on the target
Pawel Zarembski 0:01f31e923fe2 149 power_on_sequence();
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 // Wait 10ms
Pawel Zarembski 0:01f31e923fe2 152 delay(10);
Pawel Zarembski 0:01f31e923fe2 153
Pawel Zarembski 0:01f31e923fe2 154 swd_off();
Pawel Zarembski 0:01f31e923fe2 155 return 1;
Pawel Zarembski 0:01f31e923fe2 156 }
Pawel Zarembski 0:01f31e923fe2 157
Pawel Zarembski 0:01f31e923fe2 158 return swd_set_target_state_sw(state);
Pawel Zarembski 0:01f31e923fe2 159 }
Pawel Zarembski 0:01f31e923fe2 160
Pawel Zarembski 0:01f31e923fe2 161 const target_family_descriptor_t g_target_family_musca_b = {
Pawel Zarembski 0:01f31e923fe2 162 .target_before_init_debug = musca_b_target_before_init_debug,
Pawel Zarembski 0:01f31e923fe2 163 .target_set_state = musca_b_target_set_state,
Pawel Zarembski 0:01f31e923fe2 164 .apsel = 0x01000000,
Pawel Zarembski 0:01f31e923fe2 165 };
Pawel Zarembski 0:01f31e923fe2 166
Pawel Zarembski 0:01f31e923fe2 167 const target_family_descriptor_t *g_target_family = &g_target_family_musca_b;