Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/family/arm/musca_b/syscon.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file syscon.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief System Controller serial interface
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2008-2019, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include <ctype.h> // character functions
Pawel Zarembski 0:01f31e923fe2 23 #include <string.h> // string and memory functions
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "IO_Config_Override.h" // I/O pin definitions
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 #include "syscon.h" // SCC interface
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 // SYSCON timing
Pawel Zarembski 0:01f31e923fe2 30 #define TSUH 2 // Clock setup and hold
Pawel Zarembski 0:01f31e923fe2 31 #define TCLK 2 // Clock high time
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 // Misc defines
Pawel Zarembski 0:01f31e923fe2 34 #define GPIOIMSK 0x003F // GPIOI SCC bit mask
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 37 System Controller serial interface
Pawel Zarembski 0:01f31e923fe2 38 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 39 static void Sleepns(uint32_t cycles)
Pawel Zarembski 0:01f31e923fe2 40 {
Pawel Zarembski 0:01f31e923fe2 41 volatile uint32_t i = cycles; // fudge factor to give approximate 1 ns
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 while (i > 0) {
Pawel Zarembski 0:01f31e923fe2 44 i--;
Pawel Zarembski 0:01f31e923fe2 45 }
Pawel Zarembski 0:01f31e923fe2 46 }
Pawel Zarembski 0:01f31e923fe2 47 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 48 System Controller 32bit register read (16uS)
Pawel Zarembski 0:01f31e923fe2 49 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 50 void syscon_readreg(unsigned int addr, unsigned int *din)
Pawel Zarembski 0:01f31e923fe2 51 {
Pawel Zarembski 0:01f31e923fe2 52 volatile unsigned int loop, data;
Pawel Zarembski 0:01f31e923fe2 53
Pawel Zarembski 0:01f31e923fe2 54 // Write the 12bit address value
Pawel Zarembski 0:01f31e923fe2 55 for(loop = 0; loop < 12; loop++)
Pawel Zarembski 0:01f31e923fe2 56 {
Pawel Zarembski 0:01f31e923fe2 57 if (addr & 0x800)
Pawel Zarembski 0:01f31e923fe2 58 {
Pawel Zarembski 0:01f31e923fe2 59 LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 60 }
Pawel Zarembski 0:01f31e923fe2 61 else
Pawel Zarembski 0:01f31e923fe2 62 {
Pawel Zarembski 0:01f31e923fe2 63 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 64 }
Pawel Zarembski 0:01f31e923fe2 65 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 66 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 67 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 68 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 69 // Set next address bit
Pawel Zarembski 0:01f31e923fe2 70 addr = (addr << 1) & 0xFFF;
Pawel Zarembski 0:01f31e923fe2 71 }
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 74 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 75
Pawel Zarembski 0:01f31e923fe2 76 // Config load
Pawel Zarembski 0:01f31e923fe2 77 LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 78 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 79 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 80 Sleepns(TCLK * 3);
Pawel Zarembski 0:01f31e923fe2 81 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 82 LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 83 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 // Read the 32bit data value
Pawel Zarembski 0:01f31e923fe2 86 data = 0;
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88 for (loop = 0; loop < 4; loop++)
Pawel Zarembski 0:01f31e923fe2 89 {
Pawel Zarembski 0:01f31e923fe2 90 data = (data >> 8) & 0x00FFFFFF;
Pawel Zarembski 0:01f31e923fe2 91 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 92 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 93 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 94 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 95 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 96 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (24 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 97 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 98 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 99 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 100 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 101 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 102 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (25 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 103 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 104 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 105 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 106 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 107 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 108 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (26 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 109 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 110 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 111 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 112 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 113 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 114 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (27 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 115 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 116 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 117 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 118 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 119 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 120 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (28 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 121 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 122 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 123 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 124 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 125 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 126 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (29 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 127 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 128 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 129 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 130 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 131 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 132 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (30 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 133 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 134 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 135 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 136 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 137 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 138 data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (31 - PIN_SCC_DATAOUT_BIT));
Pawel Zarembski 0:01f31e923fe2 139 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 140 }
Pawel Zarembski 0:01f31e923fe2 141
Pawel Zarembski 0:01f31e923fe2 142 // Return the 32bit data value
Pawel Zarembski 0:01f31e923fe2 143 *din = data;
Pawel Zarembski 0:01f31e923fe2 144 }
Pawel Zarembski 0:01f31e923fe2 145
Pawel Zarembski 0:01f31e923fe2 146 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 147 System Controller 32bit register write (20uS)
Pawel Zarembski 0:01f31e923fe2 148 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 149 void syscon_writereg(unsigned int addr, unsigned int dout)
Pawel Zarembski 0:01f31e923fe2 150 {
Pawel Zarembski 0:01f31e923fe2 151 volatile unsigned int loop, data;
Pawel Zarembski 0:01f31e923fe2 152
Pawel Zarembski 0:01f31e923fe2 153 // Set write enable
Pawel Zarembski 0:01f31e923fe2 154 LPC_GPIO->SET[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 // Write the 12bit address value
Pawel Zarembski 0:01f31e923fe2 157 for(loop = 0; loop < 12; loop++)
Pawel Zarembski 0:01f31e923fe2 158 {
Pawel Zarembski 0:01f31e923fe2 159 if (addr & 0x800)
Pawel Zarembski 0:01f31e923fe2 160 {
Pawel Zarembski 0:01f31e923fe2 161 LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 162 }
Pawel Zarembski 0:01f31e923fe2 163 else
Pawel Zarembski 0:01f31e923fe2 164 {
Pawel Zarembski 0:01f31e923fe2 165 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 166 }
Pawel Zarembski 0:01f31e923fe2 167 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 168 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 169 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 170 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 171 // Set next address bit
Pawel Zarembski 0:01f31e923fe2 172 addr = (addr << 1) & 0xFFF;
Pawel Zarembski 0:01f31e923fe2 173 }
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 176 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 // Write the 32bit data value
Pawel Zarembski 0:01f31e923fe2 179 data = dout;
Pawel Zarembski 0:01f31e923fe2 180 for (loop = 0; loop < 32; loop++)
Pawel Zarembski 0:01f31e923fe2 181 {
Pawel Zarembski 0:01f31e923fe2 182 if (data & 0x80000000)
Pawel Zarembski 0:01f31e923fe2 183 {
Pawel Zarembski 0:01f31e923fe2 184 LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 185 }
Pawel Zarembski 0:01f31e923fe2 186 else
Pawel Zarembski 0:01f31e923fe2 187 {
Pawel Zarembski 0:01f31e923fe2 188 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 189 }
Pawel Zarembski 0:01f31e923fe2 190 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 191 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 192 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 193 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 194 // Set next address bit
Pawel Zarembski 0:01f31e923fe2 195 data = (data << 1);
Pawel Zarembski 0:01f31e923fe2 196 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 197 }
Pawel Zarembski 0:01f31e923fe2 198
Pawel Zarembski 0:01f31e923fe2 199 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
Pawel Zarembski 0:01f31e923fe2 200 Sleepns(TCLK);
Pawel Zarembski 0:01f31e923fe2 201
Pawel Zarembski 0:01f31e923fe2 202 // Config load
Pawel Zarembski 0:01f31e923fe2 203 LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 204 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 205 LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 206 Sleepns(TCLK * 3);
Pawel Zarembski 0:01f31e923fe2 207 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
Pawel Zarembski 0:01f31e923fe2 208 LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
Pawel Zarembski 0:01f31e923fe2 209 Sleepns(TCLK * 2);
Pawel Zarembski 0:01f31e923fe2 210
Pawel Zarembski 0:01f31e923fe2 211 // Set to read
Pawel Zarembski 0:01f31e923fe2 212 LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
Pawel Zarembski 0:01f31e923fe2 213 }
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215 // end of syscon.c