Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/family/arm/musca_a/syscon.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file syscon.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief System Controller serial interface
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 /* Define to prevent recursive inclusion ------------------------------------ */
Pawel Zarembski 0:01f31e923fe2 23 #ifndef __SYSCON_H
Pawel Zarembski 0:01f31e923fe2 24 #define __SYSCON_H
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 /* SCC registers */
Pawel Zarembski 0:01f31e923fe2 27 #define SCC_RESET_CTRL 0x00 // RESET Control register
Pawel Zarembski 0:01f31e923fe2 28 #define SCC_CLK_CTRL 0x04 // CLOCK Control register
Pawel Zarembski 0:01f31e923fe2 29 #define SCC_PWR_CTRL 0x08 // Power Control register
Pawel Zarembski 0:01f31e923fe2 30 #define SCC_PLL_CTRL 0x0C // System Clock divider register
Pawel Zarembski 0:01f31e923fe2 31 #define SCC_DBG_CTRL 0x10 // Debug Security override
Pawel Zarembski 0:01f31e923fe2 32 #define SCC_SRAM_CTRL 0x14 // SRAM Bank power gate enable
Pawel Zarembski 0:01f31e923fe2 33 #define SCC_INTR_CTRL 0x18 // Combined interrupt mask
Pawel Zarembski 0:01f31e923fe2 34 #define SCC_CORDIO_CTRL 0x1C // REF to LLC Control and multiplex
Pawel Zarembski 0:01f31e923fe2 35 #define SCC_CPU0_VTOR_SRAM 0x20 // CPU0 SRAM Boot vector
Pawel Zarembski 0:01f31e923fe2 36 #define SCC_SPARE0 0x24 // CPU0 Spare
Pawel Zarembski 0:01f31e923fe2 37 #define SCC_CPU1_VTOR_SRAM 0x28 // CPU1 SRAM Boot vector
Pawel Zarembski 0:01f31e923fe2 38 #define SCC_SPARE1 0x2C // CPU1 Spare
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 void syscon_readreg(unsigned int addr, unsigned int *din);
Pawel Zarembski 0:01f31e923fe2 41 void syscon_writereg(unsigned int addr, unsigned int dout);
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 #endif