Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/daplink/cmsis-dap/debug_cm.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file debug_cm.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef DEBUG_CM_H
Pawel Zarembski 0:01f31e923fe2 23 #define DEBUG_CM_H
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "DAP.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 // SWD register access
Pawel Zarembski 0:01f31e923fe2 28 #define SWD_REG_AP (1)
Pawel Zarembski 0:01f31e923fe2 29 #define SWD_REG_DP (0)
Pawel Zarembski 0:01f31e923fe2 30 #define SWD_REG_R (1<<1)
Pawel Zarembski 0:01f31e923fe2 31 #define SWD_REG_W (0<<1)
Pawel Zarembski 0:01f31e923fe2 32 #define SWD_REG_ADR(a) (a & 0x0c)
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 // Abort Register definitions
Pawel Zarembski 0:01f31e923fe2 35 #define DAPABORT 0x00000001 // DAP Abort
Pawel Zarembski 0:01f31e923fe2 36 #define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only)
Pawel Zarembski 0:01f31e923fe2 37 #define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only)
Pawel Zarembski 0:01f31e923fe2 38 #define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only)
Pawel Zarembski 0:01f31e923fe2 39 #define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only)
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 // Debug Control and Status definitions
Pawel Zarembski 0:01f31e923fe2 42 #define ORUNDETECT 0x00000001 // Overrun Detect
Pawel Zarembski 0:01f31e923fe2 43 #define STICKYORUN 0x00000002 // Sticky Overrun
Pawel Zarembski 0:01f31e923fe2 44 #define TRNMODE 0x0000000C // Transfer Mode Mask
Pawel Zarembski 0:01f31e923fe2 45 #define TRNNORMAL 0x00000000 // Transfer Mode: Normal
Pawel Zarembski 0:01f31e923fe2 46 #define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify
Pawel Zarembski 0:01f31e923fe2 47 #define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare
Pawel Zarembski 0:01f31e923fe2 48 #define STICKYCMP 0x00000010 // Sticky Compare
Pawel Zarembski 0:01f31e923fe2 49 #define STICKYERR 0x00000020 // Sticky Error
Pawel Zarembski 0:01f31e923fe2 50 #define READOK 0x00000040 // Read OK (SW Only)
Pawel Zarembski 0:01f31e923fe2 51 #define WDATAERR 0x00000080 // Write Data Error (SW Only)
Pawel Zarembski 0:01f31e923fe2 52 #define MASKLANE 0x00000F00 // Mask Lane Mask
Pawel Zarembski 0:01f31e923fe2 53 #define MASKLANE0 0x00000100 // Mask Lane 0
Pawel Zarembski 0:01f31e923fe2 54 #define MASKLANE1 0x00000200 // Mask Lane 1
Pawel Zarembski 0:01f31e923fe2 55 #define MASKLANE2 0x00000400 // Mask Lane 2
Pawel Zarembski 0:01f31e923fe2 56 #define MASKLANE3 0x00000800 // Mask Lane 3
Pawel Zarembski 0:01f31e923fe2 57 #define TRNCNT 0x001FF000 // Transaction Counter Mask
Pawel Zarembski 0:01f31e923fe2 58 #define CDBGRSTREQ 0x04000000 // Debug Reset Request
Pawel Zarembski 0:01f31e923fe2 59 #define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge
Pawel Zarembski 0:01f31e923fe2 60 #define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request
Pawel Zarembski 0:01f31e923fe2 61 #define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge
Pawel Zarembski 0:01f31e923fe2 62 #define CSYSPWRUPREQ 0x40000000 // System Power-up Request
Pawel Zarembski 0:01f31e923fe2 63 #define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge
Pawel Zarembski 0:01f31e923fe2 64
Pawel Zarembski 0:01f31e923fe2 65 // Debug Select Register definitions
Pawel Zarembski 0:01f31e923fe2 66 #define CTRLSEL 0x00000001 // CTRLSEL (SW Only)
Pawel Zarembski 0:01f31e923fe2 67 #define APBANKSEL 0x000000F0 // APBANKSEL Mask
Pawel Zarembski 0:01f31e923fe2 68 #define APSEL 0xFF000000 // APSEL Mask
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 // Access Port Register Addresses
Pawel Zarembski 0:01f31e923fe2 71 #define AP_CSW 0x00 // Control and Status Word
Pawel Zarembski 0:01f31e923fe2 72 #define AP_TAR 0x04 // Transfer Address
Pawel Zarembski 0:01f31e923fe2 73 #define AP_DRW 0x0C // Data Read/Write
Pawel Zarembski 0:01f31e923fe2 74 #define AP_BD0 0x10 // Banked Data 0
Pawel Zarembski 0:01f31e923fe2 75 #define AP_BD1 0x14 // Banked Data 1
Pawel Zarembski 0:01f31e923fe2 76 #define AP_BD2 0x18 // Banked Data 2
Pawel Zarembski 0:01f31e923fe2 77 #define AP_BD3 0x1C // Banked Data 3
Pawel Zarembski 0:01f31e923fe2 78 #define AP_ROM 0xF8 // Debug ROM Address
Pawel Zarembski 0:01f31e923fe2 79 #define AP_IDR 0xFC // Identification Register
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 // AP Control and Status Word definitions
Pawel Zarembski 0:01f31e923fe2 82 #define CSW_SIZE 0x00000007 // Access Size: Selection Mask
Pawel Zarembski 0:01f31e923fe2 83 #define CSW_SIZE8 0x00000000 // Access Size: 8-bit
Pawel Zarembski 0:01f31e923fe2 84 #define CSW_SIZE16 0x00000001 // Access Size: 16-bit
Pawel Zarembski 0:01f31e923fe2 85 #define CSW_SIZE32 0x00000002 // Access Size: 32-bit
Pawel Zarembski 0:01f31e923fe2 86 #define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask
Pawel Zarembski 0:01f31e923fe2 87 #define CSW_NADDRINC 0x00000000 // No Address Increment
Pawel Zarembski 0:01f31e923fe2 88 #define CSW_SADDRINC 0x00000010 // Single Address Increment
Pawel Zarembski 0:01f31e923fe2 89 #define CSW_PADDRINC 0x00000020 // Packed Address Increment
Pawel Zarembski 0:01f31e923fe2 90 #define CSW_DBGSTAT 0x00000040 // Debug Status
Pawel Zarembski 0:01f31e923fe2 91 #define CSW_TINPROG 0x00000080 // Transfer in progress
Pawel Zarembski 0:01f31e923fe2 92 #define CSW_HPROT 0x02000000 // User/Privilege Control
Pawel Zarembski 0:01f31e923fe2 93 #define CSW_MSTRTYPE 0x20000000 // Master Type Mask
Pawel Zarembski 0:01f31e923fe2 94 #define CSW_MSTRCORE 0x00000000 // Master Type: Core
Pawel Zarembski 0:01f31e923fe2 95 #define CSW_MSTRDBG 0x20000000 // Master Type: Debug
Pawel Zarembski 0:01f31e923fe2 96 #define CSW_RESERVED 0x01000000 // Reserved Value
Pawel Zarembski 0:01f31e923fe2 97
Pawel Zarembski 0:01f31e923fe2 98 // Core Debug Register Address Offsets
Pawel Zarembski 0:01f31e923fe2 99 #define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC
Pawel Zarembski 0:01f31e923fe2 100 #define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register
Pawel Zarembski 0:01f31e923fe2 101 #define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register
Pawel Zarembski 0:01f31e923fe2 102 #define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register
Pawel Zarembski 0:01f31e923fe2 103 #define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 // Core Debug Register Addresses
Pawel Zarembski 0:01f31e923fe2 106 #define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS)
Pawel Zarembski 0:01f31e923fe2 107 #define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS)
Pawel Zarembski 0:01f31e923fe2 108 #define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS)
Pawel Zarembski 0:01f31e923fe2 109 #define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS)
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 // Debug Halting Control and Status Register definitions
Pawel Zarembski 0:01f31e923fe2 112 #define C_DEBUGEN 0x00000001 // Debug Enable
Pawel Zarembski 0:01f31e923fe2 113 #define C_HALT 0x00000002 // Halt
Pawel Zarembski 0:01f31e923fe2 114 #define C_STEP 0x00000004 // Step
Pawel Zarembski 0:01f31e923fe2 115 #define C_MASKINTS 0x00000008 // Mask Interrupts
Pawel Zarembski 0:01f31e923fe2 116 #define C_SNAPSTALL 0x00000020 // Snap Stall
Pawel Zarembski 0:01f31e923fe2 117 #define S_REGRDY 0x00010000 // Register R/W Ready Flag
Pawel Zarembski 0:01f31e923fe2 118 #define S_HALT 0x00020000 // Halt Flag
Pawel Zarembski 0:01f31e923fe2 119 #define S_SLEEP 0x00040000 // Sleep Flag
Pawel Zarembski 0:01f31e923fe2 120 #define S_LOCKUP 0x00080000 // Lockup Flag
Pawel Zarembski 0:01f31e923fe2 121 #define S_RETIRE_ST 0x01000000 // Sticky Retire Flag
Pawel Zarembski 0:01f31e923fe2 122 #define S_RESET_ST 0x02000000 // Sticky Reset Flag
Pawel Zarembski 0:01f31e923fe2 123 #define DBGKEY 0xA05F0000 // Debug Key
Pawel Zarembski 0:01f31e923fe2 124
Pawel Zarembski 0:01f31e923fe2 125 // Debug Exception and Monitor Control Register definitions
Pawel Zarembski 0:01f31e923fe2 126 #define VC_CORERESET 0x00000001 // Reset Vector Catch
Pawel Zarembski 0:01f31e923fe2 127 #define VC_MMERR 0x00000010 // Debug Trap on MMU Fault
Pawel Zarembski 0:01f31e923fe2 128 #define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault
Pawel Zarembski 0:01f31e923fe2 129 #define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault
Pawel Zarembski 0:01f31e923fe2 130 #define VC_STATERR 0x00000080 // Debug Trap on State Error Fault
Pawel Zarembski 0:01f31e923fe2 131 #define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault
Pawel Zarembski 0:01f31e923fe2 132 #define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault
Pawel Zarembski 0:01f31e923fe2 133 #define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault
Pawel Zarembski 0:01f31e923fe2 134 #define MON_EN 0x00010000 // Monitor Enable
Pawel Zarembski 0:01f31e923fe2 135 #define MON_PEND 0x00020000 // Monitor Pend
Pawel Zarembski 0:01f31e923fe2 136 #define MON_STEP 0x00040000 // Monitor Step
Pawel Zarembski 0:01f31e923fe2 137 #define MON_REQ 0x00080000 // Monitor Request
Pawel Zarembski 0:01f31e923fe2 138 #define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU)
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 // NVIC: Interrupt Controller Type Register
Pawel Zarembski 0:01f31e923fe2 141 #define NVIC_ICT (NVIC_Addr + 0x0004)
Pawel Zarembski 0:01f31e923fe2 142 #define INTLINESNUM 0x0000001F // Interrupt Line Numbers
Pawel Zarembski 0:01f31e923fe2 143
Pawel Zarembski 0:01f31e923fe2 144 // NVIC: CPUID Base Register
Pawel Zarembski 0:01f31e923fe2 145 #define NVIC_CPUID (NVIC_Addr + 0x0D00)
Pawel Zarembski 0:01f31e923fe2 146 #define CPUID_PARTNO 0x0000FFF0 // Part Number Mask
Pawel Zarembski 0:01f31e923fe2 147 #define CPUID_REVISION 0x0000000F // Revision Mask
Pawel Zarembski 0:01f31e923fe2 148 #define CPUID_VARIANT 0x00F00000 // Variant Mask
Pawel Zarembski 0:01f31e923fe2 149
Pawel Zarembski 0:01f31e923fe2 150 // NVIC: Application Interrupt/Reset Control Register
Pawel Zarembski 0:01f31e923fe2 151 #define NVIC_AIRCR (NVIC_Addr + 0x0D0C)
Pawel Zarembski 0:01f31e923fe2 152 #define VECTRESET 0x00000001 // Reset Cortex-M (except Debug)
Pawel Zarembski 0:01f31e923fe2 153 #define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit
Pawel Zarembski 0:01f31e923fe2 154 #define SYSRESETREQ 0x00000004 // Reset System (except Debug)
Pawel Zarembski 0:01f31e923fe2 155 #define VECTKEY 0x05FA0000 // Write Key
Pawel Zarembski 0:01f31e923fe2 156
Pawel Zarembski 0:01f31e923fe2 157 // NVIC: Debug Fault Status Register
Pawel Zarembski 0:01f31e923fe2 158 #define NVIC_DFSR (NVIC_Addr + 0x0D30)
Pawel Zarembski 0:01f31e923fe2 159 #define HALTED 0x00000001 // Halt Flag
Pawel Zarembski 0:01f31e923fe2 160 #define BKPT 0x00000002 // BKPT Flag
Pawel Zarembski 0:01f31e923fe2 161 #define DWTTRAP 0x00000004 // DWT Match
Pawel Zarembski 0:01f31e923fe2 162 #define VCATCH 0x00000008 // Vector Catch Flag
Pawel Zarembski 0:01f31e923fe2 163 #define EXTERNAL 0x00000010 // External Debug Request
Pawel Zarembski 0:01f31e923fe2 164
Pawel Zarembski 0:01f31e923fe2 165 // Data Watchpoint and Trace unit
Pawel Zarembski 0:01f31e923fe2 166 #define DWT_PCSR 0xe000101c // DWT PC Sampling Register
Pawel Zarembski 0:01f31e923fe2 167
Pawel Zarembski 0:01f31e923fe2 168 #endif