Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/daplink/HardFault_Handler.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file main.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief Entry point for interface program logic
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22
Pawel Zarembski 0:01f31e923fe2 23 #include "settings.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "util.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "cortex_m.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 register unsigned int _psp __asm("psp");
Pawel Zarembski 0:01f31e923fe2 28 register unsigned int _msp __asm("msp");
Pawel Zarembski 0:01f31e923fe2 29 register unsigned int _lr __asm("lr");
Pawel Zarembski 0:01f31e923fe2 30 register unsigned int _control __asm("control");
Pawel Zarembski 0:01f31e923fe2 31 void HardFault_Handler()
Pawel Zarembski 0:01f31e923fe2 32 {
Pawel Zarembski 0:01f31e923fe2 33 //hexdump logic on hardfault
Pawel Zarembski 0:01f31e923fe2 34 uint32_t stk_ptr;
Pawel Zarembski 0:01f31e923fe2 35 uint32_t * stack = (uint32_t *)_msp;
Pawel Zarembski 0:01f31e923fe2 36
Pawel Zarembski 0:01f31e923fe2 37 if ((_lr & 0xF) == 0xD) { //process stack
Pawel Zarembski 0:01f31e923fe2 38 stack = (uint32_t *)_psp;
Pawel Zarembski 0:01f31e923fe2 39 }
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 //calculate stack ptr before fault
Pawel Zarembski 0:01f31e923fe2 42 stk_ptr = (uint32_t)stack + 0x20;
Pawel Zarembski 0:01f31e923fe2 43 if ((stack[7] & 0x200) != 0) { //xpsr bit 9 align
Pawel Zarembski 0:01f31e923fe2 44 stk_ptr += 0x4;
Pawel Zarembski 0:01f31e923fe2 45 }
Pawel Zarembski 0:01f31e923fe2 46 if ((_lr & 0x10) == 0) { //fp
Pawel Zarembski 0:01f31e923fe2 47 stk_ptr += 0x48;
Pawel Zarembski 0:01f31e923fe2 48 }
Pawel Zarembski 0:01f31e923fe2 49
Pawel Zarembski 0:01f31e923fe2 50 config_ram_add_hexdump(_lr); //EXC_RETURN
Pawel Zarembski 0:01f31e923fe2 51 config_ram_add_hexdump(_psp);
Pawel Zarembski 0:01f31e923fe2 52 config_ram_add_hexdump(_msp);
Pawel Zarembski 0:01f31e923fe2 53 config_ram_add_hexdump(_control);
Pawel Zarembski 0:01f31e923fe2 54 config_ram_add_hexdump(stk_ptr); //SP
Pawel Zarembski 0:01f31e923fe2 55 config_ram_add_hexdump(stack[5]); //LR
Pawel Zarembski 0:01f31e923fe2 56 config_ram_add_hexdump(stack[6]); //PC
Pawel Zarembski 0:01f31e923fe2 57 config_ram_add_hexdump(stack[7]); //xPSR
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 #ifndef __CORTEX_M
Pawel Zarembski 0:01f31e923fe2 60 #error __CORTEX_M not defined!!
Pawel Zarembski 0:01f31e923fe2 61 #else
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 #if (__CORTEX_M > 0x00)
Pawel Zarembski 0:01f31e923fe2 64 config_ram_add_hexdump(SCB->HFSR);
Pawel Zarembski 0:01f31e923fe2 65 config_ram_add_hexdump(SCB->CFSR);
Pawel Zarembski 0:01f31e923fe2 66 config_ram_add_hexdump(SCB->DFSR);
Pawel Zarembski 0:01f31e923fe2 67 config_ram_add_hexdump(SCB->AFSR);
Pawel Zarembski 0:01f31e923fe2 68 config_ram_add_hexdump(SCB->MMFAR);
Pawel Zarembski 0:01f31e923fe2 69 config_ram_add_hexdump(SCB->BFAR);
Pawel Zarembski 0:01f31e923fe2 70 #endif
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72 #endif //#ifndef __CORTEX_M
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 util_assert(0);
Pawel Zarembski 0:01f31e923fe2 75 SystemReset();
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 while (1); // Wait for reset
Pawel Zarembski 0:01f31e923fe2 78 }