Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/cmsis-core/mpu_armv7.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /******************************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * @file mpu_armv7.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief CMSIS MPU API for Armv7-M MPU
Pawel Zarembski 0:01f31e923fe2 4 * @version V5.1.0
Pawel Zarembski 0:01f31e923fe2 5 * @date 08. March 2019
Pawel Zarembski 0:01f31e923fe2 6 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 7 /*
Pawel Zarembski 0:01f31e923fe2 8 * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 11 *
Pawel Zarembski 0:01f31e923fe2 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Pawel Zarembski 0:01f31e923fe2 13 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 14 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 15 *
Pawel Zarembski 0:01f31e923fe2 16 * www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 17 *
Pawel Zarembski 0:01f31e923fe2 18 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 21 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 22 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 23 */
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #if defined ( __ICCARM__ )
Pawel Zarembski 0:01f31e923fe2 26 #pragma system_include /* treat file as system include file for MISRA check */
Pawel Zarembski 0:01f31e923fe2 27 #elif defined (__clang__)
Pawel Zarembski 0:01f31e923fe2 28 #pragma clang system_header /* treat file as system include file */
Pawel Zarembski 0:01f31e923fe2 29 #endif
Pawel Zarembski 0:01f31e923fe2 30
Pawel Zarembski 0:01f31e923fe2 31 #ifndef ARM_MPU_ARMV7_H
Pawel Zarembski 0:01f31e923fe2 32 #define ARM_MPU_ARMV7_H
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
Pawel Zarembski 0:01f31e923fe2 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
Pawel Zarembski 0:01f31e923fe2 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
Pawel Zarembski 0:01f31e923fe2 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
Pawel Zarembski 0:01f31e923fe2 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
Pawel Zarembski 0:01f31e923fe2 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
Pawel Zarembski 0:01f31e923fe2 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
Pawel Zarembski 0:01f31e923fe2 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
Pawel Zarembski 0:01f31e923fe2 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
Pawel Zarembski 0:01f31e923fe2 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
Pawel Zarembski 0:01f31e923fe2 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
Pawel Zarembski 0:01f31e923fe2 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
Pawel Zarembski 0:01f31e923fe2 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
Pawel Zarembski 0:01f31e923fe2 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
Pawel Zarembski 0:01f31e923fe2 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
Pawel Zarembski 0:01f31e923fe2 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
Pawel Zarembski 0:01f31e923fe2 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
Pawel Zarembski 0:01f31e923fe2 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
Pawel Zarembski 0:01f31e923fe2 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
Pawel Zarembski 0:01f31e923fe2 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
Pawel Zarembski 0:01f31e923fe2 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
Pawel Zarembski 0:01f31e923fe2 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
Pawel Zarembski 0:01f31e923fe2 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
Pawel Zarembski 0:01f31e923fe2 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
Pawel Zarembski 0:01f31e923fe2 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
Pawel Zarembski 0:01f31e923fe2 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
Pawel Zarembski 0:01f31e923fe2 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
Pawel Zarembski 0:01f31e923fe2 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
Pawel Zarembski 0:01f31e923fe2 64 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
Pawel Zarembski 0:01f31e923fe2 65 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
Pawel Zarembski 0:01f31e923fe2 66 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
Pawel Zarembski 0:01f31e923fe2 67 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
Pawel Zarembski 0:01f31e923fe2 68 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /** MPU Region Base Address Register Value
Pawel Zarembski 0:01f31e923fe2 71 *
Pawel Zarembski 0:01f31e923fe2 72 * \param Region The region to be configured, number 0 to 15.
Pawel Zarembski 0:01f31e923fe2 73 * \param BaseAddress The base address for the region.
Pawel Zarembski 0:01f31e923fe2 74 */
Pawel Zarembski 0:01f31e923fe2 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
Pawel Zarembski 0:01f31e923fe2 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
Pawel Zarembski 0:01f31e923fe2 77 ((Region) & MPU_RBAR_REGION_Msk) | \
Pawel Zarembski 0:01f31e923fe2 78 (MPU_RBAR_VALID_Msk))
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 /**
Pawel Zarembski 0:01f31e923fe2 81 * MPU Memory Access Attributes
Pawel Zarembski 0:01f31e923fe2 82 *
Pawel Zarembski 0:01f31e923fe2 83 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
Pawel Zarembski 0:01f31e923fe2 84 * \param IsShareable Region is shareable between multiple bus masters.
Pawel Zarembski 0:01f31e923fe2 85 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
Pawel Zarembski 0:01f31e923fe2 86 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
Pawel Zarembski 0:01f31e923fe2 87 */
Pawel Zarembski 0:01f31e923fe2 88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
Pawel Zarembski 0:01f31e923fe2 89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
Pawel Zarembski 0:01f31e923fe2 90 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
Pawel Zarembski 0:01f31e923fe2 91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
Pawel Zarembski 0:01f31e923fe2 92 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 /**
Pawel Zarembski 0:01f31e923fe2 95 * MPU Region Attribute and Size Register Value
Pawel Zarembski 0:01f31e923fe2 96 *
Pawel Zarembski 0:01f31e923fe2 97 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
Pawel Zarembski 0:01f31e923fe2 98 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
Pawel Zarembski 0:01f31e923fe2 99 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
Pawel Zarembski 0:01f31e923fe2 100 * \param SubRegionDisable Sub-region disable field.
Pawel Zarembski 0:01f31e923fe2 101 * \param Size Region size of the region to be configured, for example 4K, 8K.
Pawel Zarembski 0:01f31e923fe2 102 */
Pawel Zarembski 0:01f31e923fe2 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
Pawel Zarembski 0:01f31e923fe2 104 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
Pawel Zarembski 0:01f31e923fe2 105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
Pawel Zarembski 0:01f31e923fe2 106 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
Pawel Zarembski 0:01f31e923fe2 107 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
Pawel Zarembski 0:01f31e923fe2 108 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
Pawel Zarembski 0:01f31e923fe2 109 (((MPU_RASR_ENABLE_Msk))))
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 /**
Pawel Zarembski 0:01f31e923fe2 112 * MPU Region Attribute and Size Register Value
Pawel Zarembski 0:01f31e923fe2 113 *
Pawel Zarembski 0:01f31e923fe2 114 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
Pawel Zarembski 0:01f31e923fe2 115 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
Pawel Zarembski 0:01f31e923fe2 116 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
Pawel Zarembski 0:01f31e923fe2 117 * \param IsShareable Region is shareable between multiple bus masters.
Pawel Zarembski 0:01f31e923fe2 118 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
Pawel Zarembski 0:01f31e923fe2 119 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
Pawel Zarembski 0:01f31e923fe2 120 * \param SubRegionDisable Sub-region disable field.
Pawel Zarembski 0:01f31e923fe2 121 * \param Size Region size of the region to be configured, for example 4K, 8K.
Pawel Zarembski 0:01f31e923fe2 122 */
Pawel Zarembski 0:01f31e923fe2 123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
Pawel Zarembski 0:01f31e923fe2 124 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 /**
Pawel Zarembski 0:01f31e923fe2 127 * MPU Memory Access Attribute for strongly ordered memory.
Pawel Zarembski 0:01f31e923fe2 128 * - TEX: 000b
Pawel Zarembski 0:01f31e923fe2 129 * - Shareable
Pawel Zarembski 0:01f31e923fe2 130 * - Non-cacheable
Pawel Zarembski 0:01f31e923fe2 131 * - Non-bufferable
Pawel Zarembski 0:01f31e923fe2 132 */
Pawel Zarembski 0:01f31e923fe2 133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135 /**
Pawel Zarembski 0:01f31e923fe2 136 * MPU Memory Access Attribute for device memory.
Pawel Zarembski 0:01f31e923fe2 137 * - TEX: 000b (if shareable) or 010b (if non-shareable)
Pawel Zarembski 0:01f31e923fe2 138 * - Shareable or non-shareable
Pawel Zarembski 0:01f31e923fe2 139 * - Non-cacheable
Pawel Zarembski 0:01f31e923fe2 140 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
Pawel Zarembski 0:01f31e923fe2 141 *
Pawel Zarembski 0:01f31e923fe2 142 * \param IsShareable Configures the device memory as shareable or non-shareable.
Pawel Zarembski 0:01f31e923fe2 143 */
Pawel Zarembski 0:01f31e923fe2 144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
Pawel Zarembski 0:01f31e923fe2 145
Pawel Zarembski 0:01f31e923fe2 146 /**
Pawel Zarembski 0:01f31e923fe2 147 * MPU Memory Access Attribute for normal memory.
Pawel Zarembski 0:01f31e923fe2 148 * - TEX: 1BBb (reflecting outer cacheability rules)
Pawel Zarembski 0:01f31e923fe2 149 * - Shareable or non-shareable
Pawel Zarembski 0:01f31e923fe2 150 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
Pawel Zarembski 0:01f31e923fe2 151 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
Pawel Zarembski 0:01f31e923fe2 152 *
Pawel Zarembski 0:01f31e923fe2 153 * \param OuterCp Configures the outer cache policy.
Pawel Zarembski 0:01f31e923fe2 154 * \param InnerCp Configures the inner cache policy.
Pawel Zarembski 0:01f31e923fe2 155 * \param IsShareable Configures the memory as shareable or non-shareable.
Pawel Zarembski 0:01f31e923fe2 156 */
Pawel Zarembski 0:01f31e923fe2 157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
Pawel Zarembski 0:01f31e923fe2 158
Pawel Zarembski 0:01f31e923fe2 159 /**
Pawel Zarembski 0:01f31e923fe2 160 * MPU Memory Access Attribute non-cacheable policy.
Pawel Zarembski 0:01f31e923fe2 161 */
Pawel Zarembski 0:01f31e923fe2 162 #define ARM_MPU_CACHEP_NOCACHE 0U
Pawel Zarembski 0:01f31e923fe2 163
Pawel Zarembski 0:01f31e923fe2 164 /**
Pawel Zarembski 0:01f31e923fe2 165 * MPU Memory Access Attribute write-back, write and read allocate policy.
Pawel Zarembski 0:01f31e923fe2 166 */
Pawel Zarembski 0:01f31e923fe2 167 #define ARM_MPU_CACHEP_WB_WRA 1U
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 /**
Pawel Zarembski 0:01f31e923fe2 170 * MPU Memory Access Attribute write-through, no write allocate policy.
Pawel Zarembski 0:01f31e923fe2 171 */
Pawel Zarembski 0:01f31e923fe2 172 #define ARM_MPU_CACHEP_WT_NWA 2U
Pawel Zarembski 0:01f31e923fe2 173
Pawel Zarembski 0:01f31e923fe2 174 /**
Pawel Zarembski 0:01f31e923fe2 175 * MPU Memory Access Attribute write-back, no write allocate policy.
Pawel Zarembski 0:01f31e923fe2 176 */
Pawel Zarembski 0:01f31e923fe2 177 #define ARM_MPU_CACHEP_WB_NWA 3U
Pawel Zarembski 0:01f31e923fe2 178
Pawel Zarembski 0:01f31e923fe2 179
Pawel Zarembski 0:01f31e923fe2 180 /**
Pawel Zarembski 0:01f31e923fe2 181 * Struct for a single MPU Region
Pawel Zarembski 0:01f31e923fe2 182 */
Pawel Zarembski 0:01f31e923fe2 183 typedef struct {
Pawel Zarembski 0:01f31e923fe2 184 uint32_t RBAR; //!< The region base address register value (RBAR)
Pawel Zarembski 0:01f31e923fe2 185 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
Pawel Zarembski 0:01f31e923fe2 186 } ARM_MPU_Region_t;
Pawel Zarembski 0:01f31e923fe2 187
Pawel Zarembski 0:01f31e923fe2 188 /** Enable the MPU.
Pawel Zarembski 0:01f31e923fe2 189 * \param MPU_Control Default access permissions for unconfigured regions.
Pawel Zarembski 0:01f31e923fe2 190 */
Pawel Zarembski 0:01f31e923fe2 191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Pawel Zarembski 0:01f31e923fe2 192 {
Pawel Zarembski 0:01f31e923fe2 193 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 194 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 195 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 196 #endif
Pawel Zarembski 0:01f31e923fe2 197 __DSB();
Pawel Zarembski 0:01f31e923fe2 198 __ISB();
Pawel Zarembski 0:01f31e923fe2 199 }
Pawel Zarembski 0:01f31e923fe2 200
Pawel Zarembski 0:01f31e923fe2 201 /** Disable the MPU.
Pawel Zarembski 0:01f31e923fe2 202 */
Pawel Zarembski 0:01f31e923fe2 203 __STATIC_INLINE void ARM_MPU_Disable(void)
Pawel Zarembski 0:01f31e923fe2 204 {
Pawel Zarembski 0:01f31e923fe2 205 __DMB();
Pawel Zarembski 0:01f31e923fe2 206 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 207 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 208 #endif
Pawel Zarembski 0:01f31e923fe2 209 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 210 }
Pawel Zarembski 0:01f31e923fe2 211
Pawel Zarembski 0:01f31e923fe2 212 /** Clear and disable the given MPU region.
Pawel Zarembski 0:01f31e923fe2 213 * \param rnr Region number to be cleared.
Pawel Zarembski 0:01f31e923fe2 214 */
Pawel Zarembski 0:01f31e923fe2 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Pawel Zarembski 0:01f31e923fe2 216 {
Pawel Zarembski 0:01f31e923fe2 217 MPU->RNR = rnr;
Pawel Zarembski 0:01f31e923fe2 218 MPU->RASR = 0U;
Pawel Zarembski 0:01f31e923fe2 219 }
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 /** Configure an MPU region.
Pawel Zarembski 0:01f31e923fe2 222 * \param rbar Value for RBAR register.
Pawel Zarembski 0:01f31e923fe2 223 * \param rsar Value for RSAR register.
Pawel Zarembski 0:01f31e923fe2 224 */
Pawel Zarembski 0:01f31e923fe2 225 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
Pawel Zarembski 0:01f31e923fe2 226 {
Pawel Zarembski 0:01f31e923fe2 227 MPU->RBAR = rbar;
Pawel Zarembski 0:01f31e923fe2 228 MPU->RASR = rasr;
Pawel Zarembski 0:01f31e923fe2 229 }
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 /** Configure the given MPU region.
Pawel Zarembski 0:01f31e923fe2 232 * \param rnr Region number to be configured.
Pawel Zarembski 0:01f31e923fe2 233 * \param rbar Value for RBAR register.
Pawel Zarembski 0:01f31e923fe2 234 * \param rsar Value for RSAR register.
Pawel Zarembski 0:01f31e923fe2 235 */
Pawel Zarembski 0:01f31e923fe2 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
Pawel Zarembski 0:01f31e923fe2 237 {
Pawel Zarembski 0:01f31e923fe2 238 MPU->RNR = rnr;
Pawel Zarembski 0:01f31e923fe2 239 MPU->RBAR = rbar;
Pawel Zarembski 0:01f31e923fe2 240 MPU->RASR = rasr;
Pawel Zarembski 0:01f31e923fe2 241 }
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Pawel Zarembski 0:01f31e923fe2 244 * \param dst Destination data is copied to.
Pawel Zarembski 0:01f31e923fe2 245 * \param src Source data is copied from.
Pawel Zarembski 0:01f31e923fe2 246 * \param len Amount of data words to be copied.
Pawel Zarembski 0:01f31e923fe2 247 */
Pawel Zarembski 0:01f31e923fe2 248 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Pawel Zarembski 0:01f31e923fe2 249 {
Pawel Zarembski 0:01f31e923fe2 250 uint32_t i;
Pawel Zarembski 0:01f31e923fe2 251 for (i = 0U; i < len; ++i)
Pawel Zarembski 0:01f31e923fe2 252 {
Pawel Zarembski 0:01f31e923fe2 253 dst[i] = src[i];
Pawel Zarembski 0:01f31e923fe2 254 }
Pawel Zarembski 0:01f31e923fe2 255 }
Pawel Zarembski 0:01f31e923fe2 256
Pawel Zarembski 0:01f31e923fe2 257 /** Load the given number of MPU regions from a table.
Pawel Zarembski 0:01f31e923fe2 258 * \param table Pointer to the MPU configuration table.
Pawel Zarembski 0:01f31e923fe2 259 * \param cnt Amount of regions to be configured.
Pawel Zarembski 0:01f31e923fe2 260 */
Pawel Zarembski 0:01f31e923fe2 261 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
Pawel Zarembski 0:01f31e923fe2 262 {
Pawel Zarembski 0:01f31e923fe2 263 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Pawel Zarembski 0:01f31e923fe2 264 while (cnt > MPU_TYPE_RALIASES) {
Pawel Zarembski 0:01f31e923fe2 265 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
Pawel Zarembski 0:01f31e923fe2 266 table += MPU_TYPE_RALIASES;
Pawel Zarembski 0:01f31e923fe2 267 cnt -= MPU_TYPE_RALIASES;
Pawel Zarembski 0:01f31e923fe2 268 }
Pawel Zarembski 0:01f31e923fe2 269 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
Pawel Zarembski 0:01f31e923fe2 270 }
Pawel Zarembski 0:01f31e923fe2 271
Pawel Zarembski 0:01f31e923fe2 272 #endif