Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/cmsis-core/cmsis_armclang.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**************************************************************************//**
Pawel Zarembski 0:01f31e923fe2 2 * @file cmsis_armclang.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
Pawel Zarembski 0:01f31e923fe2 4 * @version V5.2.1
Pawel Zarembski 0:01f31e923fe2 5 * @date 30. July 2019
Pawel Zarembski 0:01f31e923fe2 6 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 7 /*
Pawel Zarembski 0:01f31e923fe2 8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 11 *
Pawel Zarembski 0:01f31e923fe2 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Pawel Zarembski 0:01f31e923fe2 13 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 14 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 15 *
Pawel Zarembski 0:01f31e923fe2 16 * www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 17 *
Pawel Zarembski 0:01f31e923fe2 18 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 21 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 22 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 23 */
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 #ifndef __CMSIS_ARMCLANG_H
Pawel Zarembski 0:01f31e923fe2 28 #define __CMSIS_ARMCLANG_H
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #pragma clang system_header /* treat file as system include file */
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 #ifndef __ARM_COMPAT_H
Pawel Zarembski 0:01f31e923fe2 33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
Pawel Zarembski 0:01f31e923fe2 34 #endif
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 /* CMSIS compiler specific defines */
Pawel Zarembski 0:01f31e923fe2 37 #ifndef __ASM
Pawel Zarembski 0:01f31e923fe2 38 #define __ASM __asm
Pawel Zarembski 0:01f31e923fe2 39 #endif
Pawel Zarembski 0:01f31e923fe2 40 #ifndef __INLINE
Pawel Zarembski 0:01f31e923fe2 41 #define __INLINE __inline
Pawel Zarembski 0:01f31e923fe2 42 #endif
Pawel Zarembski 0:01f31e923fe2 43 #ifndef __STATIC_INLINE
Pawel Zarembski 0:01f31e923fe2 44 #define __STATIC_INLINE static __inline
Pawel Zarembski 0:01f31e923fe2 45 #endif
Pawel Zarembski 0:01f31e923fe2 46 #ifndef __STATIC_FORCEINLINE
Pawel Zarembski 0:01f31e923fe2 47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
Pawel Zarembski 0:01f31e923fe2 48 #endif
Pawel Zarembski 0:01f31e923fe2 49 #ifndef __NO_RETURN
Pawel Zarembski 0:01f31e923fe2 50 #define __NO_RETURN __attribute__((__noreturn__))
Pawel Zarembski 0:01f31e923fe2 51 #endif
Pawel Zarembski 0:01f31e923fe2 52 #ifndef __USED
Pawel Zarembski 0:01f31e923fe2 53 #define __USED __attribute__((used))
Pawel Zarembski 0:01f31e923fe2 54 #endif
Pawel Zarembski 0:01f31e923fe2 55 #ifndef __WEAK
Pawel Zarembski 0:01f31e923fe2 56 #define __WEAK __attribute__((weak))
Pawel Zarembski 0:01f31e923fe2 57 #endif
Pawel Zarembski 0:01f31e923fe2 58 #ifndef __PACKED
Pawel Zarembski 0:01f31e923fe2 59 #define __PACKED __attribute__((packed, aligned(1)))
Pawel Zarembski 0:01f31e923fe2 60 #endif
Pawel Zarembski 0:01f31e923fe2 61 #ifndef __PACKED_STRUCT
Pawel Zarembski 0:01f31e923fe2 62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
Pawel Zarembski 0:01f31e923fe2 63 #endif
Pawel Zarembski 0:01f31e923fe2 64 #ifndef __PACKED_UNION
Pawel Zarembski 0:01f31e923fe2 65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
Pawel Zarembski 0:01f31e923fe2 66 #endif
Pawel Zarembski 0:01f31e923fe2 67 #ifndef __UNALIGNED_UINT32 /* deprecated */
Pawel Zarembski 0:01f31e923fe2 68 #pragma clang diagnostic push
Pawel Zarembski 0:01f31e923fe2 69 #pragma clang diagnostic ignored "-Wpacked"
Pawel Zarembski 0:01f31e923fe2 70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
Pawel Zarembski 0:01f31e923fe2 71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
Pawel Zarembski 0:01f31e923fe2 72 #pragma clang diagnostic pop
Pawel Zarembski 0:01f31e923fe2 73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
Pawel Zarembski 0:01f31e923fe2 74 #endif
Pawel Zarembski 0:01f31e923fe2 75 #ifndef __UNALIGNED_UINT16_WRITE
Pawel Zarembski 0:01f31e923fe2 76 #pragma clang diagnostic push
Pawel Zarembski 0:01f31e923fe2 77 #pragma clang diagnostic ignored "-Wpacked"
Pawel Zarembski 0:01f31e923fe2 78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
Pawel Zarembski 0:01f31e923fe2 79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
Pawel Zarembski 0:01f31e923fe2 80 #pragma clang diagnostic pop
Pawel Zarembski 0:01f31e923fe2 81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
Pawel Zarembski 0:01f31e923fe2 82 #endif
Pawel Zarembski 0:01f31e923fe2 83 #ifndef __UNALIGNED_UINT16_READ
Pawel Zarembski 0:01f31e923fe2 84 #pragma clang diagnostic push
Pawel Zarembski 0:01f31e923fe2 85 #pragma clang diagnostic ignored "-Wpacked"
Pawel Zarembski 0:01f31e923fe2 86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
Pawel Zarembski 0:01f31e923fe2 87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
Pawel Zarembski 0:01f31e923fe2 88 #pragma clang diagnostic pop
Pawel Zarembski 0:01f31e923fe2 89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
Pawel Zarembski 0:01f31e923fe2 90 #endif
Pawel Zarembski 0:01f31e923fe2 91 #ifndef __UNALIGNED_UINT32_WRITE
Pawel Zarembski 0:01f31e923fe2 92 #pragma clang diagnostic push
Pawel Zarembski 0:01f31e923fe2 93 #pragma clang diagnostic ignored "-Wpacked"
Pawel Zarembski 0:01f31e923fe2 94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
Pawel Zarembski 0:01f31e923fe2 95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
Pawel Zarembski 0:01f31e923fe2 96 #pragma clang diagnostic pop
Pawel Zarembski 0:01f31e923fe2 97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
Pawel Zarembski 0:01f31e923fe2 98 #endif
Pawel Zarembski 0:01f31e923fe2 99 #ifndef __UNALIGNED_UINT32_READ
Pawel Zarembski 0:01f31e923fe2 100 #pragma clang diagnostic push
Pawel Zarembski 0:01f31e923fe2 101 #pragma clang diagnostic ignored "-Wpacked"
Pawel Zarembski 0:01f31e923fe2 102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
Pawel Zarembski 0:01f31e923fe2 103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
Pawel Zarembski 0:01f31e923fe2 104 #pragma clang diagnostic pop
Pawel Zarembski 0:01f31e923fe2 105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
Pawel Zarembski 0:01f31e923fe2 106 #endif
Pawel Zarembski 0:01f31e923fe2 107 #ifndef __ALIGNED
Pawel Zarembski 0:01f31e923fe2 108 #define __ALIGNED(x) __attribute__((aligned(x)))
Pawel Zarembski 0:01f31e923fe2 109 #endif
Pawel Zarembski 0:01f31e923fe2 110 #ifndef __RESTRICT
Pawel Zarembski 0:01f31e923fe2 111 #define __RESTRICT __restrict
Pawel Zarembski 0:01f31e923fe2 112 #endif
Pawel Zarembski 0:01f31e923fe2 113 #ifndef __COMPILER_BARRIER
Pawel Zarembski 0:01f31e923fe2 114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
Pawel Zarembski 0:01f31e923fe2 115 #endif
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117 /* ######################### Startup and Lowlevel Init ######################## */
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 #ifndef __PROGRAM_START
Pawel Zarembski 0:01f31e923fe2 120 #define __PROGRAM_START __main
Pawel Zarembski 0:01f31e923fe2 121 #endif
Pawel Zarembski 0:01f31e923fe2 122
Pawel Zarembski 0:01f31e923fe2 123 #ifndef __INITIAL_SP
Pawel Zarembski 0:01f31e923fe2 124 #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
Pawel Zarembski 0:01f31e923fe2 125 #endif
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 #ifndef __STACK_LIMIT
Pawel Zarembski 0:01f31e923fe2 128 #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
Pawel Zarembski 0:01f31e923fe2 129 #endif
Pawel Zarembski 0:01f31e923fe2 130
Pawel Zarembski 0:01f31e923fe2 131 #ifndef __VECTOR_TABLE
Pawel Zarembski 0:01f31e923fe2 132 #define __VECTOR_TABLE __Vectors
Pawel Zarembski 0:01f31e923fe2 133 #endif
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135 #ifndef __VECTOR_TABLE_ATTRIBUTE
Pawel Zarembski 0:01f31e923fe2 136 #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
Pawel Zarembski 0:01f31e923fe2 137 #endif
Pawel Zarembski 0:01f31e923fe2 138
Pawel Zarembski 0:01f31e923fe2 139 /* ########################### Core Function Access ########################### */
Pawel Zarembski 0:01f31e923fe2 140 /** \ingroup CMSIS_Core_FunctionInterface
Pawel Zarembski 0:01f31e923fe2 141 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Pawel Zarembski 0:01f31e923fe2 142 @{
Pawel Zarembski 0:01f31e923fe2 143 */
Pawel Zarembski 0:01f31e923fe2 144
Pawel Zarembski 0:01f31e923fe2 145 /**
Pawel Zarembski 0:01f31e923fe2 146 \brief Enable IRQ Interrupts
Pawel Zarembski 0:01f31e923fe2 147 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Pawel Zarembski 0:01f31e923fe2 148 Can only be executed in Privileged modes.
Pawel Zarembski 0:01f31e923fe2 149 */
Pawel Zarembski 0:01f31e923fe2 150 /* intrinsic void __enable_irq(); see arm_compat.h */
Pawel Zarembski 0:01f31e923fe2 151
Pawel Zarembski 0:01f31e923fe2 152
Pawel Zarembski 0:01f31e923fe2 153 /**
Pawel Zarembski 0:01f31e923fe2 154 \brief Disable IRQ Interrupts
Pawel Zarembski 0:01f31e923fe2 155 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
Pawel Zarembski 0:01f31e923fe2 156 Can only be executed in Privileged modes.
Pawel Zarembski 0:01f31e923fe2 157 */
Pawel Zarembski 0:01f31e923fe2 158 /* intrinsic void __disable_irq(); see arm_compat.h */
Pawel Zarembski 0:01f31e923fe2 159
Pawel Zarembski 0:01f31e923fe2 160
Pawel Zarembski 0:01f31e923fe2 161 /**
Pawel Zarembski 0:01f31e923fe2 162 \brief Get Control Register
Pawel Zarembski 0:01f31e923fe2 163 \details Returns the content of the Control Register.
Pawel Zarembski 0:01f31e923fe2 164 \return Control Register value
Pawel Zarembski 0:01f31e923fe2 165 */
Pawel Zarembski 0:01f31e923fe2 166 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
Pawel Zarembski 0:01f31e923fe2 167 {
Pawel Zarembski 0:01f31e923fe2 168 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 169
Pawel Zarembski 0:01f31e923fe2 170 __ASM volatile ("MRS %0, control" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 171 return(result);
Pawel Zarembski 0:01f31e923fe2 172 }
Pawel Zarembski 0:01f31e923fe2 173
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 176 /**
Pawel Zarembski 0:01f31e923fe2 177 \brief Get Control Register (non-secure)
Pawel Zarembski 0:01f31e923fe2 178 \details Returns the content of the non-secure Control Register when in secure mode.
Pawel Zarembski 0:01f31e923fe2 179 \return non-secure Control Register value
Pawel Zarembski 0:01f31e923fe2 180 */
Pawel Zarembski 0:01f31e923fe2 181 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
Pawel Zarembski 0:01f31e923fe2 182 {
Pawel Zarembski 0:01f31e923fe2 183 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 184
Pawel Zarembski 0:01f31e923fe2 185 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 186 return(result);
Pawel Zarembski 0:01f31e923fe2 187 }
Pawel Zarembski 0:01f31e923fe2 188 #endif
Pawel Zarembski 0:01f31e923fe2 189
Pawel Zarembski 0:01f31e923fe2 190
Pawel Zarembski 0:01f31e923fe2 191 /**
Pawel Zarembski 0:01f31e923fe2 192 \brief Set Control Register
Pawel Zarembski 0:01f31e923fe2 193 \details Writes the given value to the Control Register.
Pawel Zarembski 0:01f31e923fe2 194 \param [in] control Control Register value to set
Pawel Zarembski 0:01f31e923fe2 195 */
Pawel Zarembski 0:01f31e923fe2 196 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
Pawel Zarembski 0:01f31e923fe2 197 {
Pawel Zarembski 0:01f31e923fe2 198 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
Pawel Zarembski 0:01f31e923fe2 199 }
Pawel Zarembski 0:01f31e923fe2 200
Pawel Zarembski 0:01f31e923fe2 201
Pawel Zarembski 0:01f31e923fe2 202 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 203 /**
Pawel Zarembski 0:01f31e923fe2 204 \brief Set Control Register (non-secure)
Pawel Zarembski 0:01f31e923fe2 205 \details Writes the given value to the non-secure Control Register when in secure state.
Pawel Zarembski 0:01f31e923fe2 206 \param [in] control Control Register value to set
Pawel Zarembski 0:01f31e923fe2 207 */
Pawel Zarembski 0:01f31e923fe2 208 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
Pawel Zarembski 0:01f31e923fe2 209 {
Pawel Zarembski 0:01f31e923fe2 210 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
Pawel Zarembski 0:01f31e923fe2 211 }
Pawel Zarembski 0:01f31e923fe2 212 #endif
Pawel Zarembski 0:01f31e923fe2 213
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215 /**
Pawel Zarembski 0:01f31e923fe2 216 \brief Get IPSR Register
Pawel Zarembski 0:01f31e923fe2 217 \details Returns the content of the IPSR Register.
Pawel Zarembski 0:01f31e923fe2 218 \return IPSR Register value
Pawel Zarembski 0:01f31e923fe2 219 */
Pawel Zarembski 0:01f31e923fe2 220 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
Pawel Zarembski 0:01f31e923fe2 221 {
Pawel Zarembski 0:01f31e923fe2 222 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 223
Pawel Zarembski 0:01f31e923fe2 224 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 225 return(result);
Pawel Zarembski 0:01f31e923fe2 226 }
Pawel Zarembski 0:01f31e923fe2 227
Pawel Zarembski 0:01f31e923fe2 228
Pawel Zarembski 0:01f31e923fe2 229 /**
Pawel Zarembski 0:01f31e923fe2 230 \brief Get APSR Register
Pawel Zarembski 0:01f31e923fe2 231 \details Returns the content of the APSR Register.
Pawel Zarembski 0:01f31e923fe2 232 \return APSR Register value
Pawel Zarembski 0:01f31e923fe2 233 */
Pawel Zarembski 0:01f31e923fe2 234 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
Pawel Zarembski 0:01f31e923fe2 235 {
Pawel Zarembski 0:01f31e923fe2 236 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 237
Pawel Zarembski 0:01f31e923fe2 238 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 239 return(result);
Pawel Zarembski 0:01f31e923fe2 240 }
Pawel Zarembski 0:01f31e923fe2 241
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 /**
Pawel Zarembski 0:01f31e923fe2 244 \brief Get xPSR Register
Pawel Zarembski 0:01f31e923fe2 245 \details Returns the content of the xPSR Register.
Pawel Zarembski 0:01f31e923fe2 246 \return xPSR Register value
Pawel Zarembski 0:01f31e923fe2 247 */
Pawel Zarembski 0:01f31e923fe2 248 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
Pawel Zarembski 0:01f31e923fe2 249 {
Pawel Zarembski 0:01f31e923fe2 250 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 251
Pawel Zarembski 0:01f31e923fe2 252 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 253 return(result);
Pawel Zarembski 0:01f31e923fe2 254 }
Pawel Zarembski 0:01f31e923fe2 255
Pawel Zarembski 0:01f31e923fe2 256
Pawel Zarembski 0:01f31e923fe2 257 /**
Pawel Zarembski 0:01f31e923fe2 258 \brief Get Process Stack Pointer
Pawel Zarembski 0:01f31e923fe2 259 \details Returns the current value of the Process Stack Pointer (PSP).
Pawel Zarembski 0:01f31e923fe2 260 \return PSP Register value
Pawel Zarembski 0:01f31e923fe2 261 */
Pawel Zarembski 0:01f31e923fe2 262 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
Pawel Zarembski 0:01f31e923fe2 263 {
Pawel Zarembski 0:01f31e923fe2 264 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 265
Pawel Zarembski 0:01f31e923fe2 266 __ASM volatile ("MRS %0, psp" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 267 return(result);
Pawel Zarembski 0:01f31e923fe2 268 }
Pawel Zarembski 0:01f31e923fe2 269
Pawel Zarembski 0:01f31e923fe2 270
Pawel Zarembski 0:01f31e923fe2 271 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 272 /**
Pawel Zarembski 0:01f31e923fe2 273 \brief Get Process Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 274 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 275 \return PSP Register value
Pawel Zarembski 0:01f31e923fe2 276 */
Pawel Zarembski 0:01f31e923fe2 277 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
Pawel Zarembski 0:01f31e923fe2 278 {
Pawel Zarembski 0:01f31e923fe2 279 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 280
Pawel Zarembski 0:01f31e923fe2 281 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 282 return(result);
Pawel Zarembski 0:01f31e923fe2 283 }
Pawel Zarembski 0:01f31e923fe2 284 #endif
Pawel Zarembski 0:01f31e923fe2 285
Pawel Zarembski 0:01f31e923fe2 286
Pawel Zarembski 0:01f31e923fe2 287 /**
Pawel Zarembski 0:01f31e923fe2 288 \brief Set Process Stack Pointer
Pawel Zarembski 0:01f31e923fe2 289 \details Assigns the given value to the Process Stack Pointer (PSP).
Pawel Zarembski 0:01f31e923fe2 290 \param [in] topOfProcStack Process Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 291 */
Pawel Zarembski 0:01f31e923fe2 292 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
Pawel Zarembski 0:01f31e923fe2 293 {
Pawel Zarembski 0:01f31e923fe2 294 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
Pawel Zarembski 0:01f31e923fe2 295 }
Pawel Zarembski 0:01f31e923fe2 296
Pawel Zarembski 0:01f31e923fe2 297
Pawel Zarembski 0:01f31e923fe2 298 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 299 /**
Pawel Zarembski 0:01f31e923fe2 300 \brief Set Process Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 301 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 302 \param [in] topOfProcStack Process Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 303 */
Pawel Zarembski 0:01f31e923fe2 304 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
Pawel Zarembski 0:01f31e923fe2 305 {
Pawel Zarembski 0:01f31e923fe2 306 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
Pawel Zarembski 0:01f31e923fe2 307 }
Pawel Zarembski 0:01f31e923fe2 308 #endif
Pawel Zarembski 0:01f31e923fe2 309
Pawel Zarembski 0:01f31e923fe2 310
Pawel Zarembski 0:01f31e923fe2 311 /**
Pawel Zarembski 0:01f31e923fe2 312 \brief Get Main Stack Pointer
Pawel Zarembski 0:01f31e923fe2 313 \details Returns the current value of the Main Stack Pointer (MSP).
Pawel Zarembski 0:01f31e923fe2 314 \return MSP Register value
Pawel Zarembski 0:01f31e923fe2 315 */
Pawel Zarembski 0:01f31e923fe2 316 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
Pawel Zarembski 0:01f31e923fe2 317 {
Pawel Zarembski 0:01f31e923fe2 318 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 319
Pawel Zarembski 0:01f31e923fe2 320 __ASM volatile ("MRS %0, msp" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 321 return(result);
Pawel Zarembski 0:01f31e923fe2 322 }
Pawel Zarembski 0:01f31e923fe2 323
Pawel Zarembski 0:01f31e923fe2 324
Pawel Zarembski 0:01f31e923fe2 325 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 326 /**
Pawel Zarembski 0:01f31e923fe2 327 \brief Get Main Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 328 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 329 \return MSP Register value
Pawel Zarembski 0:01f31e923fe2 330 */
Pawel Zarembski 0:01f31e923fe2 331 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
Pawel Zarembski 0:01f31e923fe2 332 {
Pawel Zarembski 0:01f31e923fe2 333 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 334
Pawel Zarembski 0:01f31e923fe2 335 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 336 return(result);
Pawel Zarembski 0:01f31e923fe2 337 }
Pawel Zarembski 0:01f31e923fe2 338 #endif
Pawel Zarembski 0:01f31e923fe2 339
Pawel Zarembski 0:01f31e923fe2 340
Pawel Zarembski 0:01f31e923fe2 341 /**
Pawel Zarembski 0:01f31e923fe2 342 \brief Set Main Stack Pointer
Pawel Zarembski 0:01f31e923fe2 343 \details Assigns the given value to the Main Stack Pointer (MSP).
Pawel Zarembski 0:01f31e923fe2 344 \param [in] topOfMainStack Main Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 345 */
Pawel Zarembski 0:01f31e923fe2 346 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
Pawel Zarembski 0:01f31e923fe2 347 {
Pawel Zarembski 0:01f31e923fe2 348 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
Pawel Zarembski 0:01f31e923fe2 349 }
Pawel Zarembski 0:01f31e923fe2 350
Pawel Zarembski 0:01f31e923fe2 351
Pawel Zarembski 0:01f31e923fe2 352 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 353 /**
Pawel Zarembski 0:01f31e923fe2 354 \brief Set Main Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 355 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 356 \param [in] topOfMainStack Main Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 357 */
Pawel Zarembski 0:01f31e923fe2 358 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
Pawel Zarembski 0:01f31e923fe2 359 {
Pawel Zarembski 0:01f31e923fe2 360 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
Pawel Zarembski 0:01f31e923fe2 361 }
Pawel Zarembski 0:01f31e923fe2 362 #endif
Pawel Zarembski 0:01f31e923fe2 363
Pawel Zarembski 0:01f31e923fe2 364
Pawel Zarembski 0:01f31e923fe2 365 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 366 /**
Pawel Zarembski 0:01f31e923fe2 367 \brief Get Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 368 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 369 \return SP Register value
Pawel Zarembski 0:01f31e923fe2 370 */
Pawel Zarembski 0:01f31e923fe2 371 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
Pawel Zarembski 0:01f31e923fe2 372 {
Pawel Zarembski 0:01f31e923fe2 373 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 374
Pawel Zarembski 0:01f31e923fe2 375 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 376 return(result);
Pawel Zarembski 0:01f31e923fe2 377 }
Pawel Zarembski 0:01f31e923fe2 378
Pawel Zarembski 0:01f31e923fe2 379
Pawel Zarembski 0:01f31e923fe2 380 /**
Pawel Zarembski 0:01f31e923fe2 381 \brief Set Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 382 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
Pawel Zarembski 0:01f31e923fe2 383 \param [in] topOfStack Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 384 */
Pawel Zarembski 0:01f31e923fe2 385 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
Pawel Zarembski 0:01f31e923fe2 386 {
Pawel Zarembski 0:01f31e923fe2 387 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
Pawel Zarembski 0:01f31e923fe2 388 }
Pawel Zarembski 0:01f31e923fe2 389 #endif
Pawel Zarembski 0:01f31e923fe2 390
Pawel Zarembski 0:01f31e923fe2 391
Pawel Zarembski 0:01f31e923fe2 392 /**
Pawel Zarembski 0:01f31e923fe2 393 \brief Get Priority Mask
Pawel Zarembski 0:01f31e923fe2 394 \details Returns the current state of the priority mask bit from the Priority Mask Register.
Pawel Zarembski 0:01f31e923fe2 395 \return Priority Mask value
Pawel Zarembski 0:01f31e923fe2 396 */
Pawel Zarembski 0:01f31e923fe2 397 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
Pawel Zarembski 0:01f31e923fe2 398 {
Pawel Zarembski 0:01f31e923fe2 399 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 400
Pawel Zarembski 0:01f31e923fe2 401 __ASM volatile ("MRS %0, primask" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 402 return(result);
Pawel Zarembski 0:01f31e923fe2 403 }
Pawel Zarembski 0:01f31e923fe2 404
Pawel Zarembski 0:01f31e923fe2 405
Pawel Zarembski 0:01f31e923fe2 406 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 407 /**
Pawel Zarembski 0:01f31e923fe2 408 \brief Get Priority Mask (non-secure)
Pawel Zarembski 0:01f31e923fe2 409 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
Pawel Zarembski 0:01f31e923fe2 410 \return Priority Mask value
Pawel Zarembski 0:01f31e923fe2 411 */
Pawel Zarembski 0:01f31e923fe2 412 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
Pawel Zarembski 0:01f31e923fe2 413 {
Pawel Zarembski 0:01f31e923fe2 414 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 415
Pawel Zarembski 0:01f31e923fe2 416 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 417 return(result);
Pawel Zarembski 0:01f31e923fe2 418 }
Pawel Zarembski 0:01f31e923fe2 419 #endif
Pawel Zarembski 0:01f31e923fe2 420
Pawel Zarembski 0:01f31e923fe2 421
Pawel Zarembski 0:01f31e923fe2 422 /**
Pawel Zarembski 0:01f31e923fe2 423 \brief Set Priority Mask
Pawel Zarembski 0:01f31e923fe2 424 \details Assigns the given value to the Priority Mask Register.
Pawel Zarembski 0:01f31e923fe2 425 \param [in] priMask Priority Mask
Pawel Zarembski 0:01f31e923fe2 426 */
Pawel Zarembski 0:01f31e923fe2 427 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
Pawel Zarembski 0:01f31e923fe2 428 {
Pawel Zarembski 0:01f31e923fe2 429 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
Pawel Zarembski 0:01f31e923fe2 430 }
Pawel Zarembski 0:01f31e923fe2 431
Pawel Zarembski 0:01f31e923fe2 432
Pawel Zarembski 0:01f31e923fe2 433 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 434 /**
Pawel Zarembski 0:01f31e923fe2 435 \brief Set Priority Mask (non-secure)
Pawel Zarembski 0:01f31e923fe2 436 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
Pawel Zarembski 0:01f31e923fe2 437 \param [in] priMask Priority Mask
Pawel Zarembski 0:01f31e923fe2 438 */
Pawel Zarembski 0:01f31e923fe2 439 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
Pawel Zarembski 0:01f31e923fe2 440 {
Pawel Zarembski 0:01f31e923fe2 441 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
Pawel Zarembski 0:01f31e923fe2 442 }
Pawel Zarembski 0:01f31e923fe2 443 #endif
Pawel Zarembski 0:01f31e923fe2 444
Pawel Zarembski 0:01f31e923fe2 445
Pawel Zarembski 0:01f31e923fe2 446 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 447 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 448 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
Pawel Zarembski 0:01f31e923fe2 449 /**
Pawel Zarembski 0:01f31e923fe2 450 \brief Enable FIQ
Pawel Zarembski 0:01f31e923fe2 451 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Pawel Zarembski 0:01f31e923fe2 452 Can only be executed in Privileged modes.
Pawel Zarembski 0:01f31e923fe2 453 */
Pawel Zarembski 0:01f31e923fe2 454 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
Pawel Zarembski 0:01f31e923fe2 455
Pawel Zarembski 0:01f31e923fe2 456
Pawel Zarembski 0:01f31e923fe2 457 /**
Pawel Zarembski 0:01f31e923fe2 458 \brief Disable FIQ
Pawel Zarembski 0:01f31e923fe2 459 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
Pawel Zarembski 0:01f31e923fe2 460 Can only be executed in Privileged modes.
Pawel Zarembski 0:01f31e923fe2 461 */
Pawel Zarembski 0:01f31e923fe2 462 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
Pawel Zarembski 0:01f31e923fe2 463
Pawel Zarembski 0:01f31e923fe2 464
Pawel Zarembski 0:01f31e923fe2 465 /**
Pawel Zarembski 0:01f31e923fe2 466 \brief Get Base Priority
Pawel Zarembski 0:01f31e923fe2 467 \details Returns the current value of the Base Priority register.
Pawel Zarembski 0:01f31e923fe2 468 \return Base Priority register value
Pawel Zarembski 0:01f31e923fe2 469 */
Pawel Zarembski 0:01f31e923fe2 470 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
Pawel Zarembski 0:01f31e923fe2 471 {
Pawel Zarembski 0:01f31e923fe2 472 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 473
Pawel Zarembski 0:01f31e923fe2 474 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 475 return(result);
Pawel Zarembski 0:01f31e923fe2 476 }
Pawel Zarembski 0:01f31e923fe2 477
Pawel Zarembski 0:01f31e923fe2 478
Pawel Zarembski 0:01f31e923fe2 479 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 480 /**
Pawel Zarembski 0:01f31e923fe2 481 \brief Get Base Priority (non-secure)
Pawel Zarembski 0:01f31e923fe2 482 \details Returns the current value of the non-secure Base Priority register when in secure state.
Pawel Zarembski 0:01f31e923fe2 483 \return Base Priority register value
Pawel Zarembski 0:01f31e923fe2 484 */
Pawel Zarembski 0:01f31e923fe2 485 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
Pawel Zarembski 0:01f31e923fe2 486 {
Pawel Zarembski 0:01f31e923fe2 487 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 488
Pawel Zarembski 0:01f31e923fe2 489 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 490 return(result);
Pawel Zarembski 0:01f31e923fe2 491 }
Pawel Zarembski 0:01f31e923fe2 492 #endif
Pawel Zarembski 0:01f31e923fe2 493
Pawel Zarembski 0:01f31e923fe2 494
Pawel Zarembski 0:01f31e923fe2 495 /**
Pawel Zarembski 0:01f31e923fe2 496 \brief Set Base Priority
Pawel Zarembski 0:01f31e923fe2 497 \details Assigns the given value to the Base Priority register.
Pawel Zarembski 0:01f31e923fe2 498 \param [in] basePri Base Priority value to set
Pawel Zarembski 0:01f31e923fe2 499 */
Pawel Zarembski 0:01f31e923fe2 500 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
Pawel Zarembski 0:01f31e923fe2 501 {
Pawel Zarembski 0:01f31e923fe2 502 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
Pawel Zarembski 0:01f31e923fe2 503 }
Pawel Zarembski 0:01f31e923fe2 504
Pawel Zarembski 0:01f31e923fe2 505
Pawel Zarembski 0:01f31e923fe2 506 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 507 /**
Pawel Zarembski 0:01f31e923fe2 508 \brief Set Base Priority (non-secure)
Pawel Zarembski 0:01f31e923fe2 509 \details Assigns the given value to the non-secure Base Priority register when in secure state.
Pawel Zarembski 0:01f31e923fe2 510 \param [in] basePri Base Priority value to set
Pawel Zarembski 0:01f31e923fe2 511 */
Pawel Zarembski 0:01f31e923fe2 512 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
Pawel Zarembski 0:01f31e923fe2 513 {
Pawel Zarembski 0:01f31e923fe2 514 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
Pawel Zarembski 0:01f31e923fe2 515 }
Pawel Zarembski 0:01f31e923fe2 516 #endif
Pawel Zarembski 0:01f31e923fe2 517
Pawel Zarembski 0:01f31e923fe2 518
Pawel Zarembski 0:01f31e923fe2 519 /**
Pawel Zarembski 0:01f31e923fe2 520 \brief Set Base Priority with condition
Pawel Zarembski 0:01f31e923fe2 521 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
Pawel Zarembski 0:01f31e923fe2 522 or the new value increases the BASEPRI priority level.
Pawel Zarembski 0:01f31e923fe2 523 \param [in] basePri Base Priority value to set
Pawel Zarembski 0:01f31e923fe2 524 */
Pawel Zarembski 0:01f31e923fe2 525 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
Pawel Zarembski 0:01f31e923fe2 526 {
Pawel Zarembski 0:01f31e923fe2 527 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
Pawel Zarembski 0:01f31e923fe2 528 }
Pawel Zarembski 0:01f31e923fe2 529
Pawel Zarembski 0:01f31e923fe2 530
Pawel Zarembski 0:01f31e923fe2 531 /**
Pawel Zarembski 0:01f31e923fe2 532 \brief Get Fault Mask
Pawel Zarembski 0:01f31e923fe2 533 \details Returns the current value of the Fault Mask register.
Pawel Zarembski 0:01f31e923fe2 534 \return Fault Mask register value
Pawel Zarembski 0:01f31e923fe2 535 */
Pawel Zarembski 0:01f31e923fe2 536 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
Pawel Zarembski 0:01f31e923fe2 537 {
Pawel Zarembski 0:01f31e923fe2 538 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 539
Pawel Zarembski 0:01f31e923fe2 540 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 541 return(result);
Pawel Zarembski 0:01f31e923fe2 542 }
Pawel Zarembski 0:01f31e923fe2 543
Pawel Zarembski 0:01f31e923fe2 544
Pawel Zarembski 0:01f31e923fe2 545 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 546 /**
Pawel Zarembski 0:01f31e923fe2 547 \brief Get Fault Mask (non-secure)
Pawel Zarembski 0:01f31e923fe2 548 \details Returns the current value of the non-secure Fault Mask register when in secure state.
Pawel Zarembski 0:01f31e923fe2 549 \return Fault Mask register value
Pawel Zarembski 0:01f31e923fe2 550 */
Pawel Zarembski 0:01f31e923fe2 551 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
Pawel Zarembski 0:01f31e923fe2 552 {
Pawel Zarembski 0:01f31e923fe2 553 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 554
Pawel Zarembski 0:01f31e923fe2 555 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 556 return(result);
Pawel Zarembski 0:01f31e923fe2 557 }
Pawel Zarembski 0:01f31e923fe2 558 #endif
Pawel Zarembski 0:01f31e923fe2 559
Pawel Zarembski 0:01f31e923fe2 560
Pawel Zarembski 0:01f31e923fe2 561 /**
Pawel Zarembski 0:01f31e923fe2 562 \brief Set Fault Mask
Pawel Zarembski 0:01f31e923fe2 563 \details Assigns the given value to the Fault Mask register.
Pawel Zarembski 0:01f31e923fe2 564 \param [in] faultMask Fault Mask value to set
Pawel Zarembski 0:01f31e923fe2 565 */
Pawel Zarembski 0:01f31e923fe2 566 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
Pawel Zarembski 0:01f31e923fe2 567 {
Pawel Zarembski 0:01f31e923fe2 568 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
Pawel Zarembski 0:01f31e923fe2 569 }
Pawel Zarembski 0:01f31e923fe2 570
Pawel Zarembski 0:01f31e923fe2 571
Pawel Zarembski 0:01f31e923fe2 572 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 573 /**
Pawel Zarembski 0:01f31e923fe2 574 \brief Set Fault Mask (non-secure)
Pawel Zarembski 0:01f31e923fe2 575 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
Pawel Zarembski 0:01f31e923fe2 576 \param [in] faultMask Fault Mask value to set
Pawel Zarembski 0:01f31e923fe2 577 */
Pawel Zarembski 0:01f31e923fe2 578 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Pawel Zarembski 0:01f31e923fe2 579 {
Pawel Zarembski 0:01f31e923fe2 580 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
Pawel Zarembski 0:01f31e923fe2 581 }
Pawel Zarembski 0:01f31e923fe2 582 #endif
Pawel Zarembski 0:01f31e923fe2 583
Pawel Zarembski 0:01f31e923fe2 584 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 585 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 586 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 587
Pawel Zarembski 0:01f31e923fe2 588
Pawel Zarembski 0:01f31e923fe2 589 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 590 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
Pawel Zarembski 0:01f31e923fe2 591
Pawel Zarembski 0:01f31e923fe2 592 /**
Pawel Zarembski 0:01f31e923fe2 593 \brief Get Process Stack Pointer Limit
Pawel Zarembski 0:01f31e923fe2 594 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 595 Stack Pointer Limit register hence zero is returned always in non-secure
Pawel Zarembski 0:01f31e923fe2 596 mode.
Pawel Zarembski 0:01f31e923fe2 597
Pawel Zarembski 0:01f31e923fe2 598 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
Pawel Zarembski 0:01f31e923fe2 599 \return PSPLIM Register value
Pawel Zarembski 0:01f31e923fe2 600 */
Pawel Zarembski 0:01f31e923fe2 601 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
Pawel Zarembski 0:01f31e923fe2 602 {
Pawel Zarembski 0:01f31e923fe2 603 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Pawel Zarembski 0:01f31e923fe2 604 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
Pawel Zarembski 0:01f31e923fe2 605 // without main extensions, the non-secure PSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 606 return 0U;
Pawel Zarembski 0:01f31e923fe2 607 #else
Pawel Zarembski 0:01f31e923fe2 608 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 609 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 610 return result;
Pawel Zarembski 0:01f31e923fe2 611 #endif
Pawel Zarembski 0:01f31e923fe2 612 }
Pawel Zarembski 0:01f31e923fe2 613
Pawel Zarembski 0:01f31e923fe2 614 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 615 /**
Pawel Zarembski 0:01f31e923fe2 616 \brief Get Process Stack Pointer Limit (non-secure)
Pawel Zarembski 0:01f31e923fe2 617 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 618 Stack Pointer Limit register hence zero is returned always in non-secure
Pawel Zarembski 0:01f31e923fe2 619 mode.
Pawel Zarembski 0:01f31e923fe2 620
Pawel Zarembski 0:01f31e923fe2 621 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
Pawel Zarembski 0:01f31e923fe2 622 \return PSPLIM Register value
Pawel Zarembski 0:01f31e923fe2 623 */
Pawel Zarembski 0:01f31e923fe2 624 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Pawel Zarembski 0:01f31e923fe2 625 {
Pawel Zarembski 0:01f31e923fe2 626 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Pawel Zarembski 0:01f31e923fe2 627 // without main extensions, the non-secure PSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 628 return 0U;
Pawel Zarembski 0:01f31e923fe2 629 #else
Pawel Zarembski 0:01f31e923fe2 630 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 631 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 632 return result;
Pawel Zarembski 0:01f31e923fe2 633 #endif
Pawel Zarembski 0:01f31e923fe2 634 }
Pawel Zarembski 0:01f31e923fe2 635 #endif
Pawel Zarembski 0:01f31e923fe2 636
Pawel Zarembski 0:01f31e923fe2 637
Pawel Zarembski 0:01f31e923fe2 638 /**
Pawel Zarembski 0:01f31e923fe2 639 \brief Set Process Stack Pointer Limit
Pawel Zarembski 0:01f31e923fe2 640 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 641 Stack Pointer Limit register hence the write is silently ignored in non-secure
Pawel Zarembski 0:01f31e923fe2 642 mode.
Pawel Zarembski 0:01f31e923fe2 643
Pawel Zarembski 0:01f31e923fe2 644 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
Pawel Zarembski 0:01f31e923fe2 645 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
Pawel Zarembski 0:01f31e923fe2 646 */
Pawel Zarembski 0:01f31e923fe2 647 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
Pawel Zarembski 0:01f31e923fe2 648 {
Pawel Zarembski 0:01f31e923fe2 649 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Pawel Zarembski 0:01f31e923fe2 650 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
Pawel Zarembski 0:01f31e923fe2 651 // without main extensions, the non-secure PSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 652 (void)ProcStackPtrLimit;
Pawel Zarembski 0:01f31e923fe2 653 #else
Pawel Zarembski 0:01f31e923fe2 654 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
Pawel Zarembski 0:01f31e923fe2 655 #endif
Pawel Zarembski 0:01f31e923fe2 656 }
Pawel Zarembski 0:01f31e923fe2 657
Pawel Zarembski 0:01f31e923fe2 658
Pawel Zarembski 0:01f31e923fe2 659 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 660 /**
Pawel Zarembski 0:01f31e923fe2 661 \brief Set Process Stack Pointer (non-secure)
Pawel Zarembski 0:01f31e923fe2 662 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 663 Stack Pointer Limit register hence the write is silently ignored in non-secure
Pawel Zarembski 0:01f31e923fe2 664 mode.
Pawel Zarembski 0:01f31e923fe2 665
Pawel Zarembski 0:01f31e923fe2 666 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
Pawel Zarembski 0:01f31e923fe2 667 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
Pawel Zarembski 0:01f31e923fe2 668 */
Pawel Zarembski 0:01f31e923fe2 669 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
Pawel Zarembski 0:01f31e923fe2 670 {
Pawel Zarembski 0:01f31e923fe2 671 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Pawel Zarembski 0:01f31e923fe2 672 // without main extensions, the non-secure PSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 673 (void)ProcStackPtrLimit;
Pawel Zarembski 0:01f31e923fe2 674 #else
Pawel Zarembski 0:01f31e923fe2 675 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
Pawel Zarembski 0:01f31e923fe2 676 #endif
Pawel Zarembski 0:01f31e923fe2 677 }
Pawel Zarembski 0:01f31e923fe2 678 #endif
Pawel Zarembski 0:01f31e923fe2 679
Pawel Zarembski 0:01f31e923fe2 680
Pawel Zarembski 0:01f31e923fe2 681 /**
Pawel Zarembski 0:01f31e923fe2 682 \brief Get Main Stack Pointer Limit
Pawel Zarembski 0:01f31e923fe2 683 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 684 Stack Pointer Limit register hence zero is returned always.
Pawel Zarembski 0:01f31e923fe2 685
Pawel Zarembski 0:01f31e923fe2 686 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
Pawel Zarembski 0:01f31e923fe2 687 \return MSPLIM Register value
Pawel Zarembski 0:01f31e923fe2 688 */
Pawel Zarembski 0:01f31e923fe2 689 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
Pawel Zarembski 0:01f31e923fe2 690 {
Pawel Zarembski 0:01f31e923fe2 691 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Pawel Zarembski 0:01f31e923fe2 692 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
Pawel Zarembski 0:01f31e923fe2 693 // without main extensions, the non-secure MSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 694 return 0U;
Pawel Zarembski 0:01f31e923fe2 695 #else
Pawel Zarembski 0:01f31e923fe2 696 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 697 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 698 return result;
Pawel Zarembski 0:01f31e923fe2 699 #endif
Pawel Zarembski 0:01f31e923fe2 700 }
Pawel Zarembski 0:01f31e923fe2 701
Pawel Zarembski 0:01f31e923fe2 702
Pawel Zarembski 0:01f31e923fe2 703 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 704 /**
Pawel Zarembski 0:01f31e923fe2 705 \brief Get Main Stack Pointer Limit (non-secure)
Pawel Zarembski 0:01f31e923fe2 706 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 707 Stack Pointer Limit register hence zero is returned always.
Pawel Zarembski 0:01f31e923fe2 708
Pawel Zarembski 0:01f31e923fe2 709 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
Pawel Zarembski 0:01f31e923fe2 710 \return MSPLIM Register value
Pawel Zarembski 0:01f31e923fe2 711 */
Pawel Zarembski 0:01f31e923fe2 712 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
Pawel Zarembski 0:01f31e923fe2 713 {
Pawel Zarembski 0:01f31e923fe2 714 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Pawel Zarembski 0:01f31e923fe2 715 // without main extensions, the non-secure MSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 716 return 0U;
Pawel Zarembski 0:01f31e923fe2 717 #else
Pawel Zarembski 0:01f31e923fe2 718 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 719 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
Pawel Zarembski 0:01f31e923fe2 720 return result;
Pawel Zarembski 0:01f31e923fe2 721 #endif
Pawel Zarembski 0:01f31e923fe2 722 }
Pawel Zarembski 0:01f31e923fe2 723 #endif
Pawel Zarembski 0:01f31e923fe2 724
Pawel Zarembski 0:01f31e923fe2 725
Pawel Zarembski 0:01f31e923fe2 726 /**
Pawel Zarembski 0:01f31e923fe2 727 \brief Set Main Stack Pointer Limit
Pawel Zarembski 0:01f31e923fe2 728 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 729 Stack Pointer Limit register hence the write is silently ignored.
Pawel Zarembski 0:01f31e923fe2 730
Pawel Zarembski 0:01f31e923fe2 731 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
Pawel Zarembski 0:01f31e923fe2 732 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
Pawel Zarembski 0:01f31e923fe2 733 */
Pawel Zarembski 0:01f31e923fe2 734 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
Pawel Zarembski 0:01f31e923fe2 735 {
Pawel Zarembski 0:01f31e923fe2 736 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Pawel Zarembski 0:01f31e923fe2 737 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
Pawel Zarembski 0:01f31e923fe2 738 // without main extensions, the non-secure MSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 739 (void)MainStackPtrLimit;
Pawel Zarembski 0:01f31e923fe2 740 #else
Pawel Zarembski 0:01f31e923fe2 741 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
Pawel Zarembski 0:01f31e923fe2 742 #endif
Pawel Zarembski 0:01f31e923fe2 743 }
Pawel Zarembski 0:01f31e923fe2 744
Pawel Zarembski 0:01f31e923fe2 745
Pawel Zarembski 0:01f31e923fe2 746 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
Pawel Zarembski 0:01f31e923fe2 747 /**
Pawel Zarembski 0:01f31e923fe2 748 \brief Set Main Stack Pointer Limit (non-secure)
Pawel Zarembski 0:01f31e923fe2 749 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Pawel Zarembski 0:01f31e923fe2 750 Stack Pointer Limit register hence the write is silently ignored.
Pawel Zarembski 0:01f31e923fe2 751
Pawel Zarembski 0:01f31e923fe2 752 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
Pawel Zarembski 0:01f31e923fe2 753 \param [in] MainStackPtrLimit Main Stack Pointer value to set
Pawel Zarembski 0:01f31e923fe2 754 */
Pawel Zarembski 0:01f31e923fe2 755 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
Pawel Zarembski 0:01f31e923fe2 756 {
Pawel Zarembski 0:01f31e923fe2 757 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Pawel Zarembski 0:01f31e923fe2 758 // without main extensions, the non-secure MSPLIM is RAZ/WI
Pawel Zarembski 0:01f31e923fe2 759 (void)MainStackPtrLimit;
Pawel Zarembski 0:01f31e923fe2 760 #else
Pawel Zarembski 0:01f31e923fe2 761 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
Pawel Zarembski 0:01f31e923fe2 762 #endif
Pawel Zarembski 0:01f31e923fe2 763 }
Pawel Zarembski 0:01f31e923fe2 764 #endif
Pawel Zarembski 0:01f31e923fe2 765
Pawel Zarembski 0:01f31e923fe2 766 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 767 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 768
Pawel Zarembski 0:01f31e923fe2 769 /**
Pawel Zarembski 0:01f31e923fe2 770 \brief Get FPSCR
Pawel Zarembski 0:01f31e923fe2 771 \details Returns the current value of the Floating Point Status/Control register.
Pawel Zarembski 0:01f31e923fe2 772 \return Floating Point Status/Control register value
Pawel Zarembski 0:01f31e923fe2 773 */
Pawel Zarembski 0:01f31e923fe2 774 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
Pawel Zarembski 0:01f31e923fe2 775 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Pawel Zarembski 0:01f31e923fe2 776 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
Pawel Zarembski 0:01f31e923fe2 777 #else
Pawel Zarembski 0:01f31e923fe2 778 #define __get_FPSCR() ((uint32_t)0U)
Pawel Zarembski 0:01f31e923fe2 779 #endif
Pawel Zarembski 0:01f31e923fe2 780
Pawel Zarembski 0:01f31e923fe2 781 /**
Pawel Zarembski 0:01f31e923fe2 782 \brief Set FPSCR
Pawel Zarembski 0:01f31e923fe2 783 \details Assigns the given value to the Floating Point Status/Control register.
Pawel Zarembski 0:01f31e923fe2 784 \param [in] fpscr Floating Point Status/Control value to set
Pawel Zarembski 0:01f31e923fe2 785 */
Pawel Zarembski 0:01f31e923fe2 786 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
Pawel Zarembski 0:01f31e923fe2 787 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Pawel Zarembski 0:01f31e923fe2 788 #define __set_FPSCR __builtin_arm_set_fpscr
Pawel Zarembski 0:01f31e923fe2 789 #else
Pawel Zarembski 0:01f31e923fe2 790 #define __set_FPSCR(x) ((void)(x))
Pawel Zarembski 0:01f31e923fe2 791 #endif
Pawel Zarembski 0:01f31e923fe2 792
Pawel Zarembski 0:01f31e923fe2 793
Pawel Zarembski 0:01f31e923fe2 794 /*@} end of CMSIS_Core_RegAccFunctions */
Pawel Zarembski 0:01f31e923fe2 795
Pawel Zarembski 0:01f31e923fe2 796
Pawel Zarembski 0:01f31e923fe2 797 /* ########################## Core Instruction Access ######################### */
Pawel Zarembski 0:01f31e923fe2 798 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Pawel Zarembski 0:01f31e923fe2 799 Access to dedicated instructions
Pawel Zarembski 0:01f31e923fe2 800 @{
Pawel Zarembski 0:01f31e923fe2 801 */
Pawel Zarembski 0:01f31e923fe2 802
Pawel Zarembski 0:01f31e923fe2 803 /* Define macros for porting to both thumb1 and thumb2.
Pawel Zarembski 0:01f31e923fe2 804 * For thumb1, use low register (r0-r7), specified by constraint "l"
Pawel Zarembski 0:01f31e923fe2 805 * Otherwise, use general registers, specified by constraint "r" */
Pawel Zarembski 0:01f31e923fe2 806 #if defined (__thumb__) && !defined (__thumb2__)
Pawel Zarembski 0:01f31e923fe2 807 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
Pawel Zarembski 0:01f31e923fe2 808 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
Pawel Zarembski 0:01f31e923fe2 809 #define __CMSIS_GCC_USE_REG(r) "l" (r)
Pawel Zarembski 0:01f31e923fe2 810 #else
Pawel Zarembski 0:01f31e923fe2 811 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
Pawel Zarembski 0:01f31e923fe2 812 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
Pawel Zarembski 0:01f31e923fe2 813 #define __CMSIS_GCC_USE_REG(r) "r" (r)
Pawel Zarembski 0:01f31e923fe2 814 #endif
Pawel Zarembski 0:01f31e923fe2 815
Pawel Zarembski 0:01f31e923fe2 816 /**
Pawel Zarembski 0:01f31e923fe2 817 \brief No Operation
Pawel Zarembski 0:01f31e923fe2 818 \details No Operation does nothing. This instruction can be used for code alignment purposes.
Pawel Zarembski 0:01f31e923fe2 819 */
Pawel Zarembski 0:01f31e923fe2 820 #define __NOP __builtin_arm_nop
Pawel Zarembski 0:01f31e923fe2 821
Pawel Zarembski 0:01f31e923fe2 822 /**
Pawel Zarembski 0:01f31e923fe2 823 \brief Wait For Interrupt
Pawel Zarembski 0:01f31e923fe2 824 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
Pawel Zarembski 0:01f31e923fe2 825 */
Pawel Zarembski 0:01f31e923fe2 826 #define __WFI __builtin_arm_wfi
Pawel Zarembski 0:01f31e923fe2 827
Pawel Zarembski 0:01f31e923fe2 828
Pawel Zarembski 0:01f31e923fe2 829 /**
Pawel Zarembski 0:01f31e923fe2 830 \brief Wait For Event
Pawel Zarembski 0:01f31e923fe2 831 \details Wait For Event is a hint instruction that permits the processor to enter
Pawel Zarembski 0:01f31e923fe2 832 a low-power state until one of a number of events occurs.
Pawel Zarembski 0:01f31e923fe2 833 */
Pawel Zarembski 0:01f31e923fe2 834 #define __WFE __builtin_arm_wfe
Pawel Zarembski 0:01f31e923fe2 835
Pawel Zarembski 0:01f31e923fe2 836
Pawel Zarembski 0:01f31e923fe2 837 /**
Pawel Zarembski 0:01f31e923fe2 838 \brief Send Event
Pawel Zarembski 0:01f31e923fe2 839 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Pawel Zarembski 0:01f31e923fe2 840 */
Pawel Zarembski 0:01f31e923fe2 841 #define __SEV __builtin_arm_sev
Pawel Zarembski 0:01f31e923fe2 842
Pawel Zarembski 0:01f31e923fe2 843
Pawel Zarembski 0:01f31e923fe2 844 /**
Pawel Zarembski 0:01f31e923fe2 845 \brief Instruction Synchronization Barrier
Pawel Zarembski 0:01f31e923fe2 846 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
Pawel Zarembski 0:01f31e923fe2 847 so that all instructions following the ISB are fetched from cache or memory,
Pawel Zarembski 0:01f31e923fe2 848 after the instruction has been completed.
Pawel Zarembski 0:01f31e923fe2 849 */
Pawel Zarembski 0:01f31e923fe2 850 #define __ISB() __builtin_arm_isb(0xF)
Pawel Zarembski 0:01f31e923fe2 851
Pawel Zarembski 0:01f31e923fe2 852 /**
Pawel Zarembski 0:01f31e923fe2 853 \brief Data Synchronization Barrier
Pawel Zarembski 0:01f31e923fe2 854 \details Acts as a special kind of Data Memory Barrier.
Pawel Zarembski 0:01f31e923fe2 855 It completes when all explicit memory accesses before this instruction complete.
Pawel Zarembski 0:01f31e923fe2 856 */
Pawel Zarembski 0:01f31e923fe2 857 #define __DSB() __builtin_arm_dsb(0xF)
Pawel Zarembski 0:01f31e923fe2 858
Pawel Zarembski 0:01f31e923fe2 859
Pawel Zarembski 0:01f31e923fe2 860 /**
Pawel Zarembski 0:01f31e923fe2 861 \brief Data Memory Barrier
Pawel Zarembski 0:01f31e923fe2 862 \details Ensures the apparent order of the explicit memory operations before
Pawel Zarembski 0:01f31e923fe2 863 and after the instruction, without ensuring their completion.
Pawel Zarembski 0:01f31e923fe2 864 */
Pawel Zarembski 0:01f31e923fe2 865 #define __DMB() __builtin_arm_dmb(0xF)
Pawel Zarembski 0:01f31e923fe2 866
Pawel Zarembski 0:01f31e923fe2 867
Pawel Zarembski 0:01f31e923fe2 868 /**
Pawel Zarembski 0:01f31e923fe2 869 \brief Reverse byte order (32 bit)
Pawel Zarembski 0:01f31e923fe2 870 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
Pawel Zarembski 0:01f31e923fe2 871 \param [in] value Value to reverse
Pawel Zarembski 0:01f31e923fe2 872 \return Reversed value
Pawel Zarembski 0:01f31e923fe2 873 */
Pawel Zarembski 0:01f31e923fe2 874 #define __REV(value) __builtin_bswap32(value)
Pawel Zarembski 0:01f31e923fe2 875
Pawel Zarembski 0:01f31e923fe2 876
Pawel Zarembski 0:01f31e923fe2 877 /**
Pawel Zarembski 0:01f31e923fe2 878 \brief Reverse byte order (16 bit)
Pawel Zarembski 0:01f31e923fe2 879 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
Pawel Zarembski 0:01f31e923fe2 880 \param [in] value Value to reverse
Pawel Zarembski 0:01f31e923fe2 881 \return Reversed value
Pawel Zarembski 0:01f31e923fe2 882 */
Pawel Zarembski 0:01f31e923fe2 883 #define __REV16(value) __ROR(__REV(value), 16)
Pawel Zarembski 0:01f31e923fe2 884
Pawel Zarembski 0:01f31e923fe2 885
Pawel Zarembski 0:01f31e923fe2 886 /**
Pawel Zarembski 0:01f31e923fe2 887 \brief Reverse byte order (16 bit)
Pawel Zarembski 0:01f31e923fe2 888 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
Pawel Zarembski 0:01f31e923fe2 889 \param [in] value Value to reverse
Pawel Zarembski 0:01f31e923fe2 890 \return Reversed value
Pawel Zarembski 0:01f31e923fe2 891 */
Pawel Zarembski 0:01f31e923fe2 892 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
Pawel Zarembski 0:01f31e923fe2 893
Pawel Zarembski 0:01f31e923fe2 894
Pawel Zarembski 0:01f31e923fe2 895 /**
Pawel Zarembski 0:01f31e923fe2 896 \brief Rotate Right in unsigned value (32 bit)
Pawel Zarembski 0:01f31e923fe2 897 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
Pawel Zarembski 0:01f31e923fe2 898 \param [in] op1 Value to rotate
Pawel Zarembski 0:01f31e923fe2 899 \param [in] op2 Number of Bits to rotate
Pawel Zarembski 0:01f31e923fe2 900 \return Rotated value
Pawel Zarembski 0:01f31e923fe2 901 */
Pawel Zarembski 0:01f31e923fe2 902 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Pawel Zarembski 0:01f31e923fe2 903 {
Pawel Zarembski 0:01f31e923fe2 904 op2 %= 32U;
Pawel Zarembski 0:01f31e923fe2 905 if (op2 == 0U)
Pawel Zarembski 0:01f31e923fe2 906 {
Pawel Zarembski 0:01f31e923fe2 907 return op1;
Pawel Zarembski 0:01f31e923fe2 908 }
Pawel Zarembski 0:01f31e923fe2 909 return (op1 >> op2) | (op1 << (32U - op2));
Pawel Zarembski 0:01f31e923fe2 910 }
Pawel Zarembski 0:01f31e923fe2 911
Pawel Zarembski 0:01f31e923fe2 912
Pawel Zarembski 0:01f31e923fe2 913 /**
Pawel Zarembski 0:01f31e923fe2 914 \brief Breakpoint
Pawel Zarembski 0:01f31e923fe2 915 \details Causes the processor to enter Debug state.
Pawel Zarembski 0:01f31e923fe2 916 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
Pawel Zarembski 0:01f31e923fe2 917 \param [in] value is ignored by the processor.
Pawel Zarembski 0:01f31e923fe2 918 If required, a debugger can use it to store additional information about the breakpoint.
Pawel Zarembski 0:01f31e923fe2 919 */
Pawel Zarembski 0:01f31e923fe2 920 #define __BKPT(value) __ASM volatile ("bkpt "#value)
Pawel Zarembski 0:01f31e923fe2 921
Pawel Zarembski 0:01f31e923fe2 922
Pawel Zarembski 0:01f31e923fe2 923 /**
Pawel Zarembski 0:01f31e923fe2 924 \brief Reverse bit order of value
Pawel Zarembski 0:01f31e923fe2 925 \details Reverses the bit order of the given value.
Pawel Zarembski 0:01f31e923fe2 926 \param [in] value Value to reverse
Pawel Zarembski 0:01f31e923fe2 927 \return Reversed value
Pawel Zarembski 0:01f31e923fe2 928 */
Pawel Zarembski 0:01f31e923fe2 929 #define __RBIT __builtin_arm_rbit
Pawel Zarembski 0:01f31e923fe2 930
Pawel Zarembski 0:01f31e923fe2 931 /**
Pawel Zarembski 0:01f31e923fe2 932 \brief Count leading zeros
Pawel Zarembski 0:01f31e923fe2 933 \details Counts the number of leading zeros of a data value.
Pawel Zarembski 0:01f31e923fe2 934 \param [in] value Value to count the leading zeros
Pawel Zarembski 0:01f31e923fe2 935 \return number of leading zeros in value
Pawel Zarembski 0:01f31e923fe2 936 */
Pawel Zarembski 0:01f31e923fe2 937 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
Pawel Zarembski 0:01f31e923fe2 938 {
Pawel Zarembski 0:01f31e923fe2 939 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
Pawel Zarembski 0:01f31e923fe2 940 __builtin_clz(0) is undefined behaviour, so handle this case specially.
Pawel Zarembski 0:01f31e923fe2 941 This guarantees ARM-compatible results if happening to compile on a non-ARM
Pawel Zarembski 0:01f31e923fe2 942 target, and ensures the compiler doesn't decide to activate any
Pawel Zarembski 0:01f31e923fe2 943 optimisations using the logic "value was passed to __builtin_clz, so it
Pawel Zarembski 0:01f31e923fe2 944 is non-zero".
Pawel Zarembski 0:01f31e923fe2 945 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
Pawel Zarembski 0:01f31e923fe2 946 single CLZ instruction.
Pawel Zarembski 0:01f31e923fe2 947 */
Pawel Zarembski 0:01f31e923fe2 948 if (value == 0U)
Pawel Zarembski 0:01f31e923fe2 949 {
Pawel Zarembski 0:01f31e923fe2 950 return 32U;
Pawel Zarembski 0:01f31e923fe2 951 }
Pawel Zarembski 0:01f31e923fe2 952 return __builtin_clz(value);
Pawel Zarembski 0:01f31e923fe2 953 }
Pawel Zarembski 0:01f31e923fe2 954
Pawel Zarembski 0:01f31e923fe2 955
Pawel Zarembski 0:01f31e923fe2 956 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 957 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 958 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 959 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
Pawel Zarembski 0:01f31e923fe2 960 /**
Pawel Zarembski 0:01f31e923fe2 961 \brief LDR Exclusive (8 bit)
Pawel Zarembski 0:01f31e923fe2 962 \details Executes a exclusive LDR instruction for 8 bit value.
Pawel Zarembski 0:01f31e923fe2 963 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 964 \return value of type uint8_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 965 */
Pawel Zarembski 0:01f31e923fe2 966 #define __LDREXB (uint8_t)__builtin_arm_ldrex
Pawel Zarembski 0:01f31e923fe2 967
Pawel Zarembski 0:01f31e923fe2 968
Pawel Zarembski 0:01f31e923fe2 969 /**
Pawel Zarembski 0:01f31e923fe2 970 \brief LDR Exclusive (16 bit)
Pawel Zarembski 0:01f31e923fe2 971 \details Executes a exclusive LDR instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 972 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 973 \return value of type uint16_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 974 */
Pawel Zarembski 0:01f31e923fe2 975 #define __LDREXH (uint16_t)__builtin_arm_ldrex
Pawel Zarembski 0:01f31e923fe2 976
Pawel Zarembski 0:01f31e923fe2 977
Pawel Zarembski 0:01f31e923fe2 978 /**
Pawel Zarembski 0:01f31e923fe2 979 \brief LDR Exclusive (32 bit)
Pawel Zarembski 0:01f31e923fe2 980 \details Executes a exclusive LDR instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 981 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 982 \return value of type uint32_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 983 */
Pawel Zarembski 0:01f31e923fe2 984 #define __LDREXW (uint32_t)__builtin_arm_ldrex
Pawel Zarembski 0:01f31e923fe2 985
Pawel Zarembski 0:01f31e923fe2 986
Pawel Zarembski 0:01f31e923fe2 987 /**
Pawel Zarembski 0:01f31e923fe2 988 \brief STR Exclusive (8 bit)
Pawel Zarembski 0:01f31e923fe2 989 \details Executes a exclusive STR instruction for 8 bit values.
Pawel Zarembski 0:01f31e923fe2 990 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 991 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 992 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 993 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 994 */
Pawel Zarembski 0:01f31e923fe2 995 #define __STREXB (uint32_t)__builtin_arm_strex
Pawel Zarembski 0:01f31e923fe2 996
Pawel Zarembski 0:01f31e923fe2 997
Pawel Zarembski 0:01f31e923fe2 998 /**
Pawel Zarembski 0:01f31e923fe2 999 \brief STR Exclusive (16 bit)
Pawel Zarembski 0:01f31e923fe2 1000 \details Executes a exclusive STR instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1001 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1002 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1003 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 1004 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 1005 */
Pawel Zarembski 0:01f31e923fe2 1006 #define __STREXH (uint32_t)__builtin_arm_strex
Pawel Zarembski 0:01f31e923fe2 1007
Pawel Zarembski 0:01f31e923fe2 1008
Pawel Zarembski 0:01f31e923fe2 1009 /**
Pawel Zarembski 0:01f31e923fe2 1010 \brief STR Exclusive (32 bit)
Pawel Zarembski 0:01f31e923fe2 1011 \details Executes a exclusive STR instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1012 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1013 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1014 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 1015 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 1016 */
Pawel Zarembski 0:01f31e923fe2 1017 #define __STREXW (uint32_t)__builtin_arm_strex
Pawel Zarembski 0:01f31e923fe2 1018
Pawel Zarembski 0:01f31e923fe2 1019
Pawel Zarembski 0:01f31e923fe2 1020 /**
Pawel Zarembski 0:01f31e923fe2 1021 \brief Remove the exclusive lock
Pawel Zarembski 0:01f31e923fe2 1022 \details Removes the exclusive lock which is created by LDREX.
Pawel Zarembski 0:01f31e923fe2 1023 */
Pawel Zarembski 0:01f31e923fe2 1024 #define __CLREX __builtin_arm_clrex
Pawel Zarembski 0:01f31e923fe2 1025
Pawel Zarembski 0:01f31e923fe2 1026 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1027 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1028 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1029 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 1030
Pawel Zarembski 0:01f31e923fe2 1031
Pawel Zarembski 0:01f31e923fe2 1032 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1033 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1034 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
Pawel Zarembski 0:01f31e923fe2 1035
Pawel Zarembski 0:01f31e923fe2 1036 /**
Pawel Zarembski 0:01f31e923fe2 1037 \brief Signed Saturate
Pawel Zarembski 0:01f31e923fe2 1038 \details Saturates a signed value.
Pawel Zarembski 0:01f31e923fe2 1039 \param [in] value Value to be saturated
Pawel Zarembski 0:01f31e923fe2 1040 \param [in] sat Bit position to saturate to (1..32)
Pawel Zarembski 0:01f31e923fe2 1041 \return Saturated value
Pawel Zarembski 0:01f31e923fe2 1042 */
Pawel Zarembski 0:01f31e923fe2 1043 #define __SSAT __builtin_arm_ssat
Pawel Zarembski 0:01f31e923fe2 1044
Pawel Zarembski 0:01f31e923fe2 1045
Pawel Zarembski 0:01f31e923fe2 1046 /**
Pawel Zarembski 0:01f31e923fe2 1047 \brief Unsigned Saturate
Pawel Zarembski 0:01f31e923fe2 1048 \details Saturates an unsigned value.
Pawel Zarembski 0:01f31e923fe2 1049 \param [in] value Value to be saturated
Pawel Zarembski 0:01f31e923fe2 1050 \param [in] sat Bit position to saturate to (0..31)
Pawel Zarembski 0:01f31e923fe2 1051 \return Saturated value
Pawel Zarembski 0:01f31e923fe2 1052 */
Pawel Zarembski 0:01f31e923fe2 1053 #define __USAT __builtin_arm_usat
Pawel Zarembski 0:01f31e923fe2 1054
Pawel Zarembski 0:01f31e923fe2 1055
Pawel Zarembski 0:01f31e923fe2 1056 /**
Pawel Zarembski 0:01f31e923fe2 1057 \brief Rotate Right with Extend (32 bit)
Pawel Zarembski 0:01f31e923fe2 1058 \details Moves each bit of a bitstring right by one bit.
Pawel Zarembski 0:01f31e923fe2 1059 The carry input is shifted in at the left end of the bitstring.
Pawel Zarembski 0:01f31e923fe2 1060 \param [in] value Value to rotate
Pawel Zarembski 0:01f31e923fe2 1061 \return Rotated value
Pawel Zarembski 0:01f31e923fe2 1062 */
Pawel Zarembski 0:01f31e923fe2 1063 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
Pawel Zarembski 0:01f31e923fe2 1064 {
Pawel Zarembski 0:01f31e923fe2 1065 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1066
Pawel Zarembski 0:01f31e923fe2 1067 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Pawel Zarembski 0:01f31e923fe2 1068 return(result);
Pawel Zarembski 0:01f31e923fe2 1069 }
Pawel Zarembski 0:01f31e923fe2 1070
Pawel Zarembski 0:01f31e923fe2 1071
Pawel Zarembski 0:01f31e923fe2 1072 /**
Pawel Zarembski 0:01f31e923fe2 1073 \brief LDRT Unprivileged (8 bit)
Pawel Zarembski 0:01f31e923fe2 1074 \details Executes a Unprivileged LDRT instruction for 8 bit value.
Pawel Zarembski 0:01f31e923fe2 1075 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1076 \return value of type uint8_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1077 */
Pawel Zarembski 0:01f31e923fe2 1078 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1079 {
Pawel Zarembski 0:01f31e923fe2 1080 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1081
Pawel Zarembski 0:01f31e923fe2 1082 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
Pawel Zarembski 0:01f31e923fe2 1083 return ((uint8_t) result); /* Add explicit type cast here */
Pawel Zarembski 0:01f31e923fe2 1084 }
Pawel Zarembski 0:01f31e923fe2 1085
Pawel Zarembski 0:01f31e923fe2 1086
Pawel Zarembski 0:01f31e923fe2 1087 /**
Pawel Zarembski 0:01f31e923fe2 1088 \brief LDRT Unprivileged (16 bit)
Pawel Zarembski 0:01f31e923fe2 1089 \details Executes a Unprivileged LDRT instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1090 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1091 \return value of type uint16_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1092 */
Pawel Zarembski 0:01f31e923fe2 1093 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1094 {
Pawel Zarembski 0:01f31e923fe2 1095 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1096
Pawel Zarembski 0:01f31e923fe2 1097 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
Pawel Zarembski 0:01f31e923fe2 1098 return ((uint16_t) result); /* Add explicit type cast here */
Pawel Zarembski 0:01f31e923fe2 1099 }
Pawel Zarembski 0:01f31e923fe2 1100
Pawel Zarembski 0:01f31e923fe2 1101
Pawel Zarembski 0:01f31e923fe2 1102 /**
Pawel Zarembski 0:01f31e923fe2 1103 \brief LDRT Unprivileged (32 bit)
Pawel Zarembski 0:01f31e923fe2 1104 \details Executes a Unprivileged LDRT instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1105 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1106 \return value of type uint32_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1107 */
Pawel Zarembski 0:01f31e923fe2 1108 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1109 {
Pawel Zarembski 0:01f31e923fe2 1110 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1111
Pawel Zarembski 0:01f31e923fe2 1112 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
Pawel Zarembski 0:01f31e923fe2 1113 return(result);
Pawel Zarembski 0:01f31e923fe2 1114 }
Pawel Zarembski 0:01f31e923fe2 1115
Pawel Zarembski 0:01f31e923fe2 1116
Pawel Zarembski 0:01f31e923fe2 1117 /**
Pawel Zarembski 0:01f31e923fe2 1118 \brief STRT Unprivileged (8 bit)
Pawel Zarembski 0:01f31e923fe2 1119 \details Executes a Unprivileged STRT instruction for 8 bit values.
Pawel Zarembski 0:01f31e923fe2 1120 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1121 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1122 */
Pawel Zarembski 0:01f31e923fe2 1123 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1124 {
Pawel Zarembski 0:01f31e923fe2 1125 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
Pawel Zarembski 0:01f31e923fe2 1126 }
Pawel Zarembski 0:01f31e923fe2 1127
Pawel Zarembski 0:01f31e923fe2 1128
Pawel Zarembski 0:01f31e923fe2 1129 /**
Pawel Zarembski 0:01f31e923fe2 1130 \brief STRT Unprivileged (16 bit)
Pawel Zarembski 0:01f31e923fe2 1131 \details Executes a Unprivileged STRT instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1132 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1133 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1134 */
Pawel Zarembski 0:01f31e923fe2 1135 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1136 {
Pawel Zarembski 0:01f31e923fe2 1137 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
Pawel Zarembski 0:01f31e923fe2 1138 }
Pawel Zarembski 0:01f31e923fe2 1139
Pawel Zarembski 0:01f31e923fe2 1140
Pawel Zarembski 0:01f31e923fe2 1141 /**
Pawel Zarembski 0:01f31e923fe2 1142 \brief STRT Unprivileged (32 bit)
Pawel Zarembski 0:01f31e923fe2 1143 \details Executes a Unprivileged STRT instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1144 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1145 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1146 */
Pawel Zarembski 0:01f31e923fe2 1147 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1148 {
Pawel Zarembski 0:01f31e923fe2 1149 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
Pawel Zarembski 0:01f31e923fe2 1150 }
Pawel Zarembski 0:01f31e923fe2 1151
Pawel Zarembski 0:01f31e923fe2 1152 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1153 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1154 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 1155
Pawel Zarembski 0:01f31e923fe2 1156 /**
Pawel Zarembski 0:01f31e923fe2 1157 \brief Signed Saturate
Pawel Zarembski 0:01f31e923fe2 1158 \details Saturates a signed value.
Pawel Zarembski 0:01f31e923fe2 1159 \param [in] value Value to be saturated
Pawel Zarembski 0:01f31e923fe2 1160 \param [in] sat Bit position to saturate to (1..32)
Pawel Zarembski 0:01f31e923fe2 1161 \return Saturated value
Pawel Zarembski 0:01f31e923fe2 1162 */
Pawel Zarembski 0:01f31e923fe2 1163 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Pawel Zarembski 0:01f31e923fe2 1164 {
Pawel Zarembski 0:01f31e923fe2 1165 if ((sat >= 1U) && (sat <= 32U))
Pawel Zarembski 0:01f31e923fe2 1166 {
Pawel Zarembski 0:01f31e923fe2 1167 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
Pawel Zarembski 0:01f31e923fe2 1168 const int32_t min = -1 - max ;
Pawel Zarembski 0:01f31e923fe2 1169 if (val > max)
Pawel Zarembski 0:01f31e923fe2 1170 {
Pawel Zarembski 0:01f31e923fe2 1171 return max;
Pawel Zarembski 0:01f31e923fe2 1172 }
Pawel Zarembski 0:01f31e923fe2 1173 else if (val < min)
Pawel Zarembski 0:01f31e923fe2 1174 {
Pawel Zarembski 0:01f31e923fe2 1175 return min;
Pawel Zarembski 0:01f31e923fe2 1176 }
Pawel Zarembski 0:01f31e923fe2 1177 }
Pawel Zarembski 0:01f31e923fe2 1178 return val;
Pawel Zarembski 0:01f31e923fe2 1179 }
Pawel Zarembski 0:01f31e923fe2 1180
Pawel Zarembski 0:01f31e923fe2 1181 /**
Pawel Zarembski 0:01f31e923fe2 1182 \brief Unsigned Saturate
Pawel Zarembski 0:01f31e923fe2 1183 \details Saturates an unsigned value.
Pawel Zarembski 0:01f31e923fe2 1184 \param [in] value Value to be saturated
Pawel Zarembski 0:01f31e923fe2 1185 \param [in] sat Bit position to saturate to (0..31)
Pawel Zarembski 0:01f31e923fe2 1186 \return Saturated value
Pawel Zarembski 0:01f31e923fe2 1187 */
Pawel Zarembski 0:01f31e923fe2 1188 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Pawel Zarembski 0:01f31e923fe2 1189 {
Pawel Zarembski 0:01f31e923fe2 1190 if (sat <= 31U)
Pawel Zarembski 0:01f31e923fe2 1191 {
Pawel Zarembski 0:01f31e923fe2 1192 const uint32_t max = ((1U << sat) - 1U);
Pawel Zarembski 0:01f31e923fe2 1193 if (val > (int32_t)max)
Pawel Zarembski 0:01f31e923fe2 1194 {
Pawel Zarembski 0:01f31e923fe2 1195 return max;
Pawel Zarembski 0:01f31e923fe2 1196 }
Pawel Zarembski 0:01f31e923fe2 1197 else if (val < 0)
Pawel Zarembski 0:01f31e923fe2 1198 {
Pawel Zarembski 0:01f31e923fe2 1199 return 0U;
Pawel Zarembski 0:01f31e923fe2 1200 }
Pawel Zarembski 0:01f31e923fe2 1201 }
Pawel Zarembski 0:01f31e923fe2 1202 return (uint32_t)val;
Pawel Zarembski 0:01f31e923fe2 1203 }
Pawel Zarembski 0:01f31e923fe2 1204
Pawel Zarembski 0:01f31e923fe2 1205 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1206 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1207 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 1208
Pawel Zarembski 0:01f31e923fe2 1209
Pawel Zarembski 0:01f31e923fe2 1210 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1211 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
Pawel Zarembski 0:01f31e923fe2 1212 /**
Pawel Zarembski 0:01f31e923fe2 1213 \brief Load-Acquire (8 bit)
Pawel Zarembski 0:01f31e923fe2 1214 \details Executes a LDAB instruction for 8 bit value.
Pawel Zarembski 0:01f31e923fe2 1215 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1216 \return value of type uint8_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1217 */
Pawel Zarembski 0:01f31e923fe2 1218 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1219 {
Pawel Zarembski 0:01f31e923fe2 1220 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1221
Pawel Zarembski 0:01f31e923fe2 1222 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1223 return ((uint8_t) result);
Pawel Zarembski 0:01f31e923fe2 1224 }
Pawel Zarembski 0:01f31e923fe2 1225
Pawel Zarembski 0:01f31e923fe2 1226
Pawel Zarembski 0:01f31e923fe2 1227 /**
Pawel Zarembski 0:01f31e923fe2 1228 \brief Load-Acquire (16 bit)
Pawel Zarembski 0:01f31e923fe2 1229 \details Executes a LDAH instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1230 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1231 \return value of type uint16_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1232 */
Pawel Zarembski 0:01f31e923fe2 1233 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1234 {
Pawel Zarembski 0:01f31e923fe2 1235 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1236
Pawel Zarembski 0:01f31e923fe2 1237 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1238 return ((uint16_t) result);
Pawel Zarembski 0:01f31e923fe2 1239 }
Pawel Zarembski 0:01f31e923fe2 1240
Pawel Zarembski 0:01f31e923fe2 1241
Pawel Zarembski 0:01f31e923fe2 1242 /**
Pawel Zarembski 0:01f31e923fe2 1243 \brief Load-Acquire (32 bit)
Pawel Zarembski 0:01f31e923fe2 1244 \details Executes a LDA instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1245 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1246 \return value of type uint32_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1247 */
Pawel Zarembski 0:01f31e923fe2 1248 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1249 {
Pawel Zarembski 0:01f31e923fe2 1250 uint32_t result;
Pawel Zarembski 0:01f31e923fe2 1251
Pawel Zarembski 0:01f31e923fe2 1252 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1253 return(result);
Pawel Zarembski 0:01f31e923fe2 1254 }
Pawel Zarembski 0:01f31e923fe2 1255
Pawel Zarembski 0:01f31e923fe2 1256
Pawel Zarembski 0:01f31e923fe2 1257 /**
Pawel Zarembski 0:01f31e923fe2 1258 \brief Store-Release (8 bit)
Pawel Zarembski 0:01f31e923fe2 1259 \details Executes a STLB instruction for 8 bit values.
Pawel Zarembski 0:01f31e923fe2 1260 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1261 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1262 */
Pawel Zarembski 0:01f31e923fe2 1263 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1264 {
Pawel Zarembski 0:01f31e923fe2 1265 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1266 }
Pawel Zarembski 0:01f31e923fe2 1267
Pawel Zarembski 0:01f31e923fe2 1268
Pawel Zarembski 0:01f31e923fe2 1269 /**
Pawel Zarembski 0:01f31e923fe2 1270 \brief Store-Release (16 bit)
Pawel Zarembski 0:01f31e923fe2 1271 \details Executes a STLH instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1272 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1273 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1274 */
Pawel Zarembski 0:01f31e923fe2 1275 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1276 {
Pawel Zarembski 0:01f31e923fe2 1277 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1278 }
Pawel Zarembski 0:01f31e923fe2 1279
Pawel Zarembski 0:01f31e923fe2 1280
Pawel Zarembski 0:01f31e923fe2 1281 /**
Pawel Zarembski 0:01f31e923fe2 1282 \brief Store-Release (32 bit)
Pawel Zarembski 0:01f31e923fe2 1283 \details Executes a STL instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1284 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1285 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1286 */
Pawel Zarembski 0:01f31e923fe2 1287 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
Pawel Zarembski 0:01f31e923fe2 1288 {
Pawel Zarembski 0:01f31e923fe2 1289 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
Pawel Zarembski 0:01f31e923fe2 1290 }
Pawel Zarembski 0:01f31e923fe2 1291
Pawel Zarembski 0:01f31e923fe2 1292
Pawel Zarembski 0:01f31e923fe2 1293 /**
Pawel Zarembski 0:01f31e923fe2 1294 \brief Load-Acquire Exclusive (8 bit)
Pawel Zarembski 0:01f31e923fe2 1295 \details Executes a LDAB exclusive instruction for 8 bit value.
Pawel Zarembski 0:01f31e923fe2 1296 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1297 \return value of type uint8_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1298 */
Pawel Zarembski 0:01f31e923fe2 1299 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
Pawel Zarembski 0:01f31e923fe2 1300
Pawel Zarembski 0:01f31e923fe2 1301
Pawel Zarembski 0:01f31e923fe2 1302 /**
Pawel Zarembski 0:01f31e923fe2 1303 \brief Load-Acquire Exclusive (16 bit)
Pawel Zarembski 0:01f31e923fe2 1304 \details Executes a LDAH exclusive instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1305 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1306 \return value of type uint16_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1307 */
Pawel Zarembski 0:01f31e923fe2 1308 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
Pawel Zarembski 0:01f31e923fe2 1309
Pawel Zarembski 0:01f31e923fe2 1310
Pawel Zarembski 0:01f31e923fe2 1311 /**
Pawel Zarembski 0:01f31e923fe2 1312 \brief Load-Acquire Exclusive (32 bit)
Pawel Zarembski 0:01f31e923fe2 1313 \details Executes a LDA exclusive instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1314 \param [in] ptr Pointer to data
Pawel Zarembski 0:01f31e923fe2 1315 \return value of type uint32_t at (*ptr)
Pawel Zarembski 0:01f31e923fe2 1316 */
Pawel Zarembski 0:01f31e923fe2 1317 #define __LDAEX (uint32_t)__builtin_arm_ldaex
Pawel Zarembski 0:01f31e923fe2 1318
Pawel Zarembski 0:01f31e923fe2 1319
Pawel Zarembski 0:01f31e923fe2 1320 /**
Pawel Zarembski 0:01f31e923fe2 1321 \brief Store-Release Exclusive (8 bit)
Pawel Zarembski 0:01f31e923fe2 1322 \details Executes a STLB exclusive instruction for 8 bit values.
Pawel Zarembski 0:01f31e923fe2 1323 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1324 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1325 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 1326 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 1327 */
Pawel Zarembski 0:01f31e923fe2 1328 #define __STLEXB (uint32_t)__builtin_arm_stlex
Pawel Zarembski 0:01f31e923fe2 1329
Pawel Zarembski 0:01f31e923fe2 1330
Pawel Zarembski 0:01f31e923fe2 1331 /**
Pawel Zarembski 0:01f31e923fe2 1332 \brief Store-Release Exclusive (16 bit)
Pawel Zarembski 0:01f31e923fe2 1333 \details Executes a STLH exclusive instruction for 16 bit values.
Pawel Zarembski 0:01f31e923fe2 1334 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1335 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1336 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 1337 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 1338 */
Pawel Zarembski 0:01f31e923fe2 1339 #define __STLEXH (uint32_t)__builtin_arm_stlex
Pawel Zarembski 0:01f31e923fe2 1340
Pawel Zarembski 0:01f31e923fe2 1341
Pawel Zarembski 0:01f31e923fe2 1342 /**
Pawel Zarembski 0:01f31e923fe2 1343 \brief Store-Release Exclusive (32 bit)
Pawel Zarembski 0:01f31e923fe2 1344 \details Executes a STL exclusive instruction for 32 bit values.
Pawel Zarembski 0:01f31e923fe2 1345 \param [in] value Value to store
Pawel Zarembski 0:01f31e923fe2 1346 \param [in] ptr Pointer to location
Pawel Zarembski 0:01f31e923fe2 1347 \return 0 Function succeeded
Pawel Zarembski 0:01f31e923fe2 1348 \return 1 Function failed
Pawel Zarembski 0:01f31e923fe2 1349 */
Pawel Zarembski 0:01f31e923fe2 1350 #define __STLEX (uint32_t)__builtin_arm_stlex
Pawel Zarembski 0:01f31e923fe2 1351
Pawel Zarembski 0:01f31e923fe2 1352 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
Pawel Zarembski 0:01f31e923fe2 1353 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
Pawel Zarembski 0:01f31e923fe2 1354
Pawel Zarembski 0:01f31e923fe2 1355 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
Pawel Zarembski 0:01f31e923fe2 1356
Pawel Zarembski 0:01f31e923fe2 1357
Pawel Zarembski 0:01f31e923fe2 1358 /* ################### Compiler specific Intrinsics ########################### */
Pawel Zarembski 0:01f31e923fe2 1359 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Pawel Zarembski 0:01f31e923fe2 1360 Access to dedicated SIMD instructions
Pawel Zarembski 0:01f31e923fe2 1361 @{
Pawel Zarembski 0:01f31e923fe2 1362 */
Pawel Zarembski 0:01f31e923fe2 1363
Pawel Zarembski 0:01f31e923fe2 1364 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
Pawel Zarembski 0:01f31e923fe2 1365
Pawel Zarembski 0:01f31e923fe2 1366 #define __SADD8 __builtin_arm_sadd8
Pawel Zarembski 0:01f31e923fe2 1367 #define __QADD8 __builtin_arm_qadd8
Pawel Zarembski 0:01f31e923fe2 1368 #define __SHADD8 __builtin_arm_shadd8
Pawel Zarembski 0:01f31e923fe2 1369 #define __UADD8 __builtin_arm_uadd8
Pawel Zarembski 0:01f31e923fe2 1370 #define __UQADD8 __builtin_arm_uqadd8
Pawel Zarembski 0:01f31e923fe2 1371 #define __UHADD8 __builtin_arm_uhadd8
Pawel Zarembski 0:01f31e923fe2 1372 #define __SSUB8 __builtin_arm_ssub8
Pawel Zarembski 0:01f31e923fe2 1373 #define __QSUB8 __builtin_arm_qsub8
Pawel Zarembski 0:01f31e923fe2 1374 #define __SHSUB8 __builtin_arm_shsub8
Pawel Zarembski 0:01f31e923fe2 1375 #define __USUB8 __builtin_arm_usub8
Pawel Zarembski 0:01f31e923fe2 1376 #define __UQSUB8 __builtin_arm_uqsub8
Pawel Zarembski 0:01f31e923fe2 1377 #define __UHSUB8 __builtin_arm_uhsub8
Pawel Zarembski 0:01f31e923fe2 1378 #define __SADD16 __builtin_arm_sadd16
Pawel Zarembski 0:01f31e923fe2 1379 #define __QADD16 __builtin_arm_qadd16
Pawel Zarembski 0:01f31e923fe2 1380 #define __SHADD16 __builtin_arm_shadd16
Pawel Zarembski 0:01f31e923fe2 1381 #define __UADD16 __builtin_arm_uadd16
Pawel Zarembski 0:01f31e923fe2 1382 #define __UQADD16 __builtin_arm_uqadd16
Pawel Zarembski 0:01f31e923fe2 1383 #define __UHADD16 __builtin_arm_uhadd16
Pawel Zarembski 0:01f31e923fe2 1384 #define __SSUB16 __builtin_arm_ssub16
Pawel Zarembski 0:01f31e923fe2 1385 #define __QSUB16 __builtin_arm_qsub16
Pawel Zarembski 0:01f31e923fe2 1386 #define __SHSUB16 __builtin_arm_shsub16
Pawel Zarembski 0:01f31e923fe2 1387 #define __USUB16 __builtin_arm_usub16
Pawel Zarembski 0:01f31e923fe2 1388 #define __UQSUB16 __builtin_arm_uqsub16
Pawel Zarembski 0:01f31e923fe2 1389 #define __UHSUB16 __builtin_arm_uhsub16
Pawel Zarembski 0:01f31e923fe2 1390 #define __SASX __builtin_arm_sasx
Pawel Zarembski 0:01f31e923fe2 1391 #define __QASX __builtin_arm_qasx
Pawel Zarembski 0:01f31e923fe2 1392 #define __SHASX __builtin_arm_shasx
Pawel Zarembski 0:01f31e923fe2 1393 #define __UASX __builtin_arm_uasx
Pawel Zarembski 0:01f31e923fe2 1394 #define __UQASX __builtin_arm_uqasx
Pawel Zarembski 0:01f31e923fe2 1395 #define __UHASX __builtin_arm_uhasx
Pawel Zarembski 0:01f31e923fe2 1396 #define __SSAX __builtin_arm_ssax
Pawel Zarembski 0:01f31e923fe2 1397 #define __QSAX __builtin_arm_qsax
Pawel Zarembski 0:01f31e923fe2 1398 #define __SHSAX __builtin_arm_shsax
Pawel Zarembski 0:01f31e923fe2 1399 #define __USAX __builtin_arm_usax
Pawel Zarembski 0:01f31e923fe2 1400 #define __UQSAX __builtin_arm_uqsax
Pawel Zarembski 0:01f31e923fe2 1401 #define __UHSAX __builtin_arm_uhsax
Pawel Zarembski 0:01f31e923fe2 1402 #define __USAD8 __builtin_arm_usad8
Pawel Zarembski 0:01f31e923fe2 1403 #define __USADA8 __builtin_arm_usada8
Pawel Zarembski 0:01f31e923fe2 1404 #define __SSAT16 __builtin_arm_ssat16
Pawel Zarembski 0:01f31e923fe2 1405 #define __USAT16 __builtin_arm_usat16
Pawel Zarembski 0:01f31e923fe2 1406 #define __UXTB16 __builtin_arm_uxtb16
Pawel Zarembski 0:01f31e923fe2 1407 #define __UXTAB16 __builtin_arm_uxtab16
Pawel Zarembski 0:01f31e923fe2 1408 #define __SXTB16 __builtin_arm_sxtb16
Pawel Zarembski 0:01f31e923fe2 1409 #define __SXTAB16 __builtin_arm_sxtab16
Pawel Zarembski 0:01f31e923fe2 1410 #define __SMUAD __builtin_arm_smuad
Pawel Zarembski 0:01f31e923fe2 1411 #define __SMUADX __builtin_arm_smuadx
Pawel Zarembski 0:01f31e923fe2 1412 #define __SMLAD __builtin_arm_smlad
Pawel Zarembski 0:01f31e923fe2 1413 #define __SMLADX __builtin_arm_smladx
Pawel Zarembski 0:01f31e923fe2 1414 #define __SMLALD __builtin_arm_smlald
Pawel Zarembski 0:01f31e923fe2 1415 #define __SMLALDX __builtin_arm_smlaldx
Pawel Zarembski 0:01f31e923fe2 1416 #define __SMUSD __builtin_arm_smusd
Pawel Zarembski 0:01f31e923fe2 1417 #define __SMUSDX __builtin_arm_smusdx
Pawel Zarembski 0:01f31e923fe2 1418 #define __SMLSD __builtin_arm_smlsd
Pawel Zarembski 0:01f31e923fe2 1419 #define __SMLSDX __builtin_arm_smlsdx
Pawel Zarembski 0:01f31e923fe2 1420 #define __SMLSLD __builtin_arm_smlsld
Pawel Zarembski 0:01f31e923fe2 1421 #define __SMLSLDX __builtin_arm_smlsldx
Pawel Zarembski 0:01f31e923fe2 1422 #define __SEL __builtin_arm_sel
Pawel Zarembski 0:01f31e923fe2 1423 #define __QADD __builtin_arm_qadd
Pawel Zarembski 0:01f31e923fe2 1424 #define __QSUB __builtin_arm_qsub
Pawel Zarembski 0:01f31e923fe2 1425
Pawel Zarembski 0:01f31e923fe2 1426 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
Pawel Zarembski 0:01f31e923fe2 1427 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
Pawel Zarembski 0:01f31e923fe2 1428
Pawel Zarembski 0:01f31e923fe2 1429 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
Pawel Zarembski 0:01f31e923fe2 1430 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
Pawel Zarembski 0:01f31e923fe2 1431
Pawel Zarembski 0:01f31e923fe2 1432 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
Pawel Zarembski 0:01f31e923fe2 1433 {
Pawel Zarembski 0:01f31e923fe2 1434 int32_t result;
Pawel Zarembski 0:01f31e923fe2 1435
Pawel Zarembski 0:01f31e923fe2 1436 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
Pawel Zarembski 0:01f31e923fe2 1437 return(result);
Pawel Zarembski 0:01f31e923fe2 1438 }
Pawel Zarembski 0:01f31e923fe2 1439
Pawel Zarembski 0:01f31e923fe2 1440 #endif /* (__ARM_FEATURE_DSP == 1) */
Pawel Zarembski 0:01f31e923fe2 1441 /*@} end of group CMSIS_SIMD_intrinsics */
Pawel Zarembski 0:01f31e923fe2 1442
Pawel Zarembski 0:01f31e923fe2 1443
Pawel Zarembski 0:01f31e923fe2 1444 #endif /* __CMSIS_ARMCLANG_H */