Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/board/override_vbluno51/IO_Config_Override.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file IO_Config_Override.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 /**
Pawel Zarembski 0:01f31e923fe2 23 * The VBLUno51 board use PIO0_9(18) pin for TGT_SWCLK function.
Pawel Zarembski 0:01f31e923fe2 24 * Because it uses RTS/CTS pins for UART Hardware flow control feature.
Pawel Zarembski 0:01f31e923fe2 25 */
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 28 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #include "LPC11Uxx.h"
Pawel Zarembski 0:01f31e923fe2 31 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 // This GPIO configuration is only valid for the LPC11U35 HIC
Pawel Zarembski 0:01f31e923fe2 34 COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35);
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 // Peripheral register bit masks (used for pin inits)
Pawel Zarembski 0:01f31e923fe2 37 #define FUNC_0 0
Pawel Zarembski 0:01f31e923fe2 38 #define FUNC_1 1
Pawel Zarembski 0:01f31e923fe2 39 #define PULL_DOWN_ENABLED (1 << 3)
Pawel Zarembski 0:01f31e923fe2 40 #define PULL_UP_ENABLED (2 << 3)
Pawel Zarembski 0:01f31e923fe2 41 #define OPENDRAIN (1 << 10)
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 // DAP LED PIO0_21
Pawel Zarembski 0:01f31e923fe2 44 #define PIN_DAP_LED_PORT 0
Pawel Zarembski 0:01f31e923fe2 45 #define PIN_DAP_LED_BIT 21
Pawel Zarembski 0:01f31e923fe2 46 #define PIN_DAP_LED (1 << PIN_DAP_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 47 #define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21
Pawel Zarembski 0:01f31e923fe2 48 #define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 49
Pawel Zarembski 0:01f31e923fe2 50 // MSD LED PIO0_20
Pawel Zarembski 0:01f31e923fe2 51 #define PIN_MSD_LED_PORT 0
Pawel Zarembski 0:01f31e923fe2 52 #define PIN_MSD_LED_BIT 20
Pawel Zarembski 0:01f31e923fe2 53 #define PIN_MSD_LED (1 << PIN_MSD_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 54 #define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20
Pawel Zarembski 0:01f31e923fe2 55 #define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 56
Pawel Zarembski 0:01f31e923fe2 57 // CDC LED PIO0_11
Pawel Zarembski 0:01f31e923fe2 58 #define PIN_CDC_LED_PORT 0
Pawel Zarembski 0:01f31e923fe2 59 #define PIN_CDC_LED_BIT 11
Pawel Zarembski 0:01f31e923fe2 60 #define PIN_CDC_LED (1 << PIN_CDC_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 61 #define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11
Pawel Zarembski 0:01f31e923fe2 62 #define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 63
Pawel Zarembski 0:01f31e923fe2 64 // Non-Forwarded Reset in PIN PIO1_19
Pawel Zarembski 0:01f31e923fe2 65 #define PIN_RESET_IN_PORT 1
Pawel Zarembski 0:01f31e923fe2 66 #define PIN_RESET_IN_BIT 19
Pawel Zarembski 0:01f31e923fe2 67 #define PIN_RESET_IN (1 << PIN_RESET_IN_BIT)
Pawel Zarembski 0:01f31e923fe2 68 #define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19
Pawel Zarembski 0:01f31e923fe2 69 #define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 // Forwarded Reset in PIN PIO0_1
Pawel Zarembski 0:01f31e923fe2 72 #define PIN_RESET_IN_FWRD_PORT 0
Pawel Zarembski 0:01f31e923fe2 73 #define PIN_RESET_IN_FWRD_BIT 1
Pawel Zarembski 0:01f31e923fe2 74 #define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT)
Pawel Zarembski 0:01f31e923fe2 75 #define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1
Pawel Zarembski 0:01f31e923fe2 76 #define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 77
Pawel Zarembski 0:01f31e923fe2 78 // nRESET OUT Pin PIO0_2
Pawel Zarembski 0:01f31e923fe2 79 #define PIN_nRESET_PORT 0
Pawel Zarembski 0:01f31e923fe2 80 #define PIN_nRESET_BIT 2
Pawel Zarembski 0:01f31e923fe2 81 #define PIN_nRESET (1 << PIN_nRESET_BIT)
Pawel Zarembski 0:01f31e923fe2 82 #define PIN_nRESET_IOCON LPC_IOCON->PIO0_2
Pawel Zarembski 0:01f31e923fe2 83 #define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 // SWCLK/TCK Pin PIO0_9
Pawel Zarembski 0:01f31e923fe2 86 #define PIN_SWCLK_PORT 0
Pawel Zarembski 0:01f31e923fe2 87 #define PIN_SWCLK_BIT 9
Pawel Zarembski 0:01f31e923fe2 88 #define PIN_SWCLK (1 << PIN_SWCLK_BIT)
Pawel Zarembski 0:01f31e923fe2 89 #define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9
Pawel Zarembski 0:01f31e923fe2 90 #define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 // SWDIO/TMS In/Out Pin PIO0_8
Pawel Zarembski 0:01f31e923fe2 93 #define PIN_SWDIO_PORT 0
Pawel Zarembski 0:01f31e923fe2 94 #define PIN_SWDIO_BIT 8
Pawel Zarembski 0:01f31e923fe2 95 #define PIN_SWDIO (1 << PIN_SWDIO_BIT)
Pawel Zarembski 0:01f31e923fe2 96 #define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8
Pawel Zarembski 0:01f31e923fe2 97 #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 // TDI Pin PIO0_17
Pawel Zarembski 0:01f31e923fe2 100 #define PIN_TDI_PORT 17
Pawel Zarembski 0:01f31e923fe2 101 #define PIN_TDI_BIT 17
Pawel Zarembski 0:01f31e923fe2 102 #define PIN_TDI (1 << PIN_TDI_BIT)
Pawel Zarembski 0:01f31e923fe2 103 #define PIN_TDI_IOCON LPC_IOCON->PIO0_17
Pawel Zarembski 0:01f31e923fe2 104 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 105
Pawel Zarembski 0:01f31e923fe2 106 // SWO/TDO Pin PIO0_9
Pawel Zarembski 0:01f31e923fe2 107 #define PIN_TDO_PORT 9
Pawel Zarembski 0:01f31e923fe2 108 #define PIN_TDO_BIT 9
Pawel Zarembski 0:01f31e923fe2 109 #define PIN_TDO (1 << PIN_TDO_BIT)
Pawel Zarembski 0:01f31e923fe2 110 #define PIN_TDO_IOCON LPC_IOCON->PIO0_9
Pawel Zarembski 0:01f31e923fe2 111 #define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED)
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 #endif