Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/board/musca_a.c@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Pawel Zarembski |
0:01f31e923fe2 | 1 | /** |
Pawel Zarembski |
0:01f31e923fe2 | 2 | * @file musca_a.c |
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0:01f31e923fe2 | 3 | * @brief board ID for the ARM MUSCA A board |
Pawel Zarembski |
0:01f31e923fe2 | 4 | * |
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0:01f31e923fe2 | 5 | * DAPLink Interface Firmware |
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0:01f31e923fe2 | 6 | * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved |
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0:01f31e923fe2 | 7 | * SPDX-License-Identifier: Apache-2.0 |
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0:01f31e923fe2 | 8 | * |
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0:01f31e923fe2 | 9 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
Pawel Zarembski |
0:01f31e923fe2 | 10 | * not use this file except in compliance with the License. |
Pawel Zarembski |
0:01f31e923fe2 | 11 | * You may obtain a copy of the License at |
Pawel Zarembski |
0:01f31e923fe2 | 12 | * |
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0:01f31e923fe2 | 13 | * http://www.apache.org/licenses/LICENSE-2.0 |
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0:01f31e923fe2 | 14 | * |
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0:01f31e923fe2 | 15 | * Unless required by applicable law or agreed to in writing, software |
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0:01f31e923fe2 | 16 | * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
Pawel Zarembski |
0:01f31e923fe2 | 17 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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0:01f31e923fe2 | 18 | * See the License for the specific language governing permissions and |
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0:01f31e923fe2 | 19 | * limitations under the License. |
Pawel Zarembski |
0:01f31e923fe2 | 20 | */ |
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0:01f31e923fe2 | 21 | |
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0:01f31e923fe2 | 22 | #include "stdbool.h" |
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0:01f31e923fe2 | 23 | #include "virtual_fs.h" |
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0:01f31e923fe2 | 24 | #include "flash_manager.h" |
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0:01f31e923fe2 | 25 | #include "IO_Config.h" |
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0:01f31e923fe2 | 26 | #include "target_board.h" |
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0:01f31e923fe2 | 27 | #include "target_family.h" |
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0:01f31e923fe2 | 28 | |
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0:01f31e923fe2 | 29 | void power_on_sequence(void); |
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0:01f31e923fe2 | 30 | |
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0:01f31e923fe2 | 31 | uint8_t gpio_get_pbon_btn() |
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0:01f31e923fe2 | 32 | { |
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0:01f31e923fe2 | 33 | return LPC_GPIO->PIN[PIN_PBON_PORT] & PIN_PBON ? 0 : 1; |
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0:01f31e923fe2 | 34 | } |
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0:01f31e923fe2 | 35 | |
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0:01f31e923fe2 | 36 | static void prerun_board_config(void) |
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0:01f31e923fe2 | 37 | { |
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0:01f31e923fe2 | 38 | /* configure MUSCA specific gpio */ |
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0:01f31e923fe2 | 39 | // configure PBON as input |
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0:01f31e923fe2 | 40 | PIN_PBON_IOCON = PIN_PBON_IOCON_INIT; |
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0:01f31e923fe2 | 41 | LPC_GPIO->DIR[PIN_PBON_PORT] &= ~PIN_PBON; |
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0:01f31e923fe2 | 42 | // configure PSUON as output |
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0:01f31e923fe2 | 43 | PIN_PSUON_IOCON = PIN_PSUON_IOCON_INIT; |
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0:01f31e923fe2 | 44 | LPC_GPIO->CLR[PIN_PSUON_PORT] = PIN_PSUON; |
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0:01f31e923fe2 | 45 | LPC_GPIO->DIR[PIN_PSUON_PORT] |= PIN_PSUON; |
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0:01f31e923fe2 | 46 | // configure SHUTDOWN as input |
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0:01f31e923fe2 | 47 | PIN_SHUTDOWN_IOCON = PIN_SHUTDOWN_IOCON_INIT; |
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0:01f31e923fe2 | 48 | LPC_GPIO->DIR[PIN_SHUTDOWN_PORT] &= ~PIN_SHUTDOWN; |
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0:01f31e923fe2 | 49 | // configure CB_nRST as output |
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0:01f31e923fe2 | 50 | PIN_CB_nRST_IOCON = PIN_CB_nRST_IOCON_INIT; |
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0:01f31e923fe2 | 51 | LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST; |
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0:01f31e923fe2 | 52 | LPC_GPIO->DIR[PIN_CB_nRST_PORT] |= PIN_CB_nRST; |
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0:01f31e923fe2 | 53 | // configure CFG_nRST as output |
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0:01f31e923fe2 | 54 | PIN_CFG_nRST_IOCON = PIN_CFG_nRST_IOCON_INIT; |
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0:01f31e923fe2 | 55 | LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST; |
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0:01f31e923fe2 | 56 | LPC_GPIO->DIR[PIN_CFG_nRST_PORT] |= PIN_CFG_nRST; |
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0:01f31e923fe2 | 57 | // configure SCC_LOAD as output |
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0:01f31e923fe2 | 58 | PIN_SCC_LOAD_IOCON = PIN_SCC_LOAD_IOCON_INIT; |
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0:01f31e923fe2 | 59 | LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD; |
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0:01f31e923fe2 | 60 | LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD; |
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0:01f31e923fe2 | 61 | // configure SCC_WNR as output |
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0:01f31e923fe2 | 62 | PIN_SCC_WNR_IOCON = PIN_SCC_WNR_IOCON_INIT; |
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0:01f31e923fe2 | 63 | LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR; |
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0:01f31e923fe2 | 64 | LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR; |
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0:01f31e923fe2 | 65 | // configure SCC_DATAIN as output |
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0:01f31e923fe2 | 66 | PIN_SCC_DATAIN_IOCON = PIN_SCC_DATAIN_IOCON_INIT; |
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0:01f31e923fe2 | 67 | LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN; |
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0:01f31e923fe2 | 68 | LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN; |
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0:01f31e923fe2 | 69 | // configure SCC_CLK as output |
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0:01f31e923fe2 | 70 | PIN_SCC_CLK_IOCON = PIN_SCC_CLK_IOCON_INIT; |
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0:01f31e923fe2 | 71 | LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK; |
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0:01f31e923fe2 | 72 | LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK; |
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0:01f31e923fe2 | 73 | // configure SCC_DATAOUT as input |
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0:01f31e923fe2 | 74 | PIN_SCC_DATAOUT_IOCON = PIN_SCC_DATAOUT_IOCON_INIT; |
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0:01f31e923fe2 | 75 | LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT; |
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0:01f31e923fe2 | 76 | // configure CS_nDET as input |
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0:01f31e923fe2 | 77 | PIN_CS_nDET_IOCON = PIN_CS_nDET_IOCON_INIT; |
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0:01f31e923fe2 | 78 | LPC_GPIO->DIR[PIN_CS_nDET_PORT] &= ~PIN_CS_nDET; |
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0:01f31e923fe2 | 79 | |
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0:01f31e923fe2 | 80 | PIN_USART_IOCON = PIN_USART_IOCON_INIT; |
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0:01f31e923fe2 | 81 | |
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0:01f31e923fe2 | 82 | // Switch on power supply - PSUON |
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0:01f31e923fe2 | 83 | LPC_GPIO->SET[PIN_PSUON_PORT] = PIN_PSUON; |
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0:01f31e923fe2 | 84 | |
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0:01f31e923fe2 | 85 | power_on_sequence(); |
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0:01f31e923fe2 | 86 | |
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0:01f31e923fe2 | 87 | flash_manager_set_page_erase(true); |
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0:01f31e923fe2 | 88 | } |
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0:01f31e923fe2 | 89 | |
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0:01f31e923fe2 | 90 | const board_info_t g_board_info = { |
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0:01f31e923fe2 | 91 | .board_id = "5006", |
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0:01f31e923fe2 | 92 | .daplink_drive_name = "MBED ", |
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0:01f31e923fe2 | 93 | .target_cfg = &target_device, |
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0:01f31e923fe2 | 94 | .prerun_board_config = prerun_board_config, |
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0:01f31e923fe2 | 95 | }; |