ArmfulKST / Mbed 2 deprecated STM32L4323PhasePWM1

One of a selection of programs exploring PWM on the STM32L432

Dependencies:   mbed

main.cpp@0:e39d2e2b668a, 2019-03-26 (annotated)

Committer:
f3d
Date:
Tue Mar 26 12:46:43 2019 +0000
Revision:
0:e39d2e2b668a
Three phase PWM (fixed) with complimentary outputs and dead-time for the STM32L432 Nucleo;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
f3d 0:e39d2e2b668a 1 #include "mbed.h"
f3d 0:e39d2e2b668a 2 #include <stm32l432xx.h>
f3d 0:e39d2e2b668a 3
f3d 0:e39d2e2b668a 4
f3d 0:e39d2e2b668a 5 #define PWM_PERIOD_COUNT 1000
f3d 0:e39d2e2b668a 6
f3d 0:e39d2e2b668a 7 /*
f3d 0:e39d2e2b668a 8 For register definitions see here:
f3d 0:e39d2e2b668a 9 https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
f3d 0:e39d2e2b668a 10 */
f3d 0:e39d2e2b668a 11 // Using the MBED libraries to configure the PWM outputs (its easier than
f3d 0:e39d2e2b668a 12 // calculating all of the register contents by hand)
f3d 0:e39d2e2b668a 13 DigitalOut myled(LED1);
f3d 0:e39d2e2b668a 14 PwmOut PhaATop(PA_8);
f3d 0:e39d2e2b668a 15 PwmOut PhaBTop(PA_9);
f3d 0:e39d2e2b668a 16 PwmOut PhaCTop(PA_10);
f3d 0:e39d2e2b668a 17 PwmOut PhaABottom(PA_7);
f3d 0:e39d2e2b668a 18 PwmOut PhaBBottom(PB_0);
f3d 0:e39d2e2b668a 19 PwmOut PhaCBottom(PB_1);
f3d 0:e39d2e2b668a 20
f3d 0:e39d2e2b668a 21 void initTimer1()
f3d 0:e39d2e2b668a 22 {
f3d 0:e39d2e2b668a 23
f3d 0:e39d2e2b668a 24 TIM1->CR1 = 0; // make sure Counter is disabled before changing configuration
f3d 0:e39d2e2b668a 25 TIM1->CR2 = 0;
f3d 0:e39d2e2b668a 26 TIM1->PSC = 1;
f3d 0:e39d2e2b668a 27 TIM1->ARR = PWM_PERIOD_COUNT;
f3d 0:e39d2e2b668a 28 TIM1->CCR1 = PWM_PERIOD_COUNT/4; // 25% duty
f3d 0:e39d2e2b668a 29 TIM1->CCR2 = PWM_PERIOD_COUNT/2; // 50% duty
f3d 0:e39d2e2b668a 30 TIM1->CCR3 = 3*PWM_PERIOD_COUNT/4; // 75% duty
f3d 0:e39d2e2b668a 31 // Enable complimentary outputs on channels 1 to 3
f3d 0:e39d2e2b668a 32 TIM1->CCER = (1 << 0) + (1 << 2) + (1 << 4) + (1 << 6) + (1 << 8) + (1<<10);
f3d 0:e39d2e2b668a 33 TIM1->SR = 0; // Clear flags.
f3d 0:e39d2e2b668a 34 TIM1->BDTR &= ~(0xff);
f3d 0:e39d2e2b668a 35 TIM1->BDTR |= (127); // set dead time to 127 clock cycles
f3d 0:e39d2e2b668a 36
f3d 0:e39d2e2b668a 37
f3d 0:e39d2e2b668a 38 }
f3d 0:e39d2e2b668a 39
f3d 0:e39d2e2b668a 40 int main() {
f3d 0:e39d2e2b668a 41
f3d 0:e39d2e2b668a 42 initTimer1();
f3d 0:e39d2e2b668a 43 while(1) {
f3d 0:e39d2e2b668a 44
f3d 0:e39d2e2b668a 45 }
f3d 0:e39d2e2b668a 46 }