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Three phase sinusoidal PWM example for the STM32L432 Nucleo
Dependencies: mbed
main.cpp@0:88449c646fbd, 2019-03-26 (annotated)
- Committer:
- f3d
- Date:
- Tue Mar 26 17:33:53 2019 +0000
- Revision:
- 0:88449c646fbd
- Child:
- 1:581901598cda
Three phase sinusoidal PWM for the STM32L432 Nucleo board
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
f3d | 0:88449c646fbd | 1 | #include "mbed.h" |
f3d | 0:88449c646fbd | 2 | #include <stm32l432xx.h> |
f3d | 0:88449c646fbd | 3 | #include "sine.h" |
f3d | 0:88449c646fbd | 4 | /* |
f3d | 0:88449c646fbd | 5 | For register definitions see here: |
f3d | 0:88449c646fbd | 6 | https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h |
f3d | 0:88449c646fbd | 7 | */ |
f3d | 0:88449c646fbd | 8 | |
f3d | 0:88449c646fbd | 9 | // Using the MBED libraries to configure the PWM outputs (its easier than |
f3d | 0:88449c646fbd | 10 | // calculating all of the register contents by hand) |
f3d | 0:88449c646fbd | 11 | DigitalOut myled(LED1); |
f3d | 0:88449c646fbd | 12 | PwmOut PhaATop(PA_8); |
f3d | 0:88449c646fbd | 13 | PwmOut PhaBTop(PA_9); |
f3d | 0:88449c646fbd | 14 | PwmOut PhaCTop(PA_10); |
f3d | 0:88449c646fbd | 15 | PwmOut PhaABottom(PA_7); |
f3d | 0:88449c646fbd | 16 | PwmOut PhaBBottom(PB_0); |
f3d | 0:88449c646fbd | 17 | PwmOut PhaCBottom(PB_1); |
f3d | 0:88449c646fbd | 18 | int AIndex=0; |
f3d | 0:88449c646fbd | 19 | int BIndex=90; |
f3d | 0:88449c646fbd | 20 | int CIndex=180; |
f3d | 0:88449c646fbd | 21 | void TimerISR(void) |
f3d | 0:88449c646fbd | 22 | { |
f3d | 0:88449c646fbd | 23 | TIM1->CCR1 = sine_table[AIndex]; |
f3d | 0:88449c646fbd | 24 | TIM1->CCR2 = sine_table[BIndex]; |
f3d | 0:88449c646fbd | 25 | TIM1->CCR3 = sine_table[CIndex]; |
f3d | 0:88449c646fbd | 26 | AIndex++; |
f3d | 0:88449c646fbd | 27 | if (AIndex >= PWM_STEPS) |
f3d | 0:88449c646fbd | 28 | AIndex = 0; |
f3d | 0:88449c646fbd | 29 | BIndex++; |
f3d | 0:88449c646fbd | 30 | if (BIndex >= PWM_STEPS) |
f3d | 0:88449c646fbd | 31 | BIndex = 0; |
f3d | 0:88449c646fbd | 32 | CIndex++; |
f3d | 0:88449c646fbd | 33 | if (CIndex >= PWM_STEPS) |
f3d | 0:88449c646fbd | 34 | CIndex = 0; |
f3d | 0:88449c646fbd | 35 | |
f3d | 0:88449c646fbd | 36 | |
f3d | 0:88449c646fbd | 37 | TIM1->SR &= ~0x3f; // ack the interrupt |
f3d | 0:88449c646fbd | 38 | } |
f3d | 0:88449c646fbd | 39 | void initTimer1() |
f3d | 0:88449c646fbd | 40 | { |
f3d | 0:88449c646fbd | 41 | |
f3d | 0:88449c646fbd | 42 | TIM1->CR1 = 0; // make sure Counter is disabled before changing configuration |
f3d | 0:88449c646fbd | 43 | TIM1->CR2 = 0; |
f3d | 0:88449c646fbd | 44 | TIM1->ARR = 270; |
f3d | 0:88449c646fbd | 45 | TIM1->PSC = 21; |
f3d | 0:88449c646fbd | 46 | TIM1->CCR1 = 135; // 50% duty |
f3d | 0:88449c646fbd | 47 | TIM1->CCR2 = 135; // 50% duty |
f3d | 0:88449c646fbd | 48 | TIM1->CCR3 = 135; // 50% duty |
f3d | 0:88449c646fbd | 49 | // Enable complimentary outputs on channels 1 to 3 |
f3d | 0:88449c646fbd | 50 | TIM1->CCER = (1 << 0) + (1 << 2) + (1 << 4) + (1 << 6) + (1 << 8) + (1<<10); |
f3d | 0:88449c646fbd | 51 | TIM1->SR = 0; // Clear flags. |
f3d | 0:88449c646fbd | 52 | //TIM1->BDTR &= ~(0xff); |
f3d | 0:88449c646fbd | 53 | //TIM1->BDTR |= (127); // set dead time to 127 clock cycles |
f3d | 0:88449c646fbd | 54 | // Set up the interrupt handler |
f3d | 0:88449c646fbd | 55 | TIM1->DIER = 1; // Want update interrupt |
f3d | 0:88449c646fbd | 56 | NVIC_SetVector(TIM1_UP_TIM16_IRQn,(uint32_t) TimerISR); |
f3d | 0:88449c646fbd | 57 | NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); |
f3d | 0:88449c646fbd | 58 | __enable_irq(); // enable interrupts */ |
f3d | 0:88449c646fbd | 59 | TIM1->CR1 |= 1; // enable counter |
f3d | 0:88449c646fbd | 60 | |
f3d | 0:88449c646fbd | 61 | } |
f3d | 0:88449c646fbd | 62 | |
f3d | 0:88449c646fbd | 63 | int main() { |
f3d | 0:88449c646fbd | 64 | initTimer1(); |
f3d | 0:88449c646fbd | 65 | while(1) { |
f3d | 0:88449c646fbd | 66 | |
f3d | 0:88449c646fbd | 67 | } |
f3d | 0:88449c646fbd | 68 | } |