ArmfulKST / Mbed 2 deprecated BridgeTest

Uses NucleoL432

Dependencies:   mbed

main.cpp@0:b98f50bdfcd4, 2018-06-05 (annotated)

Committer:
f3d
Date:
Tue Jun 05 09:17:33 2018 +0000
Revision:
0:b98f50bdfcd4
PWM Example for 3 phase bridge (fixed duty);

Who changed what in which revision?

UserRevisionLine numberNew contents of line
f3d 0:b98f50bdfcd4 1 #include "mbed.h"
f3d 0:b98f50bdfcd4 2 #define PWM_PERIOD_COUNT 20000
f3d 0:b98f50bdfcd4 3 /*
f3d 0:b98f50bdfcd4 4 For register definitions see here:
f3d 0:b98f50bdfcd4 5 https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h
f3d 0:b98f50bdfcd4 6 */
f3d 0:b98f50bdfcd4 7 // Using the MBED libraries to configure the PWM outputs (its easier than
f3d 0:b98f50bdfcd4 8 // calculating all of the register contents by hand)
f3d 0:b98f50bdfcd4 9
f3d 0:b98f50bdfcd4 10 PwmOut PhaATop(PA_8);
f3d 0:b98f50bdfcd4 11 PwmOut PhaBTop(PA_9);
f3d 0:b98f50bdfcd4 12 PwmOut PhaCTop(PA_10);
f3d 0:b98f50bdfcd4 13 PwmOut PhaABottom(PA_7);
f3d 0:b98f50bdfcd4 14 PwmOut PhaBBottom(PB_0);
f3d 0:b98f50bdfcd4 15 PwmOut PhaCBottom(PB_1);
f3d 0:b98f50bdfcd4 16
f3d 0:b98f50bdfcd4 17 void TimerISR(void)
f3d 0:b98f50bdfcd4 18 {
f3d 0:b98f50bdfcd4 19
f3d 0:b98f50bdfcd4 20
f3d 0:b98f50bdfcd4 21 TIM1->CCR1 = PWM_PERIOD_COUNT/2;
f3d 0:b98f50bdfcd4 22 TIM1->CCR2 = PWM_PERIOD_COUNT/2;
f3d 0:b98f50bdfcd4 23 TIM1->CCR3 = PWM_PERIOD_COUNT/2;
f3d 0:b98f50bdfcd4 24
f3d 0:b98f50bdfcd4 25 TIM1->SR &= ~0x3f; // ack the interrupt
f3d 0:b98f50bdfcd4 26 }
f3d 0:b98f50bdfcd4 27 void initTimer1()
f3d 0:b98f50bdfcd4 28 {
f3d 0:b98f50bdfcd4 29
f3d 0:b98f50bdfcd4 30 TIM1->CR1 = 0; // make sure Counter is disabled before changing configuration
f3d 0:b98f50bdfcd4 31 TIM1->CR2 = 0;
f3d 0:b98f50bdfcd4 32 TIM1->ARR = PWM_PERIOD_COUNT;
f3d 0:b98f50bdfcd4 33 TIM1->CCR1 = 0; // 0% duty
f3d 0:b98f50bdfcd4 34 TIM1->CCR2 = 0; // 0% duty
f3d 0:b98f50bdfcd4 35 TIM1->CCR3 = 0; // 0% duty
f3d 0:b98f50bdfcd4 36 // Enable complimentary outputs on channels 1 to 3
f3d 0:b98f50bdfcd4 37 TIM1->CCER = (1 << 0) + (1 << 2) + (1 << 4) + (1 << 6) + (1 << 8) + (1<<10);
f3d 0:b98f50bdfcd4 38 TIM1->SR = 0; // Clear flags.
f3d 0:b98f50bdfcd4 39 TIM1->BDTR &= ~(0xff);
f3d 0:b98f50bdfcd4 40 TIM1->BDTR |= (127); // set dead time to 127 clock cycles
f3d 0:b98f50bdfcd4 41 // Set up the interrupt handler
f3d 0:b98f50bdfcd4 42 TIM1->DIER = 1; // Want update interrupt
f3d 0:b98f50bdfcd4 43 NVIC_SetVector(TIM1_UP_TIM16_IRQn,(uint32_t) TimerISR);
f3d 0:b98f50bdfcd4 44 NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
f3d 0:b98f50bdfcd4 45 __enable_irq(); // enable interrupts */
f3d 0:b98f50bdfcd4 46 TIM1->CR1 |= 1; // enable counter
f3d 0:b98f50bdfcd4 47
f3d 0:b98f50bdfcd4 48 }
f3d 0:b98f50bdfcd4 49 int main() {
f3d 0:b98f50bdfcd4 50 initTimer1();
f3d 0:b98f50bdfcd4 51 while(1) {
f3d 0:b98f50bdfcd4 52
f3d 0:b98f50bdfcd4 53 }
f3d 0:b98f50bdfcd4 54 }