Antulio's Team / Mbed 2 deprecated proyecto_bluetoooth

PROYECTO DE DOMOTICA

Dependencies:   mbed Servo DHT11

MFRC522.h@0:8ff600c50722, 2019-05-28 (annotated)

Committer:
jossarr
Date:
Tue May 28 23:33:24 2019 +0000
Revision:
0:8ff600c50722
PROYECTO DE DOMOTICA

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jossarr 0:8ff600c50722 1 /**
jossarr 0:8ff600c50722 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
jossarr 0:8ff600c50722 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
jossarr 0:8ff600c50722 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
jossarr 0:8ff600c50722 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
jossarr 0:8ff600c50722 6 * Ported to mbed by Martin Olejar, Dec, 2013
jossarr 0:8ff600c50722 7 *
jossarr 0:8ff600c50722 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
jossarr 0:8ff600c50722 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
jossarr 0:8ff600c50722 10 *
jossarr 0:8ff600c50722 11 * There are three hardware components involved:
jossarr 0:8ff600c50722 12 * 1) The micro controller: An Arduino
jossarr 0:8ff600c50722 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
jossarr 0:8ff600c50722 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
jossarr 0:8ff600c50722 15 *
jossarr 0:8ff600c50722 16 * The microcontroller and card reader uses SPI for communication.
jossarr 0:8ff600c50722 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
jossarr 0:8ff600c50722 18 *
jossarr 0:8ff600c50722 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
jossarr 0:8ff600c50722 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
jossarr 0:8ff600c50722 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
jossarr 0:8ff600c50722 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
jossarr 0:8ff600c50722 23 *
jossarr 0:8ff600c50722 24 * If only the PICC UID is wanted, the above documents has all the needed information.
jossarr 0:8ff600c50722 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
jossarr 0:8ff600c50722 26 * The MIFARE Classic chips and protocol is described in the datasheets:
jossarr 0:8ff600c50722 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
jossarr 0:8ff600c50722 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
jossarr 0:8ff600c50722 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
jossarr 0:8ff600c50722 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
jossarr 0:8ff600c50722 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
jossarr 0:8ff600c50722 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
jossarr 0:8ff600c50722 33 *
jossarr 0:8ff600c50722 34 * MIFARE Classic 1K (MF1S503x):
jossarr 0:8ff600c50722 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
jossarr 0:8ff600c50722 36 * The blocks are numbered 0-63.
jossarr 0:8ff600c50722 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
jossarr 0:8ff600c50722 38 * Bytes 0-5: Key A
jossarr 0:8ff600c50722 39 * Bytes 6-8: Access Bits
jossarr 0:8ff600c50722 40 * Bytes 9: User data
jossarr 0:8ff600c50722 41 * Bytes 10-15: Key B (or user data)
jossarr 0:8ff600c50722 42 * Block 0 is read only manufacturer data.
jossarr 0:8ff600c50722 43 * To access a block, an authentication using a key from the block's sector must be performed first.
jossarr 0:8ff600c50722 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
jossarr 0:8ff600c50722 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
jossarr 0:8ff600c50722 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
jossarr 0:8ff600c50722 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
jossarr 0:8ff600c50722 48 * MIFARE Classic 4K (MF1S703x):
jossarr 0:8ff600c50722 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
jossarr 0:8ff600c50722 50 * The blocks are numbered 0-255.
jossarr 0:8ff600c50722 51 * The last block in each sector is the Sector Trailer like above.
jossarr 0:8ff600c50722 52 * MIFARE Classic Mini (MF1 IC S20):
jossarr 0:8ff600c50722 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
jossarr 0:8ff600c50722 54 * The blocks are numbered 0-19.
jossarr 0:8ff600c50722 55 * The last block in each sector is the Sector Trailer like above.
jossarr 0:8ff600c50722 56 *
jossarr 0:8ff600c50722 57 * MIFARE Ultralight (MF0ICU1):
jossarr 0:8ff600c50722 58 * Has 16 pages of 4 bytes = 64 bytes.
jossarr 0:8ff600c50722 59 * Pages 0 + 1 is used for the 7-byte UID.
jossarr 0:8ff600c50722 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
jossarr 0:8ff600c50722 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
jossarr 0:8ff600c50722 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
jossarr 0:8ff600c50722 63 * MIFARE Ultralight C (MF0ICU2):
jossarr 0:8ff600c50722 64 * Has 48 pages of 4 bytes = 64 bytes.
jossarr 0:8ff600c50722 65 * Pages 0 + 1 is used for the 7-byte UID.
jossarr 0:8ff600c50722 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
jossarr 0:8ff600c50722 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
jossarr 0:8ff600c50722 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
jossarr 0:8ff600c50722 69 * Page 40 Lock bytes
jossarr 0:8ff600c50722 70 * Page 41 16 bit one way counter
jossarr 0:8ff600c50722 71 * Pages 42-43 Authentication configuration
jossarr 0:8ff600c50722 72 * Pages 44-47 Authentication key
jossarr 0:8ff600c50722 73 */
jossarr 0:8ff600c50722 74 #ifndef MFRC522_h
jossarr 0:8ff600c50722 75 #define MFRC522_h
jossarr 0:8ff600c50722 76
jossarr 0:8ff600c50722 77 #include "mbed.h"
jossarr 0:8ff600c50722 78
jossarr 0:8ff600c50722 79 /**
jossarr 0:8ff600c50722 80 * MFRC522 example
jossarr 0:8ff600c50722 81 *
jossarr 0:8ff600c50722 82 * @code
jossarr 0:8ff600c50722 83 * #include "mbed.h"
jossarr 0:8ff600c50722 84 * #include "MFRC522.h"
jossarr 0:8ff600c50722 85 *
jossarr 0:8ff600c50722 86 * //KL25Z Pins for MFRC522 SPI interface
jossarr 0:8ff600c50722 87 * #define SPI_MOSI PTC6
jossarr 0:8ff600c50722 88 * #define SPI_MISO PTC7
jossarr 0:8ff600c50722 89 * #define SPI_SCLK PTC5
jossarr 0:8ff600c50722 90 * #define SPI_CS PTC4
jossarr 0:8ff600c50722 91 * // KL25Z Pin for MFRC522 reset
jossarr 0:8ff600c50722 92 * #define MF_RESET PTC3
jossarr 0:8ff600c50722 93 * // KL25Z Pins for Debug UART port
jossarr 0:8ff600c50722 94 * #define UART_RX PTA1
jossarr 0:8ff600c50722 95 * #define UART_TX PTA2
jossarr 0:8ff600c50722 96 *
jossarr 0:8ff600c50722 97 * DigitalOut LedRed (LED_RED);
jossarr 0:8ff600c50722 98 * DigitalOut LedGreen (LED_GREEN);
jossarr 0:8ff600c50722 99 *
jossarr 0:8ff600c50722 100 * Serial DebugUART(UART_TX, UART_RX);
jossarr 0:8ff600c50722 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
jossarr 0:8ff600c50722 102 *
jossarr 0:8ff600c50722 103 * int main(void) {
jossarr 0:8ff600c50722 104 * // Set debug UART speed
jossarr 0:8ff600c50722 105 * DebugUART.baud(115200);
jossarr 0:8ff600c50722 106 *
jossarr 0:8ff600c50722 107 * // Init. RC522 Chip
jossarr 0:8ff600c50722 108 * RfChip.PCD_Init();
jossarr 0:8ff600c50722 109 *
jossarr 0:8ff600c50722 110 * while (true) {
jossarr 0:8ff600c50722 111 * LedRed = 1;
jossarr 0:8ff600c50722 112 * LedGreen = 1;
jossarr 0:8ff600c50722 113 *
jossarr 0:8ff600c50722 114 * // Look for new cards
jossarr 0:8ff600c50722 115 * if ( ! RfChip.PICC_IsNewCardPresent())
jossarr 0:8ff600c50722 116 * {
jossarr 0:8ff600c50722 117 * wait_ms(500);
jossarr 0:8ff600c50722 118 * continue;
jossarr 0:8ff600c50722 119 * }
jossarr 0:8ff600c50722 120 *
jossarr 0:8ff600c50722 121 * LedRed = 0;
jossarr 0:8ff600c50722 122 *
jossarr 0:8ff600c50722 123 * // Select one of the cards
jossarr 0:8ff600c50722 124 * if ( ! RfChip.PICC_ReadCardSerial())
jossarr 0:8ff600c50722 125 * {
jossarr 0:8ff600c50722 126 * wait_ms(500);
jossarr 0:8ff600c50722 127 * continue;
jossarr 0:8ff600c50722 128 * }
jossarr 0:8ff600c50722 129 *
jossarr 0:8ff600c50722 130 * LedRed = 1;
jossarr 0:8ff600c50722 131 * LedGreen = 0;
jossarr 0:8ff600c50722 132 *
jossarr 0:8ff600c50722 133 * // Print Card UID
jossarr 0:8ff600c50722 134 * printf("Card UID: ");
jossarr 0:8ff600c50722 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
jossarr 0:8ff600c50722 136 * {
jossarr 0:8ff600c50722 137 * printf(" %X02", RfChip.uid.uidByte[i]);
jossarr 0:8ff600c50722 138 * }
jossarr 0:8ff600c50722 139 * printf("\n\r");
jossarr 0:8ff600c50722 140 *
jossarr 0:8ff600c50722 141 * // Print Card type
jossarr 0:8ff600c50722 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
jossarr 0:8ff600c50722 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
jossarr 0:8ff600c50722 144 * wait_ms(1000);
jossarr 0:8ff600c50722 145 * }
jossarr 0:8ff600c50722 146 * }
jossarr 0:8ff600c50722 147 * @endcode
jossarr 0:8ff600c50722 148 */
jossarr 0:8ff600c50722 149
jossarr 0:8ff600c50722 150 class MFRC522 {
jossarr 0:8ff600c50722 151 public:
jossarr 0:8ff600c50722 152
jossarr 0:8ff600c50722 153 /**
jossarr 0:8ff600c50722 154 * MFRC522 registers (described in chapter 9 of the datasheet).
jossarr 0:8ff600c50722 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
jossarr 0:8ff600c50722 156 */
jossarr 0:8ff600c50722 157 enum PCD_Register {
jossarr 0:8ff600c50722 158 // Page 0: Command and status
jossarr 0:8ff600c50722 159 // 0x00 // reserved for future use
jossarr 0:8ff600c50722 160 CommandReg = 0x01 << 1, // starts and stops command execution
jossarr 0:8ff600c50722 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
jossarr 0:8ff600c50722 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
jossarr 0:8ff600c50722 163 ComIrqReg = 0x04 << 1, // interrupt request bits
jossarr 0:8ff600c50722 164 DivIrqReg = 0x05 << 1, // interrupt request bits
jossarr 0:8ff600c50722 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
jossarr 0:8ff600c50722 166 Status1Reg = 0x07 << 1, // communication status bits
jossarr 0:8ff600c50722 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
jossarr 0:8ff600c50722 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
jossarr 0:8ff600c50722 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
jossarr 0:8ff600c50722 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
jossarr 0:8ff600c50722 171 ControlReg = 0x0C << 1, // miscellaneous control registers
jossarr 0:8ff600c50722 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
jossarr 0:8ff600c50722 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
jossarr 0:8ff600c50722 174 // 0x0F // reserved for future use
jossarr 0:8ff600c50722 175
jossarr 0:8ff600c50722 176 // Page 1:Command
jossarr 0:8ff600c50722 177 // 0x10 // reserved for future use
jossarr 0:8ff600c50722 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
jossarr 0:8ff600c50722 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
jossarr 0:8ff600c50722 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
jossarr 0:8ff600c50722 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
jossarr 0:8ff600c50722 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
jossarr 0:8ff600c50722 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
jossarr 0:8ff600c50722 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
jossarr 0:8ff600c50722 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
jossarr 0:8ff600c50722 186 DemodReg = 0x19 << 1, // defines demodulator settings
jossarr 0:8ff600c50722 187 // 0x1A // reserved for future use
jossarr 0:8ff600c50722 188 // 0x1B // reserved for future use
jossarr 0:8ff600c50722 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
jossarr 0:8ff600c50722 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
jossarr 0:8ff600c50722 191 // 0x1E // reserved for future use
jossarr 0:8ff600c50722 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
jossarr 0:8ff600c50722 193
jossarr 0:8ff600c50722 194 // Page 2: Configuration
jossarr 0:8ff600c50722 195 // 0x20 // reserved for future use
jossarr 0:8ff600c50722 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
jossarr 0:8ff600c50722 197 CRCResultRegL = 0x22 << 1,
jossarr 0:8ff600c50722 198 // 0x23 // reserved for future use
jossarr 0:8ff600c50722 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
jossarr 0:8ff600c50722 200 // 0x25 // reserved for future use
jossarr 0:8ff600c50722 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
jossarr 0:8ff600c50722 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
jossarr 0:8ff600c50722 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
jossarr 0:8ff600c50722 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
jossarr 0:8ff600c50722 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
jossarr 0:8ff600c50722 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
jossarr 0:8ff600c50722 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
jossarr 0:8ff600c50722 208 TReloadRegL = 0x2D << 1,
jossarr 0:8ff600c50722 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
jossarr 0:8ff600c50722 210 TCntValueRegL = 0x2F << 1,
jossarr 0:8ff600c50722 211
jossarr 0:8ff600c50722 212 // Page 3:Test Registers
jossarr 0:8ff600c50722 213 // 0x30 // reserved for future use
jossarr 0:8ff600c50722 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
jossarr 0:8ff600c50722 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
jossarr 0:8ff600c50722 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
jossarr 0:8ff600c50722 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
jossarr 0:8ff600c50722 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
jossarr 0:8ff600c50722 219 AutoTestReg = 0x36 << 1, // controls the digital self test
jossarr 0:8ff600c50722 220 VersionReg = 0x37 << 1, // shows the software version
jossarr 0:8ff600c50722 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
jossarr 0:8ff600c50722 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
jossarr 0:8ff600c50722 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
jossarr 0:8ff600c50722 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
jossarr 0:8ff600c50722 225 // 0x3C // reserved for production tests
jossarr 0:8ff600c50722 226 // 0x3D // reserved for production tests
jossarr 0:8ff600c50722 227 // 0x3E // reserved for production tests
jossarr 0:8ff600c50722 228 // 0x3F // reserved for production tests
jossarr 0:8ff600c50722 229 };
jossarr 0:8ff600c50722 230
jossarr 0:8ff600c50722 231 // MFRC522 commands Described in chapter 10 of the datasheet.
jossarr 0:8ff600c50722 232 enum PCD_Command {
jossarr 0:8ff600c50722 233 PCD_Idle = 0x00, // no action, cancels current command execution
jossarr 0:8ff600c50722 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
jossarr 0:8ff600c50722 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
jossarr 0:8ff600c50722 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
jossarr 0:8ff600c50722 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
jossarr 0:8ff600c50722 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
jossarr 0:8ff600c50722 239 PCD_Receive = 0x08, // activates the receiver circuits
jossarr 0:8ff600c50722 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
jossarr 0:8ff600c50722 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
jossarr 0:8ff600c50722 242 PCD_SoftReset = 0x0F // resets the MFRC522
jossarr 0:8ff600c50722 243 };
jossarr 0:8ff600c50722 244
jossarr 0:8ff600c50722 245 // Commands sent to the PICC.
jossarr 0:8ff600c50722 246 enum PICC_Command {
jossarr 0:8ff600c50722 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
jossarr 0:8ff600c50722 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
jossarr 0:8ff600c50722 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
jossarr 0:8ff600c50722 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
jossarr 0:8ff600c50722 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
jossarr 0:8ff600c50722 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
jossarr 0:8ff600c50722 255
jossarr 0:8ff600c50722 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
jossarr 0:8ff600c50722 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
jossarr 0:8ff600c50722 258 // The read/write commands can also be used for MIFARE Ultralight.
jossarr 0:8ff600c50722 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
jossarr 0:8ff600c50722 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
jossarr 0:8ff600c50722 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
jossarr 0:8ff600c50722 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
jossarr 0:8ff600c50722 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
jossarr 0:8ff600c50722 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
jossarr 0:8ff600c50722 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
jossarr 0:8ff600c50722 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
jossarr 0:8ff600c50722 267
jossarr 0:8ff600c50722 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
jossarr 0:8ff600c50722 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
jossarr 0:8ff600c50722 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
jossarr 0:8ff600c50722 271 };
jossarr 0:8ff600c50722 272
jossarr 0:8ff600c50722 273 // MIFARE constants that does not fit anywhere else
jossarr 0:8ff600c50722 274 enum MIFARE_Misc {
jossarr 0:8ff600c50722 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
jossarr 0:8ff600c50722 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
jossarr 0:8ff600c50722 277 };
jossarr 0:8ff600c50722 278
jossarr 0:8ff600c50722 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
jossarr 0:8ff600c50722 280 enum PICC_Type {
jossarr 0:8ff600c50722 281 PICC_TYPE_UNKNOWN = 0,
jossarr 0:8ff600c50722 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
jossarr 0:8ff600c50722 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
jossarr 0:8ff600c50722 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
jossarr 0:8ff600c50722 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
jossarr 0:8ff600c50722 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
jossarr 0:8ff600c50722 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
jossarr 0:8ff600c50722 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
jossarr 0:8ff600c50722 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
jossarr 0:8ff600c50722 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
jossarr 0:8ff600c50722 291 };
jossarr 0:8ff600c50722 292
jossarr 0:8ff600c50722 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
jossarr 0:8ff600c50722 294 enum StatusCode {
jossarr 0:8ff600c50722 295 STATUS_OK = 1, // Success
jossarr 0:8ff600c50722 296 STATUS_ERROR = 2, // Error in communication
jossarr 0:8ff600c50722 297 STATUS_COLLISION = 3, // Collision detected
jossarr 0:8ff600c50722 298 STATUS_TIMEOUT = 4, // Timeout in communication.
jossarr 0:8ff600c50722 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
jossarr 0:8ff600c50722 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
jossarr 0:8ff600c50722 301 STATUS_INVALID = 7, // Invalid argument.
jossarr 0:8ff600c50722 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
jossarr 0:8ff600c50722 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
jossarr 0:8ff600c50722 304 };
jossarr 0:8ff600c50722 305
jossarr 0:8ff600c50722 306 // A struct used for passing the UID of a PICC.
jossarr 0:8ff600c50722 307 typedef struct {
jossarr 0:8ff600c50722 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
jossarr 0:8ff600c50722 309 uint8_t uidByte[10];
jossarr 0:8ff600c50722 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
jossarr 0:8ff600c50722 311 } Uid;
jossarr 0:8ff600c50722 312
jossarr 0:8ff600c50722 313 // A struct used for passing a MIFARE Crypto1 key
jossarr 0:8ff600c50722 314 typedef struct {
jossarr 0:8ff600c50722 315 uint8_t keyByte[MF_KEY_SIZE];
jossarr 0:8ff600c50722 316 } MIFARE_Key;
jossarr 0:8ff600c50722 317
jossarr 0:8ff600c50722 318 // Member variables
jossarr 0:8ff600c50722 319 Uid uid; // Used by PICC_ReadCardSerial().
jossarr 0:8ff600c50722 320
jossarr 0:8ff600c50722 321 // Size of the MFRC522 FIFO
jossarr 0:8ff600c50722 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
jossarr 0:8ff600c50722 323
jossarr 0:8ff600c50722 324 /**
jossarr 0:8ff600c50722 325 * MFRC522 constructor
jossarr 0:8ff600c50722 326 *
jossarr 0:8ff600c50722 327 * @param mosi SPI MOSI pin
jossarr 0:8ff600c50722 328 * @param miso SPI MISO pin
jossarr 0:8ff600c50722 329 * @param sclk SPI SCLK pin
jossarr 0:8ff600c50722 330 * @param cs SPI CS pin
jossarr 0:8ff600c50722 331 * @param reset Reset pin
jossarr 0:8ff600c50722 332 */
jossarr 0:8ff600c50722 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
jossarr 0:8ff600c50722 334
jossarr 0:8ff600c50722 335 /**
jossarr 0:8ff600c50722 336 * MFRC522 destructor
jossarr 0:8ff600c50722 337 */
jossarr 0:8ff600c50722 338 ~MFRC522();
jossarr 0:8ff600c50722 339
jossarr 0:8ff600c50722 340
jossarr 0:8ff600c50722 341 // ************************************************************************************
jossarr 0:8ff600c50722 342 //! @name Functions for manipulating the MFRC522
jossarr 0:8ff600c50722 343 // ************************************************************************************
jossarr 0:8ff600c50722 344 //@{
jossarr 0:8ff600c50722 345
jossarr 0:8ff600c50722 346 /**
jossarr 0:8ff600c50722 347 * Initializes the MFRC522 chip.
jossarr 0:8ff600c50722 348 */
jossarr 0:8ff600c50722 349 void PCD_Init (void);
jossarr 0:8ff600c50722 350
jossarr 0:8ff600c50722 351 /**
jossarr 0:8ff600c50722 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
jossarr 0:8ff600c50722 353 */
jossarr 0:8ff600c50722 354 void PCD_Reset (void);
jossarr 0:8ff600c50722 355
jossarr 0:8ff600c50722 356 /**
jossarr 0:8ff600c50722 357 * Turns the antenna on by enabling pins TX1 and TX2.
jossarr 0:8ff600c50722 358 * After a reset these pins disabled.
jossarr 0:8ff600c50722 359 */
jossarr 0:8ff600c50722 360 void PCD_AntennaOn (void);
jossarr 0:8ff600c50722 361
jossarr 0:8ff600c50722 362 /**
jossarr 0:8ff600c50722 363 * Writes a byte to the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 364 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 365 *
jossarr 0:8ff600c50722 366 * @param reg The register to write to. One of the PCD_Register enums.
jossarr 0:8ff600c50722 367 * @param value The value to write.
jossarr 0:8ff600c50722 368 */
jossarr 0:8ff600c50722 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
jossarr 0:8ff600c50722 370
jossarr 0:8ff600c50722 371 /**
jossarr 0:8ff600c50722 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 373 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 374 *
jossarr 0:8ff600c50722 375 * @param reg The register to write to. One of the PCD_Register enums.
jossarr 0:8ff600c50722 376 * @param count The number of bytes to write to the register
jossarr 0:8ff600c50722 377 * @param values The values to write. Byte array.
jossarr 0:8ff600c50722 378 */
jossarr 0:8ff600c50722 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
jossarr 0:8ff600c50722 380
jossarr 0:8ff600c50722 381 /**
jossarr 0:8ff600c50722 382 * Reads a byte from the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 383 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 384 *
jossarr 0:8ff600c50722 385 * @param reg The register to read from. One of the PCD_Register enums.
jossarr 0:8ff600c50722 386 * @returns Register value
jossarr 0:8ff600c50722 387 */
jossarr 0:8ff600c50722 388 uint8_t PCD_ReadRegister (uint8_t reg);
jossarr 0:8ff600c50722 389
jossarr 0:8ff600c50722 390 /**
jossarr 0:8ff600c50722 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 392 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 393 *
jossarr 0:8ff600c50722 394 * @param reg The register to read from. One of the PCD_Register enums.
jossarr 0:8ff600c50722 395 * @param count The number of bytes to read.
jossarr 0:8ff600c50722 396 * @param values Byte array to store the values in.
jossarr 0:8ff600c50722 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
jossarr 0:8ff600c50722 398 */
jossarr 0:8ff600c50722 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
jossarr 0:8ff600c50722 400
jossarr 0:8ff600c50722 401 /**
jossarr 0:8ff600c50722 402 * Sets the bits given in mask in register reg.
jossarr 0:8ff600c50722 403 *
jossarr 0:8ff600c50722 404 * @param reg The register to update. One of the PCD_Register enums.
jossarr 0:8ff600c50722 405 * @param mask The bits to set.
jossarr 0:8ff600c50722 406 */
jossarr 0:8ff600c50722 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
jossarr 0:8ff600c50722 408
jossarr 0:8ff600c50722 409 /**
jossarr 0:8ff600c50722 410 * Clears the bits given in mask from register reg.
jossarr 0:8ff600c50722 411 *
jossarr 0:8ff600c50722 412 * @param reg The register to update. One of the PCD_Register enums.
jossarr 0:8ff600c50722 413 * @param mask The bits to clear.
jossarr 0:8ff600c50722 414 */
jossarr 0:8ff600c50722 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
jossarr 0:8ff600c50722 416
jossarr 0:8ff600c50722 417 /**
jossarr 0:8ff600c50722 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
jossarr 0:8ff600c50722 419 *
jossarr 0:8ff600c50722 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
jossarr 0:8ff600c50722 421 * @param length The number of bytes to transfer.
jossarr 0:8ff600c50722 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
jossarr 0:8ff600c50722 423 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 424 */
jossarr 0:8ff600c50722 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
jossarr 0:8ff600c50722 426
jossarr 0:8ff600c50722 427 /**
jossarr 0:8ff600c50722 428 * Executes the Transceive command.
jossarr 0:8ff600c50722 429 * CRC validation can only be done if backData and backLen are specified.
jossarr 0:8ff600c50722 430 *
jossarr 0:8ff600c50722 431 * @param sendData Pointer to the data to transfer to the FIFO.
jossarr 0:8ff600c50722 432 * @param sendLen Number of bytes to transfer to the FIFO.
jossarr 0:8ff600c50722 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
jossarr 0:8ff600c50722 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
jossarr 0:8ff600c50722 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
jossarr 0:8ff600c50722 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
jossarr 0:8ff600c50722 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
jossarr 0:8ff600c50722 438 *
jossarr 0:8ff600c50722 439 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 440 */
jossarr 0:8ff600c50722 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
jossarr 0:8ff600c50722 442 uint8_t sendLen,
jossarr 0:8ff600c50722 443 uint8_t *backData,
jossarr 0:8ff600c50722 444 uint8_t *backLen,
jossarr 0:8ff600c50722 445 uint8_t *validBits = NULL,
jossarr 0:8ff600c50722 446 uint8_t rxAlign = 0,
jossarr 0:8ff600c50722 447 bool checkCRC = false);
jossarr 0:8ff600c50722 448
jossarr 0:8ff600c50722 449
jossarr 0:8ff600c50722 450 /**
jossarr 0:8ff600c50722 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
jossarr 0:8ff600c50722 452 * CRC validation can only be done if backData and backLen are specified.
jossarr 0:8ff600c50722 453 *
jossarr 0:8ff600c50722 454 * @param command The command to execute. One of the PCD_Command enums.
jossarr 0:8ff600c50722 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
jossarr 0:8ff600c50722 456 * @param sendData Pointer to the data to transfer to the FIFO.
jossarr 0:8ff600c50722 457 * @param sendLen Number of bytes to transfer to the FIFO.
jossarr 0:8ff600c50722 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
jossarr 0:8ff600c50722 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
jossarr 0:8ff600c50722 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
jossarr 0:8ff600c50722 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
jossarr 0:8ff600c50722 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
jossarr 0:8ff600c50722 463 *
jossarr 0:8ff600c50722 464 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 465 */
jossarr 0:8ff600c50722 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
jossarr 0:8ff600c50722 467 uint8_t waitIRq,
jossarr 0:8ff600c50722 468 uint8_t *sendData,
jossarr 0:8ff600c50722 469 uint8_t sendLen,
jossarr 0:8ff600c50722 470 uint8_t *backData = NULL,
jossarr 0:8ff600c50722 471 uint8_t *backLen = NULL,
jossarr 0:8ff600c50722 472 uint8_t *validBits = NULL,
jossarr 0:8ff600c50722 473 uint8_t rxAlign = 0,
jossarr 0:8ff600c50722 474 bool checkCRC = false);
jossarr 0:8ff600c50722 475
jossarr 0:8ff600c50722 476 /**
jossarr 0:8ff600c50722 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 479 *
jossarr 0:8ff600c50722 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
jossarr 0:8ff600c50722 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
jossarr 0:8ff600c50722 482 *
jossarr 0:8ff600c50722 483 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 484 */
jossarr 0:8ff600c50722 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
jossarr 0:8ff600c50722 486
jossarr 0:8ff600c50722 487 /**
jossarr 0:8ff600c50722 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 490 *
jossarr 0:8ff600c50722 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
jossarr 0:8ff600c50722 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
jossarr 0:8ff600c50722 493 *
jossarr 0:8ff600c50722 494 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 495 */
jossarr 0:8ff600c50722 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
jossarr 0:8ff600c50722 497
jossarr 0:8ff600c50722 498 /**
jossarr 0:8ff600c50722 499 * Transmits REQA or WUPA commands.
jossarr 0:8ff600c50722 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 501 *
jossarr 0:8ff600c50722 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
jossarr 0:8ff600c50722 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
jossarr 0:8ff600c50722 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
jossarr 0:8ff600c50722 505 *
jossarr 0:8ff600c50722 506 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 507 */
jossarr 0:8ff600c50722 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
jossarr 0:8ff600c50722 509
jossarr 0:8ff600c50722 510 /**
jossarr 0:8ff600c50722 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
jossarr 0:8ff600c50722 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
jossarr 0:8ff600c50722 513 * On success:
jossarr 0:8ff600c50722 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
jossarr 0:8ff600c50722 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
jossarr 0:8ff600c50722 516 *
jossarr 0:8ff600c50722 517 * A PICC UID consists of 4, 7 or 10 bytes.
jossarr 0:8ff600c50722 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
jossarr 0:8ff600c50722 519 *
jossarr 0:8ff600c50722 520 * UID size Number of UID bytes Cascade levels Example of PICC
jossarr 0:8ff600c50722 521 * ======== =================== ============== ===============
jossarr 0:8ff600c50722 522 * single 4 1 MIFARE Classic
jossarr 0:8ff600c50722 523 * double 7 2 MIFARE Ultralight
jossarr 0:8ff600c50722 524 * triple 10 3 Not currently in use?
jossarr 0:8ff600c50722 525 *
jossarr 0:8ff600c50722 526 *
jossarr 0:8ff600c50722 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
jossarr 0:8ff600c50722 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
jossarr 0:8ff600c50722 529 *
jossarr 0:8ff600c50722 530 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 531 */
jossarr 0:8ff600c50722 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
jossarr 0:8ff600c50722 533
jossarr 0:8ff600c50722 534 /**
jossarr 0:8ff600c50722 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
jossarr 0:8ff600c50722 536 *
jossarr 0:8ff600c50722 537 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 538 */
jossarr 0:8ff600c50722 539 uint8_t PICC_HaltA (void);
jossarr 0:8ff600c50722 540
jossarr 0:8ff600c50722 541 // ************************************************************************************
jossarr 0:8ff600c50722 542 //@}
jossarr 0:8ff600c50722 543
jossarr 0:8ff600c50722 544
jossarr 0:8ff600c50722 545 // ************************************************************************************
jossarr 0:8ff600c50722 546 //! @name Functions for communicating with MIFARE PICCs
jossarr 0:8ff600c50722 547 // ************************************************************************************
jossarr 0:8ff600c50722 548 //@{
jossarr 0:8ff600c50722 549
jossarr 0:8ff600c50722 550 /**
jossarr 0:8ff600c50722 551 * Executes the MFRC522 MFAuthent command.
jossarr 0:8ff600c50722 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
jossarr 0:8ff600c50722 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
jossarr 0:8ff600c50722 554 * For use with MIFARE Classic PICCs.
jossarr 0:8ff600c50722 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
jossarr 0:8ff600c50722 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
jossarr 0:8ff600c50722 557 *
jossarr 0:8ff600c50722 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
jossarr 0:8ff600c50722 559 *
jossarr 0:8ff600c50722 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
jossarr 0:8ff600c50722 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
jossarr 0:8ff600c50722 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
jossarr 0:8ff600c50722 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
jossarr 0:8ff600c50722 564 *
jossarr 0:8ff600c50722 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
jossarr 0:8ff600c50722 566 */
jossarr 0:8ff600c50722 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
jossarr 0:8ff600c50722 568
jossarr 0:8ff600c50722 569 /**
jossarr 0:8ff600c50722 570 * Used to exit the PCD from its authenticated state.
jossarr 0:8ff600c50722 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
jossarr 0:8ff600c50722 572 */
jossarr 0:8ff600c50722 573 void PCD_StopCrypto1 (void);
jossarr 0:8ff600c50722 574
jossarr 0:8ff600c50722 575 /**
jossarr 0:8ff600c50722 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
jossarr 0:8ff600c50722 577 *
jossarr 0:8ff600c50722 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 579 *
jossarr 0:8ff600c50722 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
jossarr 0:8ff600c50722 581 * The MF0ICU1 returns a NAK for higher addresses.
jossarr 0:8ff600c50722 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
jossarr 0:8ff600c50722 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
jossarr 0:8ff600c50722 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
jossarr 0:8ff600c50722 585 *
jossarr 0:8ff600c50722 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
jossarr 0:8ff600c50722 587 * Checks the CRC_A before returning STATUS_OK.
jossarr 0:8ff600c50722 588 *
jossarr 0:8ff600c50722 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
jossarr 0:8ff600c50722 590 * @param buffer The buffer to store the data in
jossarr 0:8ff600c50722 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
jossarr 0:8ff600c50722 592 *
jossarr 0:8ff600c50722 593 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 594 */
jossarr 0:8ff600c50722 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
jossarr 0:8ff600c50722 596
jossarr 0:8ff600c50722 597 /**
jossarr 0:8ff600c50722 598 * Writes 16 bytes to the active PICC.
jossarr 0:8ff600c50722 599 *
jossarr 0:8ff600c50722 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 601 *
jossarr 0:8ff600c50722 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
jossarr 0:8ff600c50722 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
jossarr 0:8ff600c50722 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
jossarr 0:8ff600c50722 605 *
jossarr 0:8ff600c50722 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
jossarr 0:8ff600c50722 607 * @param buffer The 16 bytes to write to the PICC
jossarr 0:8ff600c50722 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
jossarr 0:8ff600c50722 609 *
jossarr 0:8ff600c50722 610 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 611 */
jossarr 0:8ff600c50722 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
jossarr 0:8ff600c50722 613
jossarr 0:8ff600c50722 614 /**
jossarr 0:8ff600c50722 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
jossarr 0:8ff600c50722 616 *
jossarr 0:8ff600c50722 617 * @param page The page (2-15) to write to.
jossarr 0:8ff600c50722 618 * @param buffer The 4 bytes to write to the PICC
jossarr 0:8ff600c50722 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
jossarr 0:8ff600c50722 620 *
jossarr 0:8ff600c50722 621 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 622 */
jossarr 0:8ff600c50722 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
jossarr 0:8ff600c50722 624
jossarr 0:8ff600c50722 625 /**
jossarr 0:8ff600c50722 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
jossarr 0:8ff600c50722 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
jossarr 0:8ff600c50722 629 * Use MIFARE_Transfer() to store the result in a block.
jossarr 0:8ff600c50722 630 *
jossarr 0:8ff600c50722 631 * @param blockAddr The block (0-0xff) number.
jossarr 0:8ff600c50722 632 * @param delta This number is subtracted from the value of block blockAddr.
jossarr 0:8ff600c50722 633 *
jossarr 0:8ff600c50722 634 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 635 */
jossarr 0:8ff600c50722 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
jossarr 0:8ff600c50722 637
jossarr 0:8ff600c50722 638 /**
jossarr 0:8ff600c50722 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
jossarr 0:8ff600c50722 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
jossarr 0:8ff600c50722 642 * Use MIFARE_Transfer() to store the result in a block.
jossarr 0:8ff600c50722 643 *
jossarr 0:8ff600c50722 644 * @param blockAddr The block (0-0xff) number.
jossarr 0:8ff600c50722 645 * @param delta This number is added to the value of block blockAddr.
jossarr 0:8ff600c50722 646 *
jossarr 0:8ff600c50722 647 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 648 */
jossarr 0:8ff600c50722 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
jossarr 0:8ff600c50722 650
jossarr 0:8ff600c50722 651 /**
jossarr 0:8ff600c50722 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
jossarr 0:8ff600c50722 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
jossarr 0:8ff600c50722 655 * Use MIFARE_Transfer() to store the result in a block.
jossarr 0:8ff600c50722 656 *
jossarr 0:8ff600c50722 657 * @param blockAddr The block (0-0xff) number.
jossarr 0:8ff600c50722 658 *
jossarr 0:8ff600c50722 659 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 660 */
jossarr 0:8ff600c50722 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
jossarr 0:8ff600c50722 662
jossarr 0:8ff600c50722 663 /**
jossarr 0:8ff600c50722 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
jossarr 0:8ff600c50722 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
jossarr 0:8ff600c50722 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
jossarr 0:8ff600c50722 667 *
jossarr 0:8ff600c50722 668 * @param blockAddr The block (0-0xff) number.
jossarr 0:8ff600c50722 669 *
jossarr 0:8ff600c50722 670 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 671 */
jossarr 0:8ff600c50722 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
jossarr 0:8ff600c50722 673
jossarr 0:8ff600c50722 674 // ************************************************************************************
jossarr 0:8ff600c50722 675 //@}
jossarr 0:8ff600c50722 676
jossarr 0:8ff600c50722 677
jossarr 0:8ff600c50722 678 // ************************************************************************************
jossarr 0:8ff600c50722 679 //! @name Support functions
jossarr 0:8ff600c50722 680 // ************************************************************************************
jossarr 0:8ff600c50722 681 //@{
jossarr 0:8ff600c50722 682
jossarr 0:8ff600c50722 683 /**
jossarr 0:8ff600c50722 684 * Wrapper for MIFARE protocol communication.
jossarr 0:8ff600c50722 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
jossarr 0:8ff600c50722 686 *
jossarr 0:8ff600c50722 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
jossarr 0:8ff600c50722 688 * @param sendLen Number of bytes in sendData.
jossarr 0:8ff600c50722 689 * @param acceptTimeout True => A timeout is also success
jossarr 0:8ff600c50722 690 *
jossarr 0:8ff600c50722 691 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 692 */
jossarr 0:8ff600c50722 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
jossarr 0:8ff600c50722 694
jossarr 0:8ff600c50722 695 /**
jossarr 0:8ff600c50722 696 * Translates the SAK (Select Acknowledge) to a PICC type.
jossarr 0:8ff600c50722 697 *
jossarr 0:8ff600c50722 698 * @param sak The SAK byte returned from PICC_Select().
jossarr 0:8ff600c50722 699 *
jossarr 0:8ff600c50722 700 * @return PICC_Type
jossarr 0:8ff600c50722 701 */
jossarr 0:8ff600c50722 702 uint8_t PICC_GetType (uint8_t sak);
jossarr 0:8ff600c50722 703
jossarr 0:8ff600c50722 704 /**
jossarr 0:8ff600c50722 705 * Returns a string pointer to the PICC type name.
jossarr 0:8ff600c50722 706 *
jossarr 0:8ff600c50722 707 * @param type One of the PICC_Type enums.
jossarr 0:8ff600c50722 708 *
jossarr 0:8ff600c50722 709 * @return A string pointer to the PICC type name.
jossarr 0:8ff600c50722 710 */
jossarr 0:8ff600c50722 711 char* PICC_GetTypeName (uint8_t type);
jossarr 0:8ff600c50722 712
jossarr 0:8ff600c50722 713 /**
jossarr 0:8ff600c50722 714 * Returns a string pointer to a status code name.
jossarr 0:8ff600c50722 715 *
jossarr 0:8ff600c50722 716 * @param code One of the StatusCode enums.
jossarr 0:8ff600c50722 717 *
jossarr 0:8ff600c50722 718 * @return A string pointer to a status code name.
jossarr 0:8ff600c50722 719 */
jossarr 0:8ff600c50722 720 char* GetStatusCodeName (uint8_t code);
jossarr 0:8ff600c50722 721
jossarr 0:8ff600c50722 722 /**
jossarr 0:8ff600c50722 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
jossarr 0:8ff600c50722 724 *
jossarr 0:8ff600c50722 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
jossarr 0:8ff600c50722 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
jossarr 0:8ff600c50722 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
jossarr 0:8ff600c50722 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
jossarr 0:8ff600c50722 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
jossarr 0:8ff600c50722 730 */
jossarr 0:8ff600c50722 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
jossarr 0:8ff600c50722 732 uint8_t g0,
jossarr 0:8ff600c50722 733 uint8_t g1,
jossarr 0:8ff600c50722 734 uint8_t g2,
jossarr 0:8ff600c50722 735 uint8_t g3);
jossarr 0:8ff600c50722 736
jossarr 0:8ff600c50722 737 // ************************************************************************************
jossarr 0:8ff600c50722 738 //@}
jossarr 0:8ff600c50722 739
jossarr 0:8ff600c50722 740
jossarr 0:8ff600c50722 741 // ************************************************************************************
jossarr 0:8ff600c50722 742 //! @name Convenience functions - does not add extra functionality
jossarr 0:8ff600c50722 743 // ************************************************************************************
jossarr 0:8ff600c50722 744 //@{
jossarr 0:8ff600c50722 745
jossarr 0:8ff600c50722 746 /**
jossarr 0:8ff600c50722 747 * Returns true if a PICC responds to PICC_CMD_REQA.
jossarr 0:8ff600c50722 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
jossarr 0:8ff600c50722 749 *
jossarr 0:8ff600c50722 750 * @return bool
jossarr 0:8ff600c50722 751 */
jossarr 0:8ff600c50722 752 bool PICC_IsNewCardPresent(void);
jossarr 0:8ff600c50722 753
jossarr 0:8ff600c50722 754 /**
jossarr 0:8ff600c50722 755 * Simple wrapper around PICC_Select.
jossarr 0:8ff600c50722 756 * Returns true if a UID could be read.
jossarr 0:8ff600c50722 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
jossarr 0:8ff600c50722 758 * The read UID is available in the class variable uid.
jossarr 0:8ff600c50722 759 *
jossarr 0:8ff600c50722 760 * @return bool
jossarr 0:8ff600c50722 761 */
jossarr 0:8ff600c50722 762 bool PICC_ReadCardSerial (void);
jossarr 0:8ff600c50722 763
jossarr 0:8ff600c50722 764 // ************************************************************************************
jossarr 0:8ff600c50722 765 //@}
jossarr 0:8ff600c50722 766
jossarr 0:8ff600c50722 767
jossarr 0:8ff600c50722 768 private:
jossarr 0:8ff600c50722 769 SPI m_SPI;
jossarr 0:8ff600c50722 770 DigitalOut m_CS;
jossarr 0:8ff600c50722 771 DigitalOut m_RESET;
jossarr 0:8ff600c50722 772
jossarr 0:8ff600c50722 773 /**
jossarr 0:8ff600c50722 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
jossarr 0:8ff600c50722 775 *
jossarr 0:8ff600c50722 776 * @param command The command to use
jossarr 0:8ff600c50722 777 * @param blockAddr The block (0-0xff) number.
jossarr 0:8ff600c50722 778 * @param data The data to transfer in step 2
jossarr 0:8ff600c50722 779 *
jossarr 0:8ff600c50722 780 * @return STATUS_OK on success, STATUS_??? otherwise.
jossarr 0:8ff600c50722 781 */
jossarr 0:8ff600c50722 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
jossarr 0:8ff600c50722 783 };
jossarr 0:8ff600c50722 784
jossarr 0:8ff600c50722 785 #endif