Antulio's Team / Mbed 2 deprecated proyecto_bluetoooth

PROYECTO DE DOMOTICA

Dependencies:   mbed Servo DHT11

MFRC522.cpp@0:8ff600c50722, 2019-05-28 (annotated)

Committer:
jossarr
Date:
Tue May 28 23:33:24 2019 +0000
Revision:
0:8ff600c50722
PROYECTO DE DOMOTICA

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jossarr 0:8ff600c50722 1 /*
jossarr 0:8ff600c50722 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
jossarr 0:8ff600c50722 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
jossarr 0:8ff600c50722 4 * Released into the public domain.
jossarr 0:8ff600c50722 5 */
jossarr 0:8ff600c50722 6
jossarr 0:8ff600c50722 7 #include "MFRC522.h"
jossarr 0:8ff600c50722 8
jossarr 0:8ff600c50722 9 static const char* const _TypeNamePICC[] =
jossarr 0:8ff600c50722 10 {
jossarr 0:8ff600c50722 11 "Unknown type",
jossarr 0:8ff600c50722 12 "PICC compliant with ISO/IEC 14443-4",
jossarr 0:8ff600c50722 13 "PICC compliant with ISO/IEC 18092 (NFC)",
jossarr 0:8ff600c50722 14 "MIFARE Mini, 320 bytes",
jossarr 0:8ff600c50722 15 "MIFARE 1KB",
jossarr 0:8ff600c50722 16 "MIFARE 4KB",
jossarr 0:8ff600c50722 17 "MIFARE Ultralight or Ultralight C",
jossarr 0:8ff600c50722 18 "MIFARE Plus",
jossarr 0:8ff600c50722 19 "MIFARE TNP3XXX",
jossarr 0:8ff600c50722 20
jossarr 0:8ff600c50722 21 /* not complete UID */
jossarr 0:8ff600c50722 22 "SAK indicates UID is not complete"
jossarr 0:8ff600c50722 23 };
jossarr 0:8ff600c50722 24
jossarr 0:8ff600c50722 25 static const char* const _ErrorMessage[] =
jossarr 0:8ff600c50722 26 {
jossarr 0:8ff600c50722 27 "Unknown error",
jossarr 0:8ff600c50722 28 "Success",
jossarr 0:8ff600c50722 29 "Error in communication",
jossarr 0:8ff600c50722 30 "Collision detected",
jossarr 0:8ff600c50722 31 "Timeout in communication",
jossarr 0:8ff600c50722 32 "A buffer is not big enough",
jossarr 0:8ff600c50722 33 "Internal error in the code, should not happen",
jossarr 0:8ff600c50722 34 "Invalid argument",
jossarr 0:8ff600c50722 35 "The CRC_A does not match",
jossarr 0:8ff600c50722 36 "A MIFARE PICC responded with NAK"
jossarr 0:8ff600c50722 37 };
jossarr 0:8ff600c50722 38
jossarr 0:8ff600c50722 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
jossarr 0:8ff600c50722 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
jossarr 0:8ff600c50722 41
jossarr 0:8ff600c50722 42 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 43 // Functions for setting up the driver
jossarr 0:8ff600c50722 44 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 45
jossarr 0:8ff600c50722 46 /**
jossarr 0:8ff600c50722 47 * Constructor.
jossarr 0:8ff600c50722 48 * Prepares the output pins.
jossarr 0:8ff600c50722 49 */
jossarr 0:8ff600c50722 50 MFRC522::MFRC522(PinName mosi,
jossarr 0:8ff600c50722 51 PinName miso,
jossarr 0:8ff600c50722 52 PinName sclk,
jossarr 0:8ff600c50722 53 PinName cs,
jossarr 0:8ff600c50722 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
jossarr 0:8ff600c50722 55 {
jossarr 0:8ff600c50722 56 /* Configure SPI bus */
jossarr 0:8ff600c50722 57 m_SPI.format(8, 0);
jossarr 0:8ff600c50722 58 m_SPI.frequency(8000000);
jossarr 0:8ff600c50722 59
jossarr 0:8ff600c50722 60 /* Release SPI-CS pin */
jossarr 0:8ff600c50722 61 m_CS = 1;
jossarr 0:8ff600c50722 62
jossarr 0:8ff600c50722 63 /* Release RESET pin */
jossarr 0:8ff600c50722 64 m_RESET = 1;
jossarr 0:8ff600c50722 65 } // End constructor
jossarr 0:8ff600c50722 66
jossarr 0:8ff600c50722 67
jossarr 0:8ff600c50722 68 /**
jossarr 0:8ff600c50722 69 * Destructor.
jossarr 0:8ff600c50722 70 */
jossarr 0:8ff600c50722 71 MFRC522::~MFRC522()
jossarr 0:8ff600c50722 72 {
jossarr 0:8ff600c50722 73
jossarr 0:8ff600c50722 74 }
jossarr 0:8ff600c50722 75
jossarr 0:8ff600c50722 76
jossarr 0:8ff600c50722 77 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 78 // Basic interface functions for communicating with the MFRC522
jossarr 0:8ff600c50722 79 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 80
jossarr 0:8ff600c50722 81 /**
jossarr 0:8ff600c50722 82 * Writes a byte to the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 83 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 84 */
jossarr 0:8ff600c50722 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
jossarr 0:8ff600c50722 86 {
jossarr 0:8ff600c50722 87 m_CS = 0; /* Select SPI Chip MFRC522 */
jossarr 0:8ff600c50722 88
jossarr 0:8ff600c50722 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
jossarr 0:8ff600c50722 90 (void) m_SPI.write(reg & 0x7E);
jossarr 0:8ff600c50722 91 (void) m_SPI.write(value);
jossarr 0:8ff600c50722 92
jossarr 0:8ff600c50722 93 m_CS = 1; /* Release SPI Chip MFRC522 */
jossarr 0:8ff600c50722 94 } // End PCD_WriteRegister()
jossarr 0:8ff600c50722 95
jossarr 0:8ff600c50722 96 /**
jossarr 0:8ff600c50722 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 98 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 99 */
jossarr 0:8ff600c50722 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
jossarr 0:8ff600c50722 101 {
jossarr 0:8ff600c50722 102 m_CS = 0; /* Select SPI Chip MFRC522 */
jossarr 0:8ff600c50722 103
jossarr 0:8ff600c50722 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
jossarr 0:8ff600c50722 105 (void) m_SPI.write(reg & 0x7E);
jossarr 0:8ff600c50722 106 for (uint8_t index = 0; index < count; index++)
jossarr 0:8ff600c50722 107 {
jossarr 0:8ff600c50722 108 (void) m_SPI.write(values[index]);
jossarr 0:8ff600c50722 109 }
jossarr 0:8ff600c50722 110
jossarr 0:8ff600c50722 111 m_CS = 1; /* Release SPI Chip MFRC522 */
jossarr 0:8ff600c50722 112 } // End PCD_WriteRegister()
jossarr 0:8ff600c50722 113
jossarr 0:8ff600c50722 114 /**
jossarr 0:8ff600c50722 115 * Reads a byte from the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 116 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 117 */
jossarr 0:8ff600c50722 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
jossarr 0:8ff600c50722 119 {
jossarr 0:8ff600c50722 120 uint8_t value;
jossarr 0:8ff600c50722 121 m_CS = 0; /* Select SPI Chip MFRC522 */
jossarr 0:8ff600c50722 122
jossarr 0:8ff600c50722 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
jossarr 0:8ff600c50722 124 (void) m_SPI.write(0x80 | reg);
jossarr 0:8ff600c50722 125
jossarr 0:8ff600c50722 126 // Read the value back. Send 0 to stop reading.
jossarr 0:8ff600c50722 127 value = m_SPI.write(0);
jossarr 0:8ff600c50722 128
jossarr 0:8ff600c50722 129 m_CS = 1; /* Release SPI Chip MFRC522 */
jossarr 0:8ff600c50722 130
jossarr 0:8ff600c50722 131 return value;
jossarr 0:8ff600c50722 132 } // End PCD_ReadRegister()
jossarr 0:8ff600c50722 133
jossarr 0:8ff600c50722 134 /**
jossarr 0:8ff600c50722 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
jossarr 0:8ff600c50722 136 * The interface is described in the datasheet section 8.1.2.
jossarr 0:8ff600c50722 137 */
jossarr 0:8ff600c50722 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
jossarr 0:8ff600c50722 139 {
jossarr 0:8ff600c50722 140 if (count == 0) { return; }
jossarr 0:8ff600c50722 141
jossarr 0:8ff600c50722 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
jossarr 0:8ff600c50722 143 uint8_t index = 0; // Index in values array.
jossarr 0:8ff600c50722 144
jossarr 0:8ff600c50722 145 m_CS = 0; /* Select SPI Chip MFRC522 */
jossarr 0:8ff600c50722 146 count--; // One read is performed outside of the loop
jossarr 0:8ff600c50722 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
jossarr 0:8ff600c50722 148
jossarr 0:8ff600c50722 149 while (index < count)
jossarr 0:8ff600c50722 150 {
jossarr 0:8ff600c50722 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
jossarr 0:8ff600c50722 152 {
jossarr 0:8ff600c50722 153 // Create bit mask for bit positions rxAlign..7
jossarr 0:8ff600c50722 154 uint8_t mask = 0;
jossarr 0:8ff600c50722 155 for (uint8_t i = rxAlign; i <= 7; i++)
jossarr 0:8ff600c50722 156 {
jossarr 0:8ff600c50722 157 mask |= (1 << i);
jossarr 0:8ff600c50722 158 }
jossarr 0:8ff600c50722 159
jossarr 0:8ff600c50722 160 // Read value and tell that we want to read the same address again.
jossarr 0:8ff600c50722 161 uint8_t value = m_SPI.write(address);
jossarr 0:8ff600c50722 162
jossarr 0:8ff600c50722 163 // Apply mask to both current value of values[0] and the new data in value.
jossarr 0:8ff600c50722 164 values[0] = (values[index] & ~mask) | (value & mask);
jossarr 0:8ff600c50722 165 }
jossarr 0:8ff600c50722 166 else
jossarr 0:8ff600c50722 167 {
jossarr 0:8ff600c50722 168 // Read value and tell that we want to read the same address again.
jossarr 0:8ff600c50722 169 values[index] = m_SPI.write(address);
jossarr 0:8ff600c50722 170 }
jossarr 0:8ff600c50722 171
jossarr 0:8ff600c50722 172 index++;
jossarr 0:8ff600c50722 173 }
jossarr 0:8ff600c50722 174
jossarr 0:8ff600c50722 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
jossarr 0:8ff600c50722 176
jossarr 0:8ff600c50722 177 m_CS = 1; /* Release SPI Chip MFRC522 */
jossarr 0:8ff600c50722 178 } // End PCD_ReadRegister()
jossarr 0:8ff600c50722 179
jossarr 0:8ff600c50722 180 /**
jossarr 0:8ff600c50722 181 * Sets the bits given in mask in register reg.
jossarr 0:8ff600c50722 182 */
jossarr 0:8ff600c50722 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
jossarr 0:8ff600c50722 184 {
jossarr 0:8ff600c50722 185 uint8_t tmp = PCD_ReadRegister(reg);
jossarr 0:8ff600c50722 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
jossarr 0:8ff600c50722 187 } // End PCD_SetRegisterBitMask()
jossarr 0:8ff600c50722 188
jossarr 0:8ff600c50722 189 /**
jossarr 0:8ff600c50722 190 * Clears the bits given in mask from register reg.
jossarr 0:8ff600c50722 191 */
jossarr 0:8ff600c50722 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
jossarr 0:8ff600c50722 193 {
jossarr 0:8ff600c50722 194 uint8_t tmp = PCD_ReadRegister(reg);
jossarr 0:8ff600c50722 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
jossarr 0:8ff600c50722 196 } // End PCD_ClearRegisterBitMask()
jossarr 0:8ff600c50722 197
jossarr 0:8ff600c50722 198
jossarr 0:8ff600c50722 199 /**
jossarr 0:8ff600c50722 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
jossarr 0:8ff600c50722 201 */
jossarr 0:8ff600c50722 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
jossarr 0:8ff600c50722 203 {
jossarr 0:8ff600c50722 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
jossarr 0:8ff600c50722 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
jossarr 0:8ff600c50722 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
jossarr 0:8ff600c50722 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
jossarr 0:8ff600c50722 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
jossarr 0:8ff600c50722 209
jossarr 0:8ff600c50722 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
jossarr 0:8ff600c50722 211 uint16_t i = 5000;
jossarr 0:8ff600c50722 212 uint8_t n;
jossarr 0:8ff600c50722 213 while (1)
jossarr 0:8ff600c50722 214 {
jossarr 0:8ff600c50722 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
jossarr 0:8ff600c50722 216 if (n & 0x04)
jossarr 0:8ff600c50722 217 {
jossarr 0:8ff600c50722 218 // CRCIRq bit set - calculation done
jossarr 0:8ff600c50722 219 break;
jossarr 0:8ff600c50722 220 }
jossarr 0:8ff600c50722 221
jossarr 0:8ff600c50722 222 if (--i == 0)
jossarr 0:8ff600c50722 223 {
jossarr 0:8ff600c50722 224 // The emergency break. We will eventually terminate on this one after 89ms.
jossarr 0:8ff600c50722 225 // Communication with the MFRC522 might be down.
jossarr 0:8ff600c50722 226 return STATUS_TIMEOUT;
jossarr 0:8ff600c50722 227 }
jossarr 0:8ff600c50722 228 }
jossarr 0:8ff600c50722 229
jossarr 0:8ff600c50722 230 // Stop calculating CRC for new content in the FIFO.
jossarr 0:8ff600c50722 231 PCD_WriteRegister(CommandReg, PCD_Idle);
jossarr 0:8ff600c50722 232
jossarr 0:8ff600c50722 233 // Transfer the result from the registers to the result buffer
jossarr 0:8ff600c50722 234 result[0] = PCD_ReadRegister(CRCResultRegL);
jossarr 0:8ff600c50722 235 result[1] = PCD_ReadRegister(CRCResultRegH);
jossarr 0:8ff600c50722 236 return STATUS_OK;
jossarr 0:8ff600c50722 237 } // End PCD_CalculateCRC()
jossarr 0:8ff600c50722 238
jossarr 0:8ff600c50722 239
jossarr 0:8ff600c50722 240 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 241 // Functions for manipulating the MFRC522
jossarr 0:8ff600c50722 242 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 243
jossarr 0:8ff600c50722 244 /**
jossarr 0:8ff600c50722 245 * Initializes the MFRC522 chip.
jossarr 0:8ff600c50722 246 */
jossarr 0:8ff600c50722 247 void MFRC522::PCD_Init()
jossarr 0:8ff600c50722 248 {
jossarr 0:8ff600c50722 249 /* Reset MFRC522 */
jossarr 0:8ff600c50722 250 m_RESET = 0;
jossarr 0:8ff600c50722 251 wait_ms(10);
jossarr 0:8ff600c50722 252 m_RESET = 1;
jossarr 0:8ff600c50722 253
jossarr 0:8ff600c50722 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
jossarr 0:8ff600c50722 255 wait_ms(50);
jossarr 0:8ff600c50722 256
jossarr 0:8ff600c50722 257 // When communicating with a PICC we need a timeout if something goes wrong.
jossarr 0:8ff600c50722 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
jossarr 0:8ff600c50722 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
jossarr 0:8ff600c50722 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
jossarr 0:8ff600c50722 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
jossarr 0:8ff600c50722 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
jossarr 0:8ff600c50722 263 PCD_WriteRegister(TReloadRegL, 0xE8);
jossarr 0:8ff600c50722 264
jossarr 0:8ff600c50722 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
jossarr 0:8ff600c50722 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
jossarr 0:8ff600c50722 267
jossarr 0:8ff600c50722 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
jossarr 0:8ff600c50722 269
jossarr 0:8ff600c50722 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
jossarr 0:8ff600c50722 271 } // End PCD_Init()
jossarr 0:8ff600c50722 272
jossarr 0:8ff600c50722 273 /**
jossarr 0:8ff600c50722 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
jossarr 0:8ff600c50722 275 */
jossarr 0:8ff600c50722 276 void MFRC522::PCD_Reset()
jossarr 0:8ff600c50722 277 {
jossarr 0:8ff600c50722 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
jossarr 0:8ff600c50722 279 // The datasheet does not mention how long the SoftRest command takes to complete.
jossarr 0:8ff600c50722 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
jossarr 0:8ff600c50722 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
jossarr 0:8ff600c50722 282 wait_ms(50);
jossarr 0:8ff600c50722 283
jossarr 0:8ff600c50722 284 // Wait for the PowerDown bit in CommandReg to be cleared
jossarr 0:8ff600c50722 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
jossarr 0:8ff600c50722 286 {
jossarr 0:8ff600c50722 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
jossarr 0:8ff600c50722 288 }
jossarr 0:8ff600c50722 289 } // End PCD_Reset()
jossarr 0:8ff600c50722 290
jossarr 0:8ff600c50722 291 /**
jossarr 0:8ff600c50722 292 * Turns the antenna on by enabling pins TX1 and TX2.
jossarr 0:8ff600c50722 293 * After a reset these pins disabled.
jossarr 0:8ff600c50722 294 */
jossarr 0:8ff600c50722 295 void MFRC522::PCD_AntennaOn()
jossarr 0:8ff600c50722 296 {
jossarr 0:8ff600c50722 297 uint8_t value = PCD_ReadRegister(TxControlReg);
jossarr 0:8ff600c50722 298 if ((value & 0x03) != 0x03)
jossarr 0:8ff600c50722 299 {
jossarr 0:8ff600c50722 300 PCD_WriteRegister(TxControlReg, value | 0x03);
jossarr 0:8ff600c50722 301 }
jossarr 0:8ff600c50722 302 } // End PCD_AntennaOn()
jossarr 0:8ff600c50722 303
jossarr 0:8ff600c50722 304 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 305 // Functions for communicating with PICCs
jossarr 0:8ff600c50722 306 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 307
jossarr 0:8ff600c50722 308 /**
jossarr 0:8ff600c50722 309 * Executes the Transceive command.
jossarr 0:8ff600c50722 310 * CRC validation can only be done if backData and backLen are specified.
jossarr 0:8ff600c50722 311 */
jossarr 0:8ff600c50722 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
jossarr 0:8ff600c50722 313 uint8_t sendLen,
jossarr 0:8ff600c50722 314 uint8_t *backData,
jossarr 0:8ff600c50722 315 uint8_t *backLen,
jossarr 0:8ff600c50722 316 uint8_t *validBits,
jossarr 0:8ff600c50722 317 uint8_t rxAlign,
jossarr 0:8ff600c50722 318 bool checkCRC)
jossarr 0:8ff600c50722 319 {
jossarr 0:8ff600c50722 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
jossarr 0:8ff600c50722 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
jossarr 0:8ff600c50722 322 } // End PCD_TransceiveData()
jossarr 0:8ff600c50722 323
jossarr 0:8ff600c50722 324 /**
jossarr 0:8ff600c50722 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
jossarr 0:8ff600c50722 326 * CRC validation can only be done if backData and backLen are specified.
jossarr 0:8ff600c50722 327 */
jossarr 0:8ff600c50722 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
jossarr 0:8ff600c50722 329 uint8_t waitIRq,
jossarr 0:8ff600c50722 330 uint8_t *sendData,
jossarr 0:8ff600c50722 331 uint8_t sendLen,
jossarr 0:8ff600c50722 332 uint8_t *backData,
jossarr 0:8ff600c50722 333 uint8_t *backLen,
jossarr 0:8ff600c50722 334 uint8_t *validBits,
jossarr 0:8ff600c50722 335 uint8_t rxAlign,
jossarr 0:8ff600c50722 336 bool checkCRC)
jossarr 0:8ff600c50722 337 {
jossarr 0:8ff600c50722 338 uint8_t n, _validBits = 0;
jossarr 0:8ff600c50722 339 uint32_t i;
jossarr 0:8ff600c50722 340
jossarr 0:8ff600c50722 341 // Prepare values for BitFramingReg
jossarr 0:8ff600c50722 342 uint8_t txLastBits = validBits ? *validBits : 0;
jossarr 0:8ff600c50722 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
jossarr 0:8ff600c50722 344
jossarr 0:8ff600c50722 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
jossarr 0:8ff600c50722 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
jossarr 0:8ff600c50722 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
jossarr 0:8ff600c50722 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
jossarr 0:8ff600c50722 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
jossarr 0:8ff600c50722 350 PCD_WriteRegister(CommandReg, command); // Execute the command
jossarr 0:8ff600c50722 351 if (command == PCD_Transceive)
jossarr 0:8ff600c50722 352 {
jossarr 0:8ff600c50722 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
jossarr 0:8ff600c50722 354 }
jossarr 0:8ff600c50722 355
jossarr 0:8ff600c50722 356 // Wait for the command to complete.
jossarr 0:8ff600c50722 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
jossarr 0:8ff600c50722 358 // Each iteration of the do-while-loop takes 17.86us.
jossarr 0:8ff600c50722 359 i = 2000;
jossarr 0:8ff600c50722 360 while (1)
jossarr 0:8ff600c50722 361 {
jossarr 0:8ff600c50722 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
jossarr 0:8ff600c50722 363 if (n & waitIRq)
jossarr 0:8ff600c50722 364 { // One of the interrupts that signal success has been set.
jossarr 0:8ff600c50722 365 break;
jossarr 0:8ff600c50722 366 }
jossarr 0:8ff600c50722 367
jossarr 0:8ff600c50722 368 if (n & 0x01)
jossarr 0:8ff600c50722 369 { // Timer interrupt - nothing received in 25ms
jossarr 0:8ff600c50722 370 return STATUS_TIMEOUT;
jossarr 0:8ff600c50722 371 }
jossarr 0:8ff600c50722 372
jossarr 0:8ff600c50722 373 if (--i == 0)
jossarr 0:8ff600c50722 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
jossarr 0:8ff600c50722 375 return STATUS_TIMEOUT;
jossarr 0:8ff600c50722 376 }
jossarr 0:8ff600c50722 377 }
jossarr 0:8ff600c50722 378
jossarr 0:8ff600c50722 379 // Stop now if any errors except collisions were detected.
jossarr 0:8ff600c50722 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
jossarr 0:8ff600c50722 381 if (errorRegValue & 0x13)
jossarr 0:8ff600c50722 382 { // BufferOvfl ParityErr ProtocolErr
jossarr 0:8ff600c50722 383 return STATUS_ERROR;
jossarr 0:8ff600c50722 384 }
jossarr 0:8ff600c50722 385
jossarr 0:8ff600c50722 386 // If the caller wants data back, get it from the MFRC522.
jossarr 0:8ff600c50722 387 if (backData && backLen)
jossarr 0:8ff600c50722 388 {
jossarr 0:8ff600c50722 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
jossarr 0:8ff600c50722 390 if (n > *backLen)
jossarr 0:8ff600c50722 391 {
jossarr 0:8ff600c50722 392 return STATUS_NO_ROOM;
jossarr 0:8ff600c50722 393 }
jossarr 0:8ff600c50722 394
jossarr 0:8ff600c50722 395 *backLen = n; // Number of bytes returned
jossarr 0:8ff600c50722 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
jossarr 0:8ff600c50722 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
jossarr 0:8ff600c50722 398 if (validBits)
jossarr 0:8ff600c50722 399 {
jossarr 0:8ff600c50722 400 *validBits = _validBits;
jossarr 0:8ff600c50722 401 }
jossarr 0:8ff600c50722 402 }
jossarr 0:8ff600c50722 403
jossarr 0:8ff600c50722 404 // Tell about collisions
jossarr 0:8ff600c50722 405 if (errorRegValue & 0x08)
jossarr 0:8ff600c50722 406 { // CollErr
jossarr 0:8ff600c50722 407 return STATUS_COLLISION;
jossarr 0:8ff600c50722 408 }
jossarr 0:8ff600c50722 409
jossarr 0:8ff600c50722 410 // Perform CRC_A validation if requested.
jossarr 0:8ff600c50722 411 if (backData && backLen && checkCRC)
jossarr 0:8ff600c50722 412 {
jossarr 0:8ff600c50722 413 // In this case a MIFARE Classic NAK is not OK.
jossarr 0:8ff600c50722 414 if ((*backLen == 1) && (_validBits == 4))
jossarr 0:8ff600c50722 415 {
jossarr 0:8ff600c50722 416 return STATUS_MIFARE_NACK;
jossarr 0:8ff600c50722 417 }
jossarr 0:8ff600c50722 418
jossarr 0:8ff600c50722 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
jossarr 0:8ff600c50722 420 if ((*backLen < 2) || (_validBits != 0))
jossarr 0:8ff600c50722 421 {
jossarr 0:8ff600c50722 422 return STATUS_CRC_WRONG;
jossarr 0:8ff600c50722 423 }
jossarr 0:8ff600c50722 424
jossarr 0:8ff600c50722 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
jossarr 0:8ff600c50722 426 uint8_t controlBuffer[2];
jossarr 0:8ff600c50722 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
jossarr 0:8ff600c50722 428 if (n != STATUS_OK)
jossarr 0:8ff600c50722 429 {
jossarr 0:8ff600c50722 430 return n;
jossarr 0:8ff600c50722 431 }
jossarr 0:8ff600c50722 432
jossarr 0:8ff600c50722 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
jossarr 0:8ff600c50722 434 {
jossarr 0:8ff600c50722 435 return STATUS_CRC_WRONG;
jossarr 0:8ff600c50722 436 }
jossarr 0:8ff600c50722 437 }
jossarr 0:8ff600c50722 438
jossarr 0:8ff600c50722 439 return STATUS_OK;
jossarr 0:8ff600c50722 440 } // End PCD_CommunicateWithPICC()
jossarr 0:8ff600c50722 441
jossarr 0:8ff600c50722 442 /*
jossarr 0:8ff600c50722 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 445 */
jossarr 0:8ff600c50722 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
jossarr 0:8ff600c50722 447 {
jossarr 0:8ff600c50722 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
jossarr 0:8ff600c50722 449 } // End PICC_RequestA()
jossarr 0:8ff600c50722 450
jossarr 0:8ff600c50722 451 /**
jossarr 0:8ff600c50722 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
jossarr 0:8ff600c50722 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 454 */
jossarr 0:8ff600c50722 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
jossarr 0:8ff600c50722 456 {
jossarr 0:8ff600c50722 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
jossarr 0:8ff600c50722 458 } // End PICC_WakeupA()
jossarr 0:8ff600c50722 459
jossarr 0:8ff600c50722 460 /*
jossarr 0:8ff600c50722 461 * Transmits REQA or WUPA commands.
jossarr 0:8ff600c50722 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jossarr 0:8ff600c50722 463 */
jossarr 0:8ff600c50722 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
jossarr 0:8ff600c50722 465 {
jossarr 0:8ff600c50722 466 uint8_t validBits;
jossarr 0:8ff600c50722 467 uint8_t status;
jossarr 0:8ff600c50722 468
jossarr 0:8ff600c50722 469 if (bufferATQA == NULL || *bufferSize < 2)
jossarr 0:8ff600c50722 470 { // The ATQA response is 2 bytes long.
jossarr 0:8ff600c50722 471 return STATUS_NO_ROOM;
jossarr 0:8ff600c50722 472 }
jossarr 0:8ff600c50722 473
jossarr 0:8ff600c50722 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
jossarr 0:8ff600c50722 475 PCD_ClrRegisterBits(CollReg, 0x80);
jossarr 0:8ff600c50722 476
jossarr 0:8ff600c50722 477 // For REQA and WUPA we need the short frame format
jossarr 0:8ff600c50722 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
jossarr 0:8ff600c50722 479 validBits = 7;
jossarr 0:8ff600c50722 480
jossarr 0:8ff600c50722 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
jossarr 0:8ff600c50722 482 if (status != STATUS_OK)
jossarr 0:8ff600c50722 483 {
jossarr 0:8ff600c50722 484 return status;
jossarr 0:8ff600c50722 485 }
jossarr 0:8ff600c50722 486
jossarr 0:8ff600c50722 487 if ((*bufferSize != 2) || (validBits != 0))
jossarr 0:8ff600c50722 488 { // ATQA must be exactly 16 bits.
jossarr 0:8ff600c50722 489 return STATUS_ERROR;
jossarr 0:8ff600c50722 490 }
jossarr 0:8ff600c50722 491
jossarr 0:8ff600c50722 492 return STATUS_OK;
jossarr 0:8ff600c50722 493 } // End PICC_REQA_or_WUPA()
jossarr 0:8ff600c50722 494
jossarr 0:8ff600c50722 495 /*
jossarr 0:8ff600c50722 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
jossarr 0:8ff600c50722 497 */
jossarr 0:8ff600c50722 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
jossarr 0:8ff600c50722 499 {
jossarr 0:8ff600c50722 500 bool uidComplete;
jossarr 0:8ff600c50722 501 bool selectDone;
jossarr 0:8ff600c50722 502 bool useCascadeTag;
jossarr 0:8ff600c50722 503 uint8_t cascadeLevel = 1;
jossarr 0:8ff600c50722 504 uint8_t result;
jossarr 0:8ff600c50722 505 uint8_t count;
jossarr 0:8ff600c50722 506 uint8_t index;
jossarr 0:8ff600c50722 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
jossarr 0:8ff600c50722 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
jossarr 0:8ff600c50722 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
jossarr 0:8ff600c50722 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
jossarr 0:8ff600c50722 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
jossarr 0:8ff600c50722 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
jossarr 0:8ff600c50722 513 uint8_t *responseBuffer;
jossarr 0:8ff600c50722 514 uint8_t responseLength;
jossarr 0:8ff600c50722 515
jossarr 0:8ff600c50722 516 // Description of buffer structure:
jossarr 0:8ff600c50722 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
jossarr 0:8ff600c50722 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
jossarr 0:8ff600c50722 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
jossarr 0:8ff600c50722 520 // Byte 3: UID-data
jossarr 0:8ff600c50722 521 // Byte 4: UID-data
jossarr 0:8ff600c50722 522 // Byte 5: UID-data
jossarr 0:8ff600c50722 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
jossarr 0:8ff600c50722 524 // Byte 7: CRC_A
jossarr 0:8ff600c50722 525 // Byte 8: CRC_A
jossarr 0:8ff600c50722 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
jossarr 0:8ff600c50722 527 //
jossarr 0:8ff600c50722 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
jossarr 0:8ff600c50722 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
jossarr 0:8ff600c50722 530 // ======== ============= ===== ===== ===== =====
jossarr 0:8ff600c50722 531 // 4 bytes 1 uid0 uid1 uid2 uid3
jossarr 0:8ff600c50722 532 // 7 bytes 1 CT uid0 uid1 uid2
jossarr 0:8ff600c50722 533 // 2 uid3 uid4 uid5 uid6
jossarr 0:8ff600c50722 534 // 10 bytes 1 CT uid0 uid1 uid2
jossarr 0:8ff600c50722 535 // 2 CT uid3 uid4 uid5
jossarr 0:8ff600c50722 536 // 3 uid6 uid7 uid8 uid9
jossarr 0:8ff600c50722 537
jossarr 0:8ff600c50722 538 // Sanity checks
jossarr 0:8ff600c50722 539 if (validBits > 80)
jossarr 0:8ff600c50722 540 {
jossarr 0:8ff600c50722 541 return STATUS_INVALID;
jossarr 0:8ff600c50722 542 }
jossarr 0:8ff600c50722 543
jossarr 0:8ff600c50722 544 // Prepare MFRC522
jossarr 0:8ff600c50722 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
jossarr 0:8ff600c50722 546 PCD_ClrRegisterBits(CollReg, 0x80);
jossarr 0:8ff600c50722 547
jossarr 0:8ff600c50722 548 // Repeat Cascade Level loop until we have a complete UID.
jossarr 0:8ff600c50722 549 uidComplete = false;
jossarr 0:8ff600c50722 550 while ( ! uidComplete)
jossarr 0:8ff600c50722 551 {
jossarr 0:8ff600c50722 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
jossarr 0:8ff600c50722 553 switch (cascadeLevel)
jossarr 0:8ff600c50722 554 {
jossarr 0:8ff600c50722 555 case 1:
jossarr 0:8ff600c50722 556 buffer[0] = PICC_CMD_SEL_CL1;
jossarr 0:8ff600c50722 557 uidIndex = 0;
jossarr 0:8ff600c50722 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
jossarr 0:8ff600c50722 559 break;
jossarr 0:8ff600c50722 560
jossarr 0:8ff600c50722 561 case 2:
jossarr 0:8ff600c50722 562 buffer[0] = PICC_CMD_SEL_CL2;
jossarr 0:8ff600c50722 563 uidIndex = 3;
jossarr 0:8ff600c50722 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
jossarr 0:8ff600c50722 565 break;
jossarr 0:8ff600c50722 566
jossarr 0:8ff600c50722 567 case 3:
jossarr 0:8ff600c50722 568 buffer[0] = PICC_CMD_SEL_CL3;
jossarr 0:8ff600c50722 569 uidIndex = 6;
jossarr 0:8ff600c50722 570 useCascadeTag = false; // Never used in CL3.
jossarr 0:8ff600c50722 571 break;
jossarr 0:8ff600c50722 572
jossarr 0:8ff600c50722 573 default:
jossarr 0:8ff600c50722 574 return STATUS_INTERNAL_ERROR;
jossarr 0:8ff600c50722 575 //break;
jossarr 0:8ff600c50722 576 }
jossarr 0:8ff600c50722 577
jossarr 0:8ff600c50722 578 // How many UID bits are known in this Cascade Level?
jossarr 0:8ff600c50722 579 if(validBits > (8 * uidIndex))
jossarr 0:8ff600c50722 580 {
jossarr 0:8ff600c50722 581 currentLevelKnownBits = validBits - (8 * uidIndex);
jossarr 0:8ff600c50722 582 }
jossarr 0:8ff600c50722 583 else
jossarr 0:8ff600c50722 584 {
jossarr 0:8ff600c50722 585 currentLevelKnownBits = 0;
jossarr 0:8ff600c50722 586 }
jossarr 0:8ff600c50722 587
jossarr 0:8ff600c50722 588 // Copy the known bits from uid->uidByte[] to buffer[]
jossarr 0:8ff600c50722 589 index = 2; // destination index in buffer[]
jossarr 0:8ff600c50722 590 if (useCascadeTag)
jossarr 0:8ff600c50722 591 {
jossarr 0:8ff600c50722 592 buffer[index++] = PICC_CMD_CT;
jossarr 0:8ff600c50722 593 }
jossarr 0:8ff600c50722 594
jossarr 0:8ff600c50722 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
jossarr 0:8ff600c50722 596 if (bytesToCopy)
jossarr 0:8ff600c50722 597 {
jossarr 0:8ff600c50722 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
jossarr 0:8ff600c50722 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
jossarr 0:8ff600c50722 600 if (bytesToCopy > maxBytes)
jossarr 0:8ff600c50722 601 {
jossarr 0:8ff600c50722 602 bytesToCopy = maxBytes;
jossarr 0:8ff600c50722 603 }
jossarr 0:8ff600c50722 604
jossarr 0:8ff600c50722 605 for (count = 0; count < bytesToCopy; count++)
jossarr 0:8ff600c50722 606 {
jossarr 0:8ff600c50722 607 buffer[index++] = uid->uidByte[uidIndex + count];
jossarr 0:8ff600c50722 608 }
jossarr 0:8ff600c50722 609 }
jossarr 0:8ff600c50722 610
jossarr 0:8ff600c50722 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
jossarr 0:8ff600c50722 612 if (useCascadeTag)
jossarr 0:8ff600c50722 613 {
jossarr 0:8ff600c50722 614 currentLevelKnownBits += 8;
jossarr 0:8ff600c50722 615 }
jossarr 0:8ff600c50722 616
jossarr 0:8ff600c50722 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
jossarr 0:8ff600c50722 618 selectDone = false;
jossarr 0:8ff600c50722 619 while ( ! selectDone)
jossarr 0:8ff600c50722 620 {
jossarr 0:8ff600c50722 621 // Find out how many bits and bytes to send and receive.
jossarr 0:8ff600c50722 622 if (currentLevelKnownBits >= 32)
jossarr 0:8ff600c50722 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
jossarr 0:8ff600c50722 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
jossarr 0:8ff600c50722 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
jossarr 0:8ff600c50722 626
jossarr 0:8ff600c50722 627 // Calulate BCC - Block Check Character
jossarr 0:8ff600c50722 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
jossarr 0:8ff600c50722 629
jossarr 0:8ff600c50722 630 // Calculate CRC_A
jossarr 0:8ff600c50722 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
jossarr 0:8ff600c50722 632 if (result != STATUS_OK)
jossarr 0:8ff600c50722 633 {
jossarr 0:8ff600c50722 634 return result;
jossarr 0:8ff600c50722 635 }
jossarr 0:8ff600c50722 636
jossarr 0:8ff600c50722 637 txLastBits = 0; // 0 => All 8 bits are valid.
jossarr 0:8ff600c50722 638 bufferUsed = 9;
jossarr 0:8ff600c50722 639
jossarr 0:8ff600c50722 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
jossarr 0:8ff600c50722 641 responseBuffer = &buffer[6];
jossarr 0:8ff600c50722 642 responseLength = 3;
jossarr 0:8ff600c50722 643 }
jossarr 0:8ff600c50722 644 else
jossarr 0:8ff600c50722 645 { // This is an ANTICOLLISION.
jossarr 0:8ff600c50722 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
jossarr 0:8ff600c50722 647 txLastBits = currentLevelKnownBits % 8;
jossarr 0:8ff600c50722 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
jossarr 0:8ff600c50722 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
jossarr 0:8ff600c50722 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
jossarr 0:8ff600c50722 651 bufferUsed = index + (txLastBits ? 1 : 0);
jossarr 0:8ff600c50722 652
jossarr 0:8ff600c50722 653 // Store response in the unused part of buffer
jossarr 0:8ff600c50722 654 responseBuffer = &buffer[index];
jossarr 0:8ff600c50722 655 responseLength = sizeof(buffer) - index;
jossarr 0:8ff600c50722 656 }
jossarr 0:8ff600c50722 657
jossarr 0:8ff600c50722 658 // Set bit adjustments
jossarr 0:8ff600c50722 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
jossarr 0:8ff600c50722 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
jossarr 0:8ff600c50722 661
jossarr 0:8ff600c50722 662 // Transmit the buffer and receive the response.
jossarr 0:8ff600c50722 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
jossarr 0:8ff600c50722 664 if (result == STATUS_COLLISION)
jossarr 0:8ff600c50722 665 { // More than one PICC in the field => collision.
jossarr 0:8ff600c50722 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
jossarr 0:8ff600c50722 667 if (result & 0x20)
jossarr 0:8ff600c50722 668 { // CollPosNotValid
jossarr 0:8ff600c50722 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
jossarr 0:8ff600c50722 670 }
jossarr 0:8ff600c50722 671
jossarr 0:8ff600c50722 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
jossarr 0:8ff600c50722 673 if (collisionPos == 0)
jossarr 0:8ff600c50722 674 {
jossarr 0:8ff600c50722 675 collisionPos = 32;
jossarr 0:8ff600c50722 676 }
jossarr 0:8ff600c50722 677
jossarr 0:8ff600c50722 678 if (collisionPos <= currentLevelKnownBits)
jossarr 0:8ff600c50722 679 { // No progress - should not happen
jossarr 0:8ff600c50722 680 return STATUS_INTERNAL_ERROR;
jossarr 0:8ff600c50722 681 }
jossarr 0:8ff600c50722 682
jossarr 0:8ff600c50722 683 // Choose the PICC with the bit set.
jossarr 0:8ff600c50722 684 currentLevelKnownBits = collisionPos;
jossarr 0:8ff600c50722 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
jossarr 0:8ff600c50722 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
jossarr 0:8ff600c50722 687 buffer[index] |= (1 << count);
jossarr 0:8ff600c50722 688 }
jossarr 0:8ff600c50722 689 else if (result != STATUS_OK)
jossarr 0:8ff600c50722 690 {
jossarr 0:8ff600c50722 691 return result;
jossarr 0:8ff600c50722 692 }
jossarr 0:8ff600c50722 693 else
jossarr 0:8ff600c50722 694 { // STATUS_OK
jossarr 0:8ff600c50722 695 if (currentLevelKnownBits >= 32)
jossarr 0:8ff600c50722 696 { // This was a SELECT.
jossarr 0:8ff600c50722 697 selectDone = true; // No more anticollision
jossarr 0:8ff600c50722 698 // We continue below outside the while.
jossarr 0:8ff600c50722 699 }
jossarr 0:8ff600c50722 700 else
jossarr 0:8ff600c50722 701 { // This was an ANTICOLLISION.
jossarr 0:8ff600c50722 702 // We now have all 32 bits of the UID in this Cascade Level
jossarr 0:8ff600c50722 703 currentLevelKnownBits = 32;
jossarr 0:8ff600c50722 704 // Run loop again to do the SELECT.
jossarr 0:8ff600c50722 705 }
jossarr 0:8ff600c50722 706 }
jossarr 0:8ff600c50722 707 } // End of while ( ! selectDone)
jossarr 0:8ff600c50722 708
jossarr 0:8ff600c50722 709 // We do not check the CBB - it was constructed by us above.
jossarr 0:8ff600c50722 710
jossarr 0:8ff600c50722 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
jossarr 0:8ff600c50722 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
jossarr 0:8ff600c50722 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
jossarr 0:8ff600c50722 714 for (count = 0; count < bytesToCopy; count++)
jossarr 0:8ff600c50722 715 {
jossarr 0:8ff600c50722 716 uid->uidByte[uidIndex + count] = buffer[index++];
jossarr 0:8ff600c50722 717 }
jossarr 0:8ff600c50722 718
jossarr 0:8ff600c50722 719 // Check response SAK (Select Acknowledge)
jossarr 0:8ff600c50722 720 if (responseLength != 3 || txLastBits != 0)
jossarr 0:8ff600c50722 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
jossarr 0:8ff600c50722 722 return STATUS_ERROR;
jossarr 0:8ff600c50722 723 }
jossarr 0:8ff600c50722 724
jossarr 0:8ff600c50722 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
jossarr 0:8ff600c50722 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
jossarr 0:8ff600c50722 727 if (result != STATUS_OK)
jossarr 0:8ff600c50722 728 {
jossarr 0:8ff600c50722 729 return result;
jossarr 0:8ff600c50722 730 }
jossarr 0:8ff600c50722 731
jossarr 0:8ff600c50722 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
jossarr 0:8ff600c50722 733 {
jossarr 0:8ff600c50722 734 return STATUS_CRC_WRONG;
jossarr 0:8ff600c50722 735 }
jossarr 0:8ff600c50722 736
jossarr 0:8ff600c50722 737 if (responseBuffer[0] & 0x04)
jossarr 0:8ff600c50722 738 { // Cascade bit set - UID not complete yes
jossarr 0:8ff600c50722 739 cascadeLevel++;
jossarr 0:8ff600c50722 740 }
jossarr 0:8ff600c50722 741 else
jossarr 0:8ff600c50722 742 {
jossarr 0:8ff600c50722 743 uidComplete = true;
jossarr 0:8ff600c50722 744 uid->sak = responseBuffer[0];
jossarr 0:8ff600c50722 745 }
jossarr 0:8ff600c50722 746 } // End of while ( ! uidComplete)
jossarr 0:8ff600c50722 747
jossarr 0:8ff600c50722 748 // Set correct uid->size
jossarr 0:8ff600c50722 749 uid->size = 3 * cascadeLevel + 1;
jossarr 0:8ff600c50722 750
jossarr 0:8ff600c50722 751 return STATUS_OK;
jossarr 0:8ff600c50722 752 } // End PICC_Select()
jossarr 0:8ff600c50722 753
jossarr 0:8ff600c50722 754 /*
jossarr 0:8ff600c50722 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
jossarr 0:8ff600c50722 756 */
jossarr 0:8ff600c50722 757 uint8_t MFRC522::PICC_HaltA()
jossarr 0:8ff600c50722 758 {
jossarr 0:8ff600c50722 759 uint8_t result;
jossarr 0:8ff600c50722 760 uint8_t buffer[4];
jossarr 0:8ff600c50722 761
jossarr 0:8ff600c50722 762 // Build command buffer
jossarr 0:8ff600c50722 763 buffer[0] = PICC_CMD_HLTA;
jossarr 0:8ff600c50722 764 buffer[1] = 0;
jossarr 0:8ff600c50722 765
jossarr 0:8ff600c50722 766 // Calculate CRC_A
jossarr 0:8ff600c50722 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
jossarr 0:8ff600c50722 768 if (result == STATUS_OK)
jossarr 0:8ff600c50722 769 {
jossarr 0:8ff600c50722 770 // Send the command.
jossarr 0:8ff600c50722 771 // The standard says:
jossarr 0:8ff600c50722 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
jossarr 0:8ff600c50722 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
jossarr 0:8ff600c50722 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
jossarr 0:8ff600c50722 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
jossarr 0:8ff600c50722 776 if (result == STATUS_TIMEOUT)
jossarr 0:8ff600c50722 777 {
jossarr 0:8ff600c50722 778 result = STATUS_OK;
jossarr 0:8ff600c50722 779 }
jossarr 0:8ff600c50722 780 else if (result == STATUS_OK)
jossarr 0:8ff600c50722 781 { // That is ironically NOT ok in this case ;-)
jossarr 0:8ff600c50722 782 result = STATUS_ERROR;
jossarr 0:8ff600c50722 783 }
jossarr 0:8ff600c50722 784 }
jossarr 0:8ff600c50722 785
jossarr 0:8ff600c50722 786 return result;
jossarr 0:8ff600c50722 787 } // End PICC_HaltA()
jossarr 0:8ff600c50722 788
jossarr 0:8ff600c50722 789
jossarr 0:8ff600c50722 790 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 791 // Functions for communicating with MIFARE PICCs
jossarr 0:8ff600c50722 792 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 793
jossarr 0:8ff600c50722 794 /*
jossarr 0:8ff600c50722 795 * Executes the MFRC522 MFAuthent command.
jossarr 0:8ff600c50722 796 */
jossarr 0:8ff600c50722 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
jossarr 0:8ff600c50722 798 {
jossarr 0:8ff600c50722 799 uint8_t i, waitIRq = 0x10; // IdleIRq
jossarr 0:8ff600c50722 800
jossarr 0:8ff600c50722 801 // Build command buffer
jossarr 0:8ff600c50722 802 uint8_t sendData[12];
jossarr 0:8ff600c50722 803 sendData[0] = command;
jossarr 0:8ff600c50722 804 sendData[1] = blockAddr;
jossarr 0:8ff600c50722 805
jossarr 0:8ff600c50722 806 for (i = 0; i < MF_KEY_SIZE; i++)
jossarr 0:8ff600c50722 807 { // 6 key bytes
jossarr 0:8ff600c50722 808 sendData[2+i] = key->keyByte[i];
jossarr 0:8ff600c50722 809 }
jossarr 0:8ff600c50722 810
jossarr 0:8ff600c50722 811 for (i = 0; i < 4; i++)
jossarr 0:8ff600c50722 812 { // The first 4 bytes of the UID
jossarr 0:8ff600c50722 813 sendData[8+i] = uid->uidByte[i];
jossarr 0:8ff600c50722 814 }
jossarr 0:8ff600c50722 815
jossarr 0:8ff600c50722 816 // Start the authentication.
jossarr 0:8ff600c50722 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
jossarr 0:8ff600c50722 818 } // End PCD_Authenticate()
jossarr 0:8ff600c50722 819
jossarr 0:8ff600c50722 820 /*
jossarr 0:8ff600c50722 821 * Used to exit the PCD from its authenticated state.
jossarr 0:8ff600c50722 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
jossarr 0:8ff600c50722 823 */
jossarr 0:8ff600c50722 824 void MFRC522::PCD_StopCrypto1()
jossarr 0:8ff600c50722 825 {
jossarr 0:8ff600c50722 826 // Clear MFCrypto1On bit
jossarr 0:8ff600c50722 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
jossarr 0:8ff600c50722 828 } // End PCD_StopCrypto1()
jossarr 0:8ff600c50722 829
jossarr 0:8ff600c50722 830 /*
jossarr 0:8ff600c50722 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
jossarr 0:8ff600c50722 832 */
jossarr 0:8ff600c50722 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
jossarr 0:8ff600c50722 834 {
jossarr 0:8ff600c50722 835 uint8_t result = STATUS_NO_ROOM;
jossarr 0:8ff600c50722 836
jossarr 0:8ff600c50722 837 // Sanity check
jossarr 0:8ff600c50722 838 if ((buffer == NULL) || (*bufferSize < 18))
jossarr 0:8ff600c50722 839 {
jossarr 0:8ff600c50722 840 return result;
jossarr 0:8ff600c50722 841 }
jossarr 0:8ff600c50722 842
jossarr 0:8ff600c50722 843 // Build command buffer
jossarr 0:8ff600c50722 844 buffer[0] = PICC_CMD_MF_READ;
jossarr 0:8ff600c50722 845 buffer[1] = blockAddr;
jossarr 0:8ff600c50722 846
jossarr 0:8ff600c50722 847 // Calculate CRC_A
jossarr 0:8ff600c50722 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
jossarr 0:8ff600c50722 849 if (result != STATUS_OK)
jossarr 0:8ff600c50722 850 {
jossarr 0:8ff600c50722 851 return result;
jossarr 0:8ff600c50722 852 }
jossarr 0:8ff600c50722 853
jossarr 0:8ff600c50722 854 // Transmit the buffer and receive the response, validate CRC_A.
jossarr 0:8ff600c50722 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
jossarr 0:8ff600c50722 856 } // End MIFARE_Read()
jossarr 0:8ff600c50722 857
jossarr 0:8ff600c50722 858 /*
jossarr 0:8ff600c50722 859 * Writes 16 bytes to the active PICC.
jossarr 0:8ff600c50722 860 */
jossarr 0:8ff600c50722 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
jossarr 0:8ff600c50722 862 {
jossarr 0:8ff600c50722 863 uint8_t result;
jossarr 0:8ff600c50722 864
jossarr 0:8ff600c50722 865 // Sanity check
jossarr 0:8ff600c50722 866 if (buffer == NULL || bufferSize < 16)
jossarr 0:8ff600c50722 867 {
jossarr 0:8ff600c50722 868 return STATUS_INVALID;
jossarr 0:8ff600c50722 869 }
jossarr 0:8ff600c50722 870
jossarr 0:8ff600c50722 871 // Mifare Classic protocol requires two communications to perform a write.
jossarr 0:8ff600c50722 872 // Step 1: Tell the PICC we want to write to block blockAddr.
jossarr 0:8ff600c50722 873 uint8_t cmdBuffer[2];
jossarr 0:8ff600c50722 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
jossarr 0:8ff600c50722 875 cmdBuffer[1] = blockAddr;
jossarr 0:8ff600c50722 876 // Adds CRC_A and checks that the response is MF_ACK.
jossarr 0:8ff600c50722 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
jossarr 0:8ff600c50722 878 if (result != STATUS_OK)
jossarr 0:8ff600c50722 879 {
jossarr 0:8ff600c50722 880 return result;
jossarr 0:8ff600c50722 881 }
jossarr 0:8ff600c50722 882
jossarr 0:8ff600c50722 883 // Step 2: Transfer the data
jossarr 0:8ff600c50722 884 // Adds CRC_A and checks that the response is MF_ACK.
jossarr 0:8ff600c50722 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
jossarr 0:8ff600c50722 886 if (result != STATUS_OK)
jossarr 0:8ff600c50722 887 {
jossarr 0:8ff600c50722 888 return result;
jossarr 0:8ff600c50722 889 }
jossarr 0:8ff600c50722 890
jossarr 0:8ff600c50722 891 return STATUS_OK;
jossarr 0:8ff600c50722 892 } // End MIFARE_Write()
jossarr 0:8ff600c50722 893
jossarr 0:8ff600c50722 894 /*
jossarr 0:8ff600c50722 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
jossarr 0:8ff600c50722 896 */
jossarr 0:8ff600c50722 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
jossarr 0:8ff600c50722 898 {
jossarr 0:8ff600c50722 899 uint8_t result;
jossarr 0:8ff600c50722 900
jossarr 0:8ff600c50722 901 // Sanity check
jossarr 0:8ff600c50722 902 if (buffer == NULL || bufferSize < 4)
jossarr 0:8ff600c50722 903 {
jossarr 0:8ff600c50722 904 return STATUS_INVALID;
jossarr 0:8ff600c50722 905 }
jossarr 0:8ff600c50722 906
jossarr 0:8ff600c50722 907 // Build commmand buffer
jossarr 0:8ff600c50722 908 uint8_t cmdBuffer[6];
jossarr 0:8ff600c50722 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
jossarr 0:8ff600c50722 910 cmdBuffer[1] = page;
jossarr 0:8ff600c50722 911 memcpy(&cmdBuffer[2], buffer, 4);
jossarr 0:8ff600c50722 912
jossarr 0:8ff600c50722 913 // Perform the write
jossarr 0:8ff600c50722 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
jossarr 0:8ff600c50722 915 if (result != STATUS_OK)
jossarr 0:8ff600c50722 916 {
jossarr 0:8ff600c50722 917 return result;
jossarr 0:8ff600c50722 918 }
jossarr 0:8ff600c50722 919
jossarr 0:8ff600c50722 920 return STATUS_OK;
jossarr 0:8ff600c50722 921 } // End MIFARE_Ultralight_Write()
jossarr 0:8ff600c50722 922
jossarr 0:8ff600c50722 923 /*
jossarr 0:8ff600c50722 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
jossarr 0:8ff600c50722 925 */
jossarr 0:8ff600c50722 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
jossarr 0:8ff600c50722 927 {
jossarr 0:8ff600c50722 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
jossarr 0:8ff600c50722 929 } // End MIFARE_Decrement()
jossarr 0:8ff600c50722 930
jossarr 0:8ff600c50722 931 /*
jossarr 0:8ff600c50722 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
jossarr 0:8ff600c50722 933 */
jossarr 0:8ff600c50722 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
jossarr 0:8ff600c50722 935 {
jossarr 0:8ff600c50722 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
jossarr 0:8ff600c50722 937 } // End MIFARE_Increment()
jossarr 0:8ff600c50722 938
jossarr 0:8ff600c50722 939 /**
jossarr 0:8ff600c50722 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
jossarr 0:8ff600c50722 941 */
jossarr 0:8ff600c50722 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
jossarr 0:8ff600c50722 943 {
jossarr 0:8ff600c50722 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
jossarr 0:8ff600c50722 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
jossarr 0:8ff600c50722 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
jossarr 0:8ff600c50722 947 } // End MIFARE_Restore()
jossarr 0:8ff600c50722 948
jossarr 0:8ff600c50722 949 /*
jossarr 0:8ff600c50722 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
jossarr 0:8ff600c50722 951 */
jossarr 0:8ff600c50722 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
jossarr 0:8ff600c50722 953 {
jossarr 0:8ff600c50722 954 uint8_t result;
jossarr 0:8ff600c50722 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
jossarr 0:8ff600c50722 956
jossarr 0:8ff600c50722 957 // Step 1: Tell the PICC the command and block address
jossarr 0:8ff600c50722 958 cmdBuffer[0] = command;
jossarr 0:8ff600c50722 959 cmdBuffer[1] = blockAddr;
jossarr 0:8ff600c50722 960
jossarr 0:8ff600c50722 961 // Adds CRC_A and checks that the response is MF_ACK.
jossarr 0:8ff600c50722 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
jossarr 0:8ff600c50722 963 if (result != STATUS_OK)
jossarr 0:8ff600c50722 964 {
jossarr 0:8ff600c50722 965 return result;
jossarr 0:8ff600c50722 966 }
jossarr 0:8ff600c50722 967
jossarr 0:8ff600c50722 968 // Step 2: Transfer the data
jossarr 0:8ff600c50722 969 // Adds CRC_A and accept timeout as success.
jossarr 0:8ff600c50722 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
jossarr 0:8ff600c50722 971 if (result != STATUS_OK)
jossarr 0:8ff600c50722 972 {
jossarr 0:8ff600c50722 973 return result;
jossarr 0:8ff600c50722 974 }
jossarr 0:8ff600c50722 975
jossarr 0:8ff600c50722 976 return STATUS_OK;
jossarr 0:8ff600c50722 977 } // End MIFARE_TwoStepHelper()
jossarr 0:8ff600c50722 978
jossarr 0:8ff600c50722 979 /*
jossarr 0:8ff600c50722 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
jossarr 0:8ff600c50722 981 */
jossarr 0:8ff600c50722 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
jossarr 0:8ff600c50722 983 {
jossarr 0:8ff600c50722 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
jossarr 0:8ff600c50722 985
jossarr 0:8ff600c50722 986 // Tell the PICC we want to transfer the result into block blockAddr.
jossarr 0:8ff600c50722 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
jossarr 0:8ff600c50722 988 cmdBuffer[1] = blockAddr;
jossarr 0:8ff600c50722 989
jossarr 0:8ff600c50722 990 // Adds CRC_A and checks that the response is MF_ACK.
jossarr 0:8ff600c50722 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
jossarr 0:8ff600c50722 992 } // End MIFARE_Transfer()
jossarr 0:8ff600c50722 993
jossarr 0:8ff600c50722 994
jossarr 0:8ff600c50722 995 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 996 // Support functions
jossarr 0:8ff600c50722 997 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 998
jossarr 0:8ff600c50722 999 /*
jossarr 0:8ff600c50722 1000 * Wrapper for MIFARE protocol communication.
jossarr 0:8ff600c50722 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
jossarr 0:8ff600c50722 1002 */
jossarr 0:8ff600c50722 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
jossarr 0:8ff600c50722 1004 {
jossarr 0:8ff600c50722 1005 uint8_t result;
jossarr 0:8ff600c50722 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
jossarr 0:8ff600c50722 1007
jossarr 0:8ff600c50722 1008 // Sanity check
jossarr 0:8ff600c50722 1009 if (sendData == NULL || sendLen > 16)
jossarr 0:8ff600c50722 1010 {
jossarr 0:8ff600c50722 1011 return STATUS_INVALID;
jossarr 0:8ff600c50722 1012 }
jossarr 0:8ff600c50722 1013
jossarr 0:8ff600c50722 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
jossarr 0:8ff600c50722 1015 memcpy(cmdBuffer, sendData, sendLen);
jossarr 0:8ff600c50722 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
jossarr 0:8ff600c50722 1017 if (result != STATUS_OK)
jossarr 0:8ff600c50722 1018 {
jossarr 0:8ff600c50722 1019 return result;
jossarr 0:8ff600c50722 1020 }
jossarr 0:8ff600c50722 1021
jossarr 0:8ff600c50722 1022 sendLen += 2;
jossarr 0:8ff600c50722 1023
jossarr 0:8ff600c50722 1024 // Transceive the data, store the reply in cmdBuffer[]
jossarr 0:8ff600c50722 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
jossarr 0:8ff600c50722 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
jossarr 0:8ff600c50722 1027 uint8_t validBits = 0;
jossarr 0:8ff600c50722 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
jossarr 0:8ff600c50722 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
jossarr 0:8ff600c50722 1030 {
jossarr 0:8ff600c50722 1031 return STATUS_OK;
jossarr 0:8ff600c50722 1032 }
jossarr 0:8ff600c50722 1033
jossarr 0:8ff600c50722 1034 if (result != STATUS_OK)
jossarr 0:8ff600c50722 1035 {
jossarr 0:8ff600c50722 1036 return result;
jossarr 0:8ff600c50722 1037 }
jossarr 0:8ff600c50722 1038
jossarr 0:8ff600c50722 1039 // The PICC must reply with a 4 bit ACK
jossarr 0:8ff600c50722 1040 if (cmdBufferSize != 1 || validBits != 4)
jossarr 0:8ff600c50722 1041 {
jossarr 0:8ff600c50722 1042 return STATUS_ERROR;
jossarr 0:8ff600c50722 1043 }
jossarr 0:8ff600c50722 1044
jossarr 0:8ff600c50722 1045 if (cmdBuffer[0] != MF_ACK)
jossarr 0:8ff600c50722 1046 {
jossarr 0:8ff600c50722 1047 return STATUS_MIFARE_NACK;
jossarr 0:8ff600c50722 1048 }
jossarr 0:8ff600c50722 1049
jossarr 0:8ff600c50722 1050 return STATUS_OK;
jossarr 0:8ff600c50722 1051 } // End PCD_MIFARE_Transceive()
jossarr 0:8ff600c50722 1052
jossarr 0:8ff600c50722 1053
jossarr 0:8ff600c50722 1054 /*
jossarr 0:8ff600c50722 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
jossarr 0:8ff600c50722 1056 */
jossarr 0:8ff600c50722 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
jossarr 0:8ff600c50722 1058 {
jossarr 0:8ff600c50722 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
jossarr 0:8ff600c50722 1060
jossarr 0:8ff600c50722 1061 if (sak & 0x04)
jossarr 0:8ff600c50722 1062 { // UID not complete
jossarr 0:8ff600c50722 1063 retType = PICC_TYPE_NOT_COMPLETE;
jossarr 0:8ff600c50722 1064 }
jossarr 0:8ff600c50722 1065 else
jossarr 0:8ff600c50722 1066 {
jossarr 0:8ff600c50722 1067 switch (sak)
jossarr 0:8ff600c50722 1068 {
jossarr 0:8ff600c50722 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
jossarr 0:8ff600c50722 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
jossarr 0:8ff600c50722 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
jossarr 0:8ff600c50722 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
jossarr 0:8ff600c50722 1073 case 0x10:
jossarr 0:8ff600c50722 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
jossarr 0:8ff600c50722 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
jossarr 0:8ff600c50722 1076 default:
jossarr 0:8ff600c50722 1077 if (sak & 0x20)
jossarr 0:8ff600c50722 1078 {
jossarr 0:8ff600c50722 1079 retType = PICC_TYPE_ISO_14443_4;
jossarr 0:8ff600c50722 1080 }
jossarr 0:8ff600c50722 1081 else if (sak & 0x40)
jossarr 0:8ff600c50722 1082 {
jossarr 0:8ff600c50722 1083 retType = PICC_TYPE_ISO_18092;
jossarr 0:8ff600c50722 1084 }
jossarr 0:8ff600c50722 1085 break;
jossarr 0:8ff600c50722 1086 }
jossarr 0:8ff600c50722 1087 }
jossarr 0:8ff600c50722 1088
jossarr 0:8ff600c50722 1089 return (retType);
jossarr 0:8ff600c50722 1090 } // End PICC_GetType()
jossarr 0:8ff600c50722 1091
jossarr 0:8ff600c50722 1092 /*
jossarr 0:8ff600c50722 1093 * Returns a string pointer to the PICC type name.
jossarr 0:8ff600c50722 1094 */
jossarr 0:8ff600c50722 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
jossarr 0:8ff600c50722 1096 {
jossarr 0:8ff600c50722 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
jossarr 0:8ff600c50722 1098 {
jossarr 0:8ff600c50722 1099 piccType = MFRC522_MaxPICCs - 1;
jossarr 0:8ff600c50722 1100 }
jossarr 0:8ff600c50722 1101
jossarr 0:8ff600c50722 1102 return((char *) _TypeNamePICC[piccType]);
jossarr 0:8ff600c50722 1103 } // End PICC_GetTypeName()
jossarr 0:8ff600c50722 1104
jossarr 0:8ff600c50722 1105 /*
jossarr 0:8ff600c50722 1106 * Returns a string pointer to a status code name.
jossarr 0:8ff600c50722 1107 */
jossarr 0:8ff600c50722 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
jossarr 0:8ff600c50722 1109 {
jossarr 0:8ff600c50722 1110 return((char *) _ErrorMessage[code]);
jossarr 0:8ff600c50722 1111 } // End GetStatusCodeName()
jossarr 0:8ff600c50722 1112
jossarr 0:8ff600c50722 1113 /*
jossarr 0:8ff600c50722 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
jossarr 0:8ff600c50722 1115 */
jossarr 0:8ff600c50722 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
jossarr 0:8ff600c50722 1117 uint8_t g0,
jossarr 0:8ff600c50722 1118 uint8_t g1,
jossarr 0:8ff600c50722 1119 uint8_t g2,
jossarr 0:8ff600c50722 1120 uint8_t g3)
jossarr 0:8ff600c50722 1121 {
jossarr 0:8ff600c50722 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
jossarr 0:8ff600c50722 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
jossarr 0:8ff600c50722 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
jossarr 0:8ff600c50722 1125
jossarr 0:8ff600c50722 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
jossarr 0:8ff600c50722 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
jossarr 0:8ff600c50722 1128 accessBitBuffer[2] = c3 << 4 | c2;
jossarr 0:8ff600c50722 1129 } // End MIFARE_SetAccessBits()
jossarr 0:8ff600c50722 1130
jossarr 0:8ff600c50722 1131 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 1132 // Convenience functions - does not add extra functionality
jossarr 0:8ff600c50722 1133 /////////////////////////////////////////////////////////////////////////////////////
jossarr 0:8ff600c50722 1134
jossarr 0:8ff600c50722 1135 /*
jossarr 0:8ff600c50722 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
jossarr 0:8ff600c50722 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
jossarr 0:8ff600c50722 1138 */
jossarr 0:8ff600c50722 1139 bool MFRC522::PICC_IsNewCardPresent(void)
jossarr 0:8ff600c50722 1140 {
jossarr 0:8ff600c50722 1141 uint8_t bufferATQA[2];
jossarr 0:8ff600c50722 1142 uint8_t bufferSize = sizeof(bufferATQA);
jossarr 0:8ff600c50722 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
jossarr 0:8ff600c50722 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
jossarr 0:8ff600c50722 1145 } // End PICC_IsNewCardPresent()
jossarr 0:8ff600c50722 1146
jossarr 0:8ff600c50722 1147 /*
jossarr 0:8ff600c50722 1148 * Simple wrapper around PICC_Select.
jossarr 0:8ff600c50722 1149 */
jossarr 0:8ff600c50722 1150 bool MFRC522::PICC_ReadCardSerial(void)
jossarr 0:8ff600c50722 1151 {
jossarr 0:8ff600c50722 1152 uint8_t result = PICC_Select(&uid);
jossarr 0:8ff600c50722 1153 return (result == STATUS_OK);
jossarr 0:8ff600c50722 1154 } // End PICC_ReadCardSerial()