Diff: sdp_k1_sdram.h

Revision:

0:59a74b81fde8

Child:

1:c1da02c6a73c

diff -r 000000000000 -r 59a74b81fde8 sdp_k1_sdram.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sdp_k1_sdram.h	Thu Oct 15 14:05:13 2020 +0000
@@ -0,0 +1,64 @@
+#ifndef __SDPK1_SDRAM_H
+#define __SDPK1_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx_hal.h"
+
+/* SDRAM status defines */
+#define   SDRAM_OK         ((uint8_t)0x00)
+#define   SDRAM_ERROR      ((uint8_t)0x01)
+
+#define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000) /* SDRAM device address */
+
+#define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_32
+
+#define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
+
+#define REFRESH_COUNT                    ((uint32_t)0x0569)   /* SDRAM refresh counter (90Mhz SD clock) */
+
+#define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
+
+/* DMA definitions for SDRAM DMA transfer */
+#define __DMAx_CLK_ENABLE                 __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMAx_CLK_DISABLE                __HAL_RCC_DMA2_CLK_DISABLE
+#define SDRAM_DMAx_CHANNEL                DMA_CHANNEL_0
+#define SDRAM_DMAx_STREAM                 DMA2_Stream0
+#define SDRAM_DMAx_IRQn                   DMA2_Stream0_IRQn
+#define BSP_SDRAM_DMA_IRQHandler          DMA2_Stream0_IRQHandler
+
+/* SDRAM register defines */
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+uint8_t SDP_SDRAM_Init(void);
+uint8_t SDP_SDRAM_DeInit(void);
+void    SDP_SDRAM_Setup(uint32_t RefreshCount);
+uint8_t SDP_SDRAM_ReadData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_ReadData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_ReadData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_ReadData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_Write_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_Write_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_Write_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_WriteData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
+uint8_t SDP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
+void    SDP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
+void    SDP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif