Analog Devices / mbed-drivers

A collection of Analog Devices drivers for the mbed platform

For additional information check out the mbed page of the Analog Devices wiki: https://wiki.analog.com/resources/tools-software/mbed-drivers-all

libraries/AD7124/AD7124.h@33:c3ec596a29c2, 2016-11-07 (annotated)

Committer:
Adrian Suciu
Date:
Mon Nov 07 16:27:12 2016 +0200
Revision:
33:c3ec596a29c2
Parent:
31:511c6ff17de3 
Added CN0391, CN0396 and CN0397 shields

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Adrian Suciu 30:990ce210e8c2 1 /**
Adrian Suciu 30:990ce210e8c2 2 * @file AD7124.h
Adrian Suciu 30:990ce210e8c2 3 * @brief Header file for AD7790 ADC
Adrian Suciu 30:990ce210e8c2 4 * @author Analog Devices Inc.
Adrian Suciu 30:990ce210e8c2 5 *
Adrian Suciu 30:990ce210e8c2 6 * For support please go to:
Adrian Suciu 30:990ce210e8c2 7 * Github: https://github.com/analogdevicesinc/mbed-adi
Adrian Suciu 30:990ce210e8c2 8 * Support: https://ez.analog.com/community/linux-device-drivers/microcontroller-no-os-drivers
Adrian Suciu 30:990ce210e8c2 9 * Product: http://www.analog.com/AD7124
Adrian Suciu 30:990ce210e8c2 10 * More: https://wiki.analog.com/resources/tools-software/mbed-drivers-all
Adrian Suciu 30:990ce210e8c2 11
Adrian Suciu 30:990ce210e8c2 12 ********************************************************************************
Adrian Suciu 30:990ce210e8c2 13 * Copyright 2016(c) Analog Devices, Inc.
Adrian Suciu 30:990ce210e8c2 14 *
Adrian Suciu 30:990ce210e8c2 15 * All rights reserved.
Adrian Suciu 30:990ce210e8c2 16 *
Adrian Suciu 30:990ce210e8c2 17 * Redistribution and use in source and binary forms, with or without
Adrian Suciu 30:990ce210e8c2 18 * modification, are permitted provided that the following conditions are met:
Adrian Suciu 30:990ce210e8c2 19 * - Redistributions of source code must retain the above copyright
Adrian Suciu 30:990ce210e8c2 20 * notice, this list of conditions and the following disclaimer.
Adrian Suciu 30:990ce210e8c2 21 * - Redistributions in binary form must reproduce the above copyright
Adrian Suciu 30:990ce210e8c2 22 * notice, this list of conditions and the following disclaimer in
Adrian Suciu 30:990ce210e8c2 23 * the documentation and/or other materials provided with the
Adrian Suciu 30:990ce210e8c2 24 * distribution.
Adrian Suciu 30:990ce210e8c2 25 * - Neither the name of Analog Devices, Inc. nor the names of its
Adrian Suciu 30:990ce210e8c2 26 * contributors may be used to endorse or promote products derived
Adrian Suciu 30:990ce210e8c2 27 * from this software without specific prior written permission.
Adrian Suciu 30:990ce210e8c2 28 * - The use of this software may or may not infringe the patent rights
Adrian Suciu 30:990ce210e8c2 29 * of one or more patent holders. This license does not release you
Adrian Suciu 30:990ce210e8c2 30 * from the requirement that you obtain separate licenses from these
Adrian Suciu 30:990ce210e8c2 31 * patent holders to use this software.
Adrian Suciu 30:990ce210e8c2 32 * - Use of the software either in source or binary form, must be run
Adrian Suciu 30:990ce210e8c2 33 * on or directly connected to an Analog Devices Inc. component.
Adrian Suciu 30:990ce210e8c2 34 *
Adrian Suciu 30:990ce210e8c2 35 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
Adrian Suciu 30:990ce210e8c2 36 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
Adrian Suciu 30:990ce210e8c2 37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
Adrian Suciu 30:990ce210e8c2 38 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
Adrian Suciu 30:990ce210e8c2 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
Adrian Suciu 30:990ce210e8c2 40 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
Adrian Suciu 30:990ce210e8c2 41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Adrian Suciu 30:990ce210e8c2 42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Adrian Suciu 30:990ce210e8c2 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Adrian Suciu 30:990ce210e8c2 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Adrian Suciu 30:990ce210e8c2 45 *
Adrian Suciu 30:990ce210e8c2 46 ********************************************************************************/
Adrian Suciu 30:990ce210e8c2 47
Adrian Suciu 30:990ce210e8c2 48 #ifndef AD7790_H
Adrian Suciu 30:990ce210e8c2 49 #define AD7790_H
Adrian Suciu 30:990ce210e8c2 50
Adrian Suciu 30:990ce210e8c2 51 #include "mbed.h"
Adrian Suciu 30:990ce210e8c2 52
Adrian Suciu 30:990ce210e8c2 53 /**
Adrian Suciu 30:990ce210e8c2 54 * Comment this line if you want to turn off the debug mode.
Adrian Suciu 30:990ce210e8c2 55 * The debug mode will send a message if an exception occurs within AD7790 driver
Adrian Suciu 30:990ce210e8c2 56 */
Adrian Suciu 30:990ce210e8c2 57
Adrian Suciu 30:990ce210e8c2 58 #define AD7124_DEBUG_MODE
Adrian Suciu 30:990ce210e8c2 59
Adrian Suciu 30:990ce210e8c2 60 /**
Adrian Suciu 30:990ce210e8c2 61 * @brief Analog Devices AD7790 SPI 16-bit Buffered Sigma-Delta ADC
Adrian Suciu 30:990ce210e8c2 62 */
Adrian Suciu 30:990ce210e8c2 63 class AD7124
Adrian Suciu 30:990ce210e8c2 64 {
Adrian Suciu 30:990ce210e8c2 65 public:
Adrian Suciu 30:990ce210e8c2 66 enum ad7124_registers {
Adrian Suciu 30:990ce210e8c2 67 AD7124_Status = 0x00,
Adrian Suciu 30:990ce210e8c2 68 AD7124_ADC_Control,
Adrian Suciu 30:990ce210e8c2 69 AD7124_Data,
Adrian Suciu 30:990ce210e8c2 70 AD7124_IOCon1,
Adrian Suciu 30:990ce210e8c2 71 AD7124_IOCon2,
Adrian Suciu 30:990ce210e8c2 72 AD7124_ID,
Adrian Suciu 30:990ce210e8c2 73 AD7124_Error,
Adrian Suciu 30:990ce210e8c2 74 AD7124_Error_En,
Adrian Suciu 30:990ce210e8c2 75 AD7124_Mclk_Count,
Adrian Suciu 30:990ce210e8c2 76 AD7124_Channel_0,
Adrian Suciu 30:990ce210e8c2 77 AD7124_Channel_1,
Adrian Suciu 30:990ce210e8c2 78 AD7124_Channel_2,
Adrian Suciu 30:990ce210e8c2 79 AD7124_Channel_3,
Adrian Suciu 30:990ce210e8c2 80 AD7124_Channel_4,
Adrian Suciu 30:990ce210e8c2 81 AD7124_Channel_5,
Adrian Suciu 30:990ce210e8c2 82 AD7124_Channel_6,
Adrian Suciu 30:990ce210e8c2 83 AD7124_Channel_7,
Adrian Suciu 30:990ce210e8c2 84 AD7124_Channel_8,
Adrian Suciu 30:990ce210e8c2 85 AD7124_Channel_9,
Adrian Suciu 30:990ce210e8c2 86 AD7124_Channel_10,
Adrian Suciu 30:990ce210e8c2 87 AD7124_Channel_11,
Adrian Suciu 30:990ce210e8c2 88 AD7124_Channel_12,
Adrian Suciu 30:990ce210e8c2 89 AD7124_Channel_13,
Adrian Suciu 30:990ce210e8c2 90 AD7124_Channel_14,
Adrian Suciu 30:990ce210e8c2 91 AD7124_Channel_15,
Adrian Suciu 30:990ce210e8c2 92 AD7124_Config_0,
Adrian Suciu 30:990ce210e8c2 93 AD7124_Config_1,
Adrian Suciu 30:990ce210e8c2 94 AD7124_Config_2,
Adrian Suciu 30:990ce210e8c2 95 AD7124_Config_3,
Adrian Suciu 30:990ce210e8c2 96 AD7124_Config_4,
Adrian Suciu 30:990ce210e8c2 97 AD7124_Config_5,
Adrian Suciu 30:990ce210e8c2 98 AD7124_Config_6,
Adrian Suciu 30:990ce210e8c2 99 AD7124_Config_7,
Adrian Suciu 30:990ce210e8c2 100 AD7124_Filter_0,
Adrian Suciu 30:990ce210e8c2 101 AD7124_Filter_1,
Adrian Suciu 30:990ce210e8c2 102 AD7124_Filter_2,
Adrian Suciu 30:990ce210e8c2 103 AD7124_Filter_3,
Adrian Suciu 30:990ce210e8c2 104 AD7124_Filter_4,
Adrian Suciu 30:990ce210e8c2 105 AD7124_Filter_5,
Adrian Suciu 30:990ce210e8c2 106 AD7124_Filter_6,
Adrian Suciu 30:990ce210e8c2 107 AD7124_Filter_7,
Adrian Suciu 30:990ce210e8c2 108 AD7124_Offset_0,
Adrian Suciu 30:990ce210e8c2 109 AD7124_Offset_1,
Adrian Suciu 30:990ce210e8c2 110 AD7124_Offset_2,
Adrian Suciu 30:990ce210e8c2 111 AD7124_Offset_3,
Adrian Suciu 30:990ce210e8c2 112 AD7124_Offset_4,
Adrian Suciu 30:990ce210e8c2 113 AD7124_Offset_5,
Adrian Suciu 30:990ce210e8c2 114 AD7124_Offset_6,
Adrian Suciu 30:990ce210e8c2 115 AD7124_Offset_7,
Adrian Suciu 30:990ce210e8c2 116 AD7124_Gain_0,
Adrian Suciu 30:990ce210e8c2 117 AD7124_Gain_1,
Adrian Suciu 30:990ce210e8c2 118 AD7124_Gain_2,
Adrian Suciu 30:990ce210e8c2 119 AD7124_Gain_3,
Adrian Suciu 30:990ce210e8c2 120 AD7124_Gain_4,
Adrian Suciu 30:990ce210e8c2 121 AD7124_Gain_5,
Adrian Suciu 30:990ce210e8c2 122 AD7124_Gain_6,
Adrian Suciu 30:990ce210e8c2 123 AD7124_Gain_7,
Adrian Suciu 30:990ce210e8c2 124 AD7124_REG_NO
Adrian Suciu 30:990ce210e8c2 125 };
Adrian Suciu 30:990ce210e8c2 126 private:
Adrian Suciu 30:990ce210e8c2 127 enum {
Adrian Suciu 30:990ce210e8c2 128 AD7124_RW = 1, /* Read and Write */
Adrian Suciu 30:990ce210e8c2 129 AD7124_R = 2, /* Read only */
Adrian Suciu 30:990ce210e8c2 130 AD7124_W = 3, /* Write only */
Adrian Suciu 30:990ce210e8c2 131 } ad7124_reg_access;
Adrian Suciu 30:990ce210e8c2 132
Adrian Suciu 30:990ce210e8c2 133 /*! Device register info */
Adrian Suciu 30:990ce210e8c2 134 typedef struct _ad7124_st_reg {
Adrian Suciu 30:990ce210e8c2 135 int32_t addr;
Adrian Suciu 30:990ce210e8c2 136 int32_t value;
Adrian Suciu 30:990ce210e8c2 137 int32_t size;
Adrian Suciu 30:990ce210e8c2 138 int32_t rw;
Adrian Suciu 30:990ce210e8c2 139 } ad7124_st_reg;
Adrian Suciu 30:990ce210e8c2 140
Adrian Suciu 30:990ce210e8c2 141
Adrian Suciu 30:990ce210e8c2 142 /*! Array holding the info for the ad7124 registers - address, initial value,
Adrian Suciu 30:990ce210e8c2 143 size and access type. */
Adrian Suciu 30:990ce210e8c2 144 ad7124_st_reg ad7124_regs[57] = {
Adrian Suciu 30:990ce210e8c2 145 {0x00, 0x00, 1, 2}, /* AD7124_Status */
Adrian Suciu 30:990ce210e8c2 146 {0x01, 0x0000, 2, 1}, /* AD7124_ADC_Control */
Adrian Suciu 30:990ce210e8c2 147 {0x02, 0x0000, 3, 2}, /* AD7124_Data */
Adrian Suciu 30:990ce210e8c2 148 {0x03, 0x0000, 3, 1}, /* AD7124_IOCon1 */
Adrian Suciu 30:990ce210e8c2 149 {0x04, 0x0000, 2, 1}, /* AD7124_IOCon2 */
Adrian Suciu 30:990ce210e8c2 150 {0x05, 0x12, 1, 2}, /* AD7124_ID */
Adrian Suciu 30:990ce210e8c2 151 {0x06, 0x0000, 3, 2}, /* AD7124_Error */
Adrian Suciu 30:990ce210e8c2 152 {0x07, 0x0400, 3, 1}, /* AD7124_Error_En */
Adrian Suciu 30:990ce210e8c2 153 {0x08, 0x00, 1, 2}, /* AD7124_Mclk_Count */
Adrian Suciu 30:990ce210e8c2 154 {0x09, 0x8001, 2, 1}, /* AD7124_Channel_0 */
Adrian Suciu 30:990ce210e8c2 155 {0x0A, 0x0001, 2, 1}, /* AD7124_Channel_1 */
Adrian Suciu 30:990ce210e8c2 156 {0x0B, 0x0001, 2, 1}, /* AD7124_Channel_2 */
Adrian Suciu 30:990ce210e8c2 157 {0x0C, 0x0001, 2, 1}, /* AD7124_Channel_3 */
Adrian Suciu 30:990ce210e8c2 158 {0x0D, 0x0001, 2, 1}, /* AD7124_Channel_4 */
Adrian Suciu 30:990ce210e8c2 159 {0x0E, 0x0001, 2, 1}, /* AD7124_Channel_5 */
Adrian Suciu 30:990ce210e8c2 160 {0x0F, 0x0001, 2, 1}, /* AD7124_Channel_6 */
Adrian Suciu 30:990ce210e8c2 161 {0x10, 0x0001, 2, 1}, /* AD7124_Channel_7 */
Adrian Suciu 30:990ce210e8c2 162 {0x11, 0x0001, 2, 1}, /* AD7124_Channel_8 */
Adrian Suciu 30:990ce210e8c2 163 {0x12, 0x0001, 2, 1}, /* AD7124_Channel_9 */
Adrian Suciu 30:990ce210e8c2 164 {0x13, 0x0001, 2, 1}, /* AD7124_Channel_10 */
Adrian Suciu 30:990ce210e8c2 165 {0x14, 0x0001, 2, 1}, /* AD7124_Channel_11 */
Adrian Suciu 30:990ce210e8c2 166 {0x15, 0x0001, 2, 1}, /* AD7124_Channel_12 */
Adrian Suciu 30:990ce210e8c2 167 {0x16, 0x0001, 2, 1}, /* AD7124_Channel_13 */
Adrian Suciu 30:990ce210e8c2 168 {0x17, 0x0001, 2, 1}, /* AD7124_Channel_14 */
Adrian Suciu 30:990ce210e8c2 169 {0x18, 0x0001, 2, 1}, /* AD7124_Channel_15 */
Adrian Suciu 30:990ce210e8c2 170 {0x19, 0x0860, 2, 1}, /* AD7124_Config_0 */
Adrian Suciu 30:990ce210e8c2 171 {0x1A, 0x0860, 2, 1}, /* AD7124_Config_1 */
Adrian Suciu 30:990ce210e8c2 172 {0x1B, 0x0860, 2, 1}, /* AD7124_Config_2 */
Adrian Suciu 30:990ce210e8c2 173 {0x1C, 0x0860, 2, 1}, /* AD7124_Config_3 */
Adrian Suciu 30:990ce210e8c2 174 {0x1D, 0x0860, 2, 1}, /* AD7124_Config_4 */
Adrian Suciu 30:990ce210e8c2 175 {0x1E, 0x0860, 2, 1}, /* AD7124_Config_5 */
Adrian Suciu 30:990ce210e8c2 176 {0x1F, 0x0860, 2, 1}, /* AD7124_Config_6 */
Adrian Suciu 30:990ce210e8c2 177 {0x20, 0x0860, 2, 1}, /* AD7124_Config_7 */
Adrian Suciu 30:990ce210e8c2 178 {0x21, 0x060180, 3, 1}, /* AD7124_Filter_0 */
Adrian Suciu 30:990ce210e8c2 179 {0x22, 0x060180, 3, 1}, /* AD7124_Filter_1 */
Adrian Suciu 30:990ce210e8c2 180 {0x23, 0x060180, 3, 1}, /* AD7124_Filter_2 */
Adrian Suciu 30:990ce210e8c2 181 {0x24, 0x060180, 3, 1}, /* AD7124_Filter_3 */
Adrian Suciu 30:990ce210e8c2 182 {0x25, 0x060180, 3, 1}, /* AD7124_Filter_4 */
Adrian Suciu 30:990ce210e8c2 183 {0x26, 0x060180, 3, 1}, /* AD7124_Filter_5 */
Adrian Suciu 30:990ce210e8c2 184 {0x27, 0x060180, 3, 1}, /* AD7124_Filter_6 */
Adrian Suciu 30:990ce210e8c2 185 {0x28, 0x060180, 3, 1}, /* AD7124_Filter_7 */
Adrian Suciu 30:990ce210e8c2 186 {0x29, 0x800000, 3, 1}, /* AD7124_Offset_0 */
Adrian Suciu 30:990ce210e8c2 187 {0x2A, 0x800000, 3, 1}, /* AD7124_Offset_1 */
Adrian Suciu 30:990ce210e8c2 188 {0x2B, 0x800000, 3, 1}, /* AD7124_Offset_2 */
Adrian Suciu 30:990ce210e8c2 189 {0x2C, 0x800000, 3, 1}, /* AD7124_Offset_3 */
Adrian Suciu 30:990ce210e8c2 190 {0x2D, 0x800000, 3, 1}, /* AD7124_Offset_4 */
Adrian Suciu 30:990ce210e8c2 191 {0x2E, 0x800000, 3, 1}, /* AD7124_Offset_5 */
Adrian Suciu 30:990ce210e8c2 192 {0x2F, 0x800000, 3, 1}, /* AD7124_Offset_6 */
Adrian Suciu 30:990ce210e8c2 193 {0x30, 0x800000, 3, 1}, /* AD7124_Offset_7 */
Adrian Suciu 30:990ce210e8c2 194 {0x31, 0x500000, 3, 1}, /* AD7124_Gain_0 */
Adrian Suciu 30:990ce210e8c2 195 {0x32, 0x500000, 3, 1}, /* AD7124_Gain_1 */
Adrian Suciu 30:990ce210e8c2 196 {0x33, 0x500000, 3, 1}, /* AD7124_Gain_2 */
Adrian Suciu 30:990ce210e8c2 197 {0x34, 0x500000, 3, 1}, /* AD7124_Gain_3 */
Adrian Suciu 30:990ce210e8c2 198 {0x35, 0x500000, 3, 1}, /* AD7124_Gain_4 */
Adrian Suciu 30:990ce210e8c2 199 {0x36, 0x500000, 3, 1}, /* AD7124_Gain_5 */
Adrian Suciu 30:990ce210e8c2 200 {0x37, 0x500000, 3, 1}, /* AD7124_Gain_6 */
Adrian Suciu 30:990ce210e8c2 201 {0x38, 0x500000, 3, 1}, /* AD7124_Gain_7 */
Adrian Suciu 30:990ce210e8c2 202 };
Adrian Suciu 30:990ce210e8c2 203
Adrian Suciu 30:990ce210e8c2 204
Adrian Suciu 30:990ce210e8c2 205 /* AD7124 Register Map */
Adrian Suciu 30:990ce210e8c2 206 enum AD7124_reg_map {
Adrian Suciu 30:990ce210e8c2 207 COMM_REG = 0x00,
Adrian Suciu 30:990ce210e8c2 208 STATUS_REG = 0x00,
Adrian Suciu 30:990ce210e8c2 209 ADC_CTRL_REG = 0x01,
Adrian Suciu 30:990ce210e8c2 210 DATA_REG = 0x02,
Adrian Suciu 30:990ce210e8c2 211 IO_CTRL1_REG = 0x03,
Adrian Suciu 30:990ce210e8c2 212 IO_CTRL2_REG = 0x04,
Adrian Suciu 30:990ce210e8c2 213 ID_REG = 0x05,
Adrian Suciu 30:990ce210e8c2 214 ERR_REG = 0x06,
Adrian Suciu 30:990ce210e8c2 215 ERREN_REG = 0x07,
Adrian Suciu 30:990ce210e8c2 216 CH0_MAP_REG = 0x09,
Adrian Suciu 30:990ce210e8c2 217 CH1_MAP_REG = 0x0A,
Adrian Suciu 30:990ce210e8c2 218 CH2_MAP_REG = 0x0B,
Adrian Suciu 30:990ce210e8c2 219 CH3_MAP_REG = 0x0C,
Adrian Suciu 30:990ce210e8c2 220 CH4_MAP_REG = 0x0D,
Adrian Suciu 30:990ce210e8c2 221 CH5_MAP_REG = 0x0E,
Adrian Suciu 30:990ce210e8c2 222 CH6_MAP_REG = 0x0F,
Adrian Suciu 30:990ce210e8c2 223 CH7_MAP_REG = 0x10,
Adrian Suciu 30:990ce210e8c2 224 CH8_MAP_REG = 0x11,
Adrian Suciu 30:990ce210e8c2 225 CH9_MAP_REG = 0x12,
Adrian Suciu 30:990ce210e8c2 226 CH10_MAP_REG = 0x13,
Adrian Suciu 30:990ce210e8c2 227 CH11_MAP_REG = 0x14,
Adrian Suciu 30:990ce210e8c2 228 CH12_MAP_REG = 0x15,
Adrian Suciu 30:990ce210e8c2 229 CH13_MAP_REG = 0x16,
Adrian Suciu 30:990ce210e8c2 230 CH14_MAP_REG = 0x17,
Adrian Suciu 30:990ce210e8c2 231 CH15_MAP_REG = 0x18,
Adrian Suciu 30:990ce210e8c2 232 CFG0_REG = 0x19,
Adrian Suciu 30:990ce210e8c2 233 CFG1_REG = 0x1A,
Adrian Suciu 30:990ce210e8c2 234 CFG2_REG = 0x1B,
Adrian Suciu 30:990ce210e8c2 235 CFG3_REG = 0x1C,
Adrian Suciu 30:990ce210e8c2 236 CFG4_REG = 0x1D,
Adrian Suciu 30:990ce210e8c2 237 CFG5_REG = 0x1E,
Adrian Suciu 30:990ce210e8c2 238 CFG6_REG = 0x1F,
Adrian Suciu 30:990ce210e8c2 239 CFG7_REG = 0x20,
Adrian Suciu 30:990ce210e8c2 240 FILT0_REG = 0x21,
Adrian Suciu 30:990ce210e8c2 241 FILT1_REG = 0x22,
Adrian Suciu 30:990ce210e8c2 242 FILT2_REG = 0x23,
Adrian Suciu 30:990ce210e8c2 243 FILT3_REG = 0x24,
Adrian Suciu 30:990ce210e8c2 244 FILT4_REG = 0x25,
Adrian Suciu 30:990ce210e8c2 245 FILT5_REG = 0x26,
Adrian Suciu 30:990ce210e8c2 246 FILT6_REG = 0x27,
Adrian Suciu 30:990ce210e8c2 247 FILT7_REG = 0x28,
Adrian Suciu 30:990ce210e8c2 248 OFFS0_REG = 0x29,
Adrian Suciu 30:990ce210e8c2 249 OFFS1_REG = 0x2A,
Adrian Suciu 30:990ce210e8c2 250 OFFS2_REG = 0x2B,
Adrian Suciu 30:990ce210e8c2 251 OFFS3_REG = 0x2C,
Adrian Suciu 30:990ce210e8c2 252 OFFS4_REG = 0x2D,
Adrian Suciu 30:990ce210e8c2 253 OFFS5_REG = 0x2E,
Adrian Suciu 30:990ce210e8c2 254 OFFS6_REG = 0x2F,
Adrian Suciu 30:990ce210e8c2 255 OFFS7_REG = 0x30,
Adrian Suciu 30:990ce210e8c2 256 GAIN0_REG = 0x31,
Adrian Suciu 30:990ce210e8c2 257 GAIN1_REG = 0x32,
Adrian Suciu 30:990ce210e8c2 258 GAIN2_REG = 0x33,
Adrian Suciu 30:990ce210e8c2 259 GAIN3_REG = 0x34,
Adrian Suciu 30:990ce210e8c2 260 GAIN4_REG = 0x35,
Adrian Suciu 30:990ce210e8c2 261 GAIN5_REG = 0x36,
Adrian Suciu 30:990ce210e8c2 262 GAIN6_REG = 0x37,
Adrian Suciu 30:990ce210e8c2 263 GAIN7_REG = 0x38,
Adrian Suciu 30:990ce210e8c2 264 };
Adrian Suciu 30:990ce210e8c2 265
Adrian Suciu 30:990ce210e8c2 266 /* Communication Register bits */
Adrian Suciu 30:990ce210e8c2 267 #define AD7124_COMM_REG_WEN (0 << 7)
Adrian Suciu 30:990ce210e8c2 268 #define AD7124_COMM_REG_WR (0 << 6)
Adrian Suciu 30:990ce210e8c2 269 #define AD7124_COMM_REG_RD (1 << 6)
Adrian Suciu 30:990ce210e8c2 270 #define AD7124_COMM_REG_RA(x) ((x) & 0x3F)
Adrian Suciu 30:990ce210e8c2 271
Adrian Suciu 30:990ce210e8c2 272 /* Status Register bits */
Adrian Suciu 30:990ce210e8c2 273 #define AD7124_STATUS_REG_RDY (1 << 7)
Adrian Suciu 30:990ce210e8c2 274 #define AD7124_STATUS_REG_ERROR_FLAG (1 << 6)
Adrian Suciu 30:990ce210e8c2 275 #define AD7124_STATUS_REG_POR_FLAG (1 << 4)
Adrian Suciu 30:990ce210e8c2 276 #define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF)
Adrian Suciu 30:990ce210e8c2 277
Adrian Suciu 30:990ce210e8c2 278 /* ADC_Control Register bits */
Adrian Suciu 30:990ce210e8c2 279 #define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL (1 << 12)
Adrian Suciu 30:990ce210e8c2 280 #define AD7124_ADC_CTRL_REG_CONT_READ (1 << 11)
Adrian Suciu 30:990ce210e8c2 281 #define AD7124_ADC_CTRL_REG_DATA_STATUS (1 << 10)
Adrian Suciu 30:990ce210e8c2 282 #define AD7124_ADC_CTRL_REG_CS_EN (1 << 9)
Adrian Suciu 30:990ce210e8c2 283 #define AD7124_ADC_CTRL_REG_REF_EN (1 << 8)
Adrian Suciu 30:990ce210e8c2 284 #define AD7124_ADC_CTRL_REG_POWER_MODE(x) (((x) & 0x3) << 6)
Adrian Suciu 30:990ce210e8c2 285 #define AD7124_ADC_CTRL_REG_MODE(x) (((x) & 0xF) << 2)
Adrian Suciu 30:990ce210e8c2 286 #define AD7124_ADC_CTRL_REG_CLK_SEL(x) (((x) & 0x3) << 0)
Adrian Suciu 30:990ce210e8c2 287
Adrian Suciu 30:990ce210e8c2 288 /* IO_Control_1 Register bits */
Adrian Suciu 30:990ce210e8c2 289 #define AD7124_IO_CTRL1_REG_GPIO_DAT2 (1 << 23)
Adrian Suciu 30:990ce210e8c2 290 #define AD7124_IO_CTRL1_REG_GPIO_DAT1 (1 << 22)
Adrian Suciu 30:990ce210e8c2 291 #define AD7124_IO_CTRL1_REG_GPIO_CTRL2 (1 << 19)
Adrian Suciu 30:990ce210e8c2 292 #define AD7124_IO_CTRL1_REG_GPIO_CTRL1 (1 << 18)
Adrian Suciu 30:990ce210e8c2 293 #define AD7124_IO_CTRL1_REG_PDSW (1 << 15)
Adrian Suciu 30:990ce210e8c2 294 #define AD7124_IO_CTRL1_REG_IOUT1(x) (((x) & 0x7) << 11)
Adrian Suciu 30:990ce210e8c2 295 #define AD7124_IO_CTRL1_REG_IOUT0(x) (((x) & 0x7) << 8)
Adrian Suciu 30:990ce210e8c2 296 #define AD7124_IO_CTRL1_REG_IOUT_CH1(x) (((x) & 0xF) << 4)
Adrian Suciu 30:990ce210e8c2 297 #define AD7124_IO_CTRL1_REG_IOUT_CH0(x) (((x) & 0xF) << 0)
Adrian Suciu 30:990ce210e8c2 298
Adrian Suciu 30:990ce210e8c2 299 /*IO_Control_1 AD7124-8 specific bits */
Adrian Suciu 30:990ce210e8c2 300 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 (1 << 23)
Adrian Suciu 30:990ce210e8c2 301 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT3 (1 << 22)
Adrian Suciu 30:990ce210e8c2 302 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT2 (1 << 21)
Adrian Suciu 30:990ce210e8c2 303 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT1 (1 << 20)
Adrian Suciu 30:990ce210e8c2 304 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4 (1 << 19)
Adrian Suciu 30:990ce210e8c2 305 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3 (1 << 18)
Adrian Suciu 30:990ce210e8c2 306 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2 (1 << 17)
Adrian Suciu 30:990ce210e8c2 307 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1 (1 << 16)
Adrian Suciu 30:990ce210e8c2 308
Adrian Suciu 30:990ce210e8c2 309 /* IO_Control_2 Register bits */
Adrian Suciu 30:990ce210e8c2 310 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 15)
Adrian Suciu 30:990ce210e8c2 311 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 14)
Adrian Suciu 30:990ce210e8c2 312 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 11)
Adrian Suciu 30:990ce210e8c2 313 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 10)
Adrian Suciu 30:990ce210e8c2 314 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 5)
Adrian Suciu 30:990ce210e8c2 315 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 4)
Adrian Suciu 30:990ce210e8c2 316 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
Adrian Suciu 30:990ce210e8c2 317 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS0 (1)
Adrian Suciu 30:990ce210e8c2 318
Adrian Suciu 30:990ce210e8c2 319 /*IO_Control_2 AD7124-8 specific bits */
Adrian Suciu 30:990ce210e8c2 320 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15 (1 << 15)
Adrian Suciu 30:990ce210e8c2 321 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14 (1 << 14)
Adrian Suciu 30:990ce210e8c2 322 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13 (1 << 13)
Adrian Suciu 30:990ce210e8c2 323 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12 (1 << 12)
Adrian Suciu 30:990ce210e8c2 324 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11 (1 << 11)
Adrian Suciu 30:990ce210e8c2 325 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10 (1 << 10)
Adrian Suciu 30:990ce210e8c2 326 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9 (1 << 9)
Adrian Suciu 30:990ce210e8c2 327 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8 (1 << 8)
Adrian Suciu 30:990ce210e8c2 328 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 7)
Adrian Suciu 30:990ce210e8c2 329 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 6)
Adrian Suciu 30:990ce210e8c2 330 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 5)
Adrian Suciu 30:990ce210e8c2 331 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 4)
Adrian Suciu 30:990ce210e8c2 332 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 3)
Adrian Suciu 30:990ce210e8c2 333 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 2)
Adrian Suciu 30:990ce210e8c2 334 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
Adrian Suciu 30:990ce210e8c2 335 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0)
Adrian Suciu 30:990ce210e8c2 336
Adrian Suciu 30:990ce210e8c2 337 /* ID Register bits */
Adrian Suciu 30:990ce210e8c2 338 #define AD7124_ID_REG_DEVICE_ID(x) (((x) & 0xF) << 4)
Adrian Suciu 30:990ce210e8c2 339 #define AD7124_ID_REG_SILICON_REV(x) (((x) & 0xF) << 0)
Adrian Suciu 30:990ce210e8c2 340
Adrian Suciu 30:990ce210e8c2 341 /* Error Register bits */
Adrian Suciu 30:990ce210e8c2 342 #define AD7124_ERR_REG_LDO_CAP_ERR (1 << 19)
Adrian Suciu 30:990ce210e8c2 343 #define AD7124_ERR_REG_ADC_CAL_ERR (1 << 18)
Adrian Suciu 30:990ce210e8c2 344 #define AD7124_ERR_REG_ADC_CONV_ERR (1 << 17)
Adrian Suciu 30:990ce210e8c2 345 #define AD7124_ERR_REG_ADC_SAT_ERR (1 << 16)
Adrian Suciu 30:990ce210e8c2 346 #define AD7124_ERR_REG_AINP_OV_ERR (1 << 15)
Adrian Suciu 30:990ce210e8c2 347 #define AD7124_ERR_REG_AINP_UV_ERR (1 << 14)
Adrian Suciu 30:990ce210e8c2 348 #define AD7124_ERR_REG_AINM_OV_ERR (1 << 13)
Adrian Suciu 30:990ce210e8c2 349 #define AD7124_ERR_REG_AINM_UV_ERR (1 << 12)
Adrian Suciu 30:990ce210e8c2 350 #define AD7124_ERR_REG_REF_DET_ERR (1 << 11)
Adrian Suciu 30:990ce210e8c2 351 #define AD7124_ERR_REG_DLDO_PSM_ERR (1 << 9)
Adrian Suciu 30:990ce210e8c2 352 #define AD7124_ERR_REG_ALDO_PSM_ERR (1 << 7)
Adrian Suciu 30:990ce210e8c2 353 #define AD7124_ERR_REG_SPI_IGNORE_ERR (1 << 6)
Adrian Suciu 30:990ce210e8c2 354 #define AD7124_ERR_REG_SPI_SLCK_CNT_ERR (1 << 5)
Adrian Suciu 30:990ce210e8c2 355 #define AD7124_ERR_REG_SPI_READ_ERR (1 << 4)
Adrian Suciu 30:990ce210e8c2 356 #define AD7124_ERR_REG_SPI_WRITE_ERR (1 << 3)
Adrian Suciu 30:990ce210e8c2 357 #define AD7124_ERR_REG_SPI_CRC_ERR (1 << 2)
Adrian Suciu 30:990ce210e8c2 358 #define AD7124_ERR_REG_MM_CRC_ERR (1 << 1)
Adrian Suciu 30:990ce210e8c2 359
Adrian Suciu 30:990ce210e8c2 360 /* Error_En Register bits */
Adrian Suciu 30:990ce210e8c2 361 #define AD7124_ERREN_REG_MCLK_CNT_EN (1 << 22)
Adrian Suciu 30:990ce210e8c2 362 #define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN (1 << 21)
Adrian Suciu 30:990ce210e8c2 363 #define AD7124_ERREN_REG_LDO_CAP_CHK(x) (((x) & 0x3) << 19)
Adrian Suciu 30:990ce210e8c2 364 #define AD7124_ERREN_REG_ADC_CAL_ERR_EN (1 << 18)
Adrian Suciu 30:990ce210e8c2 365 #define AD7124_ERREN_REG_ADC_CONV_ERR_EN (1 << 17)
Adrian Suciu 30:990ce210e8c2 366 #define AD7124_ERREN_REG_ADC_SAT_ERR_EN (1 << 16)
Adrian Suciu 30:990ce210e8c2 367 #define AD7124_ERREN_REG_AINP_OV_ERR_EN (1 << 15)
Adrian Suciu 30:990ce210e8c2 368 #define AD7124_ERREN_REG_AINP_UV_ERR_EN (1 << 14)
Adrian Suciu 30:990ce210e8c2 369 #define AD7124_ERREN_REG_AINM_OV_ERR_EN (1 << 13)
Adrian Suciu 30:990ce210e8c2 370 #define AD7124_ERREN_REG_AINM_UV_ERR_EN (1 << 12)
Adrian Suciu 30:990ce210e8c2 371 #define AD7124_ERREN_REG_REF_DET_ERR_EN (1 << 11)
Adrian Suciu 30:990ce210e8c2 372 #define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN (1 << 10)
Adrian Suciu 30:990ce210e8c2 373 #define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR (1 << 9)
Adrian Suciu 30:990ce210e8c2 374 #define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN (1 << 8)
Adrian Suciu 30:990ce210e8c2 375 #define AD7124_ERREN_REG_ALDO_PSM_ERR_EN (1 << 7)
Adrian Suciu 30:990ce210e8c2 376 #define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN (1 << 6)
Adrian Suciu 30:990ce210e8c2 377 #define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN (1 << 5)
Adrian Suciu 30:990ce210e8c2 378 #define AD7124_ERREN_REG_SPI_READ_ERR_EN (1 << 4)
Adrian Suciu 30:990ce210e8c2 379 #define AD7124_ERREN_REG_SPI_WRITE_ERR_EN (1 << 3)
Adrian Suciu 30:990ce210e8c2 380 #define AD7124_ERREN_REG_SPI_CRC_ERR_EN (1 << 2)
Adrian Suciu 30:990ce210e8c2 381 #define AD7124_ERREN_REG_MM_CRC_ERR_EN (1 << 1)
Adrian Suciu 30:990ce210e8c2 382
Adrian Suciu 30:990ce210e8c2 383 /* Channel Registers 0-15 bits */
Adrian Suciu 30:990ce210e8c2 384 #define AD7124_CH_MAP_REG_CH_ENABLE (1 << 15)
Adrian Suciu 30:990ce210e8c2 385 #define AD7124_CH_MAP_REG_SETUP(x) (((x) & 0x7) << 12)
Adrian Suciu 30:990ce210e8c2 386 #define AD7124_CH_MAP_REG_AINP(x) (((x) & 0x1F) << 5)
Adrian Suciu 30:990ce210e8c2 387 #define AD7124_CH_MAP_REG_AINM(x) (((x) & 0x1F) << 0)
Adrian Suciu 30:990ce210e8c2 388
Adrian Suciu 30:990ce210e8c2 389 /* Configuration Registers 0-7 bits */
Adrian Suciu 30:990ce210e8c2 390 #define AD7124_CFG_REG_BIPOLAR (1 << 11)
Adrian Suciu 30:990ce210e8c2 391 #define AD7124_CFG_REG_BURNOUT(x) (((x) & 0x3) << 9)
Adrian Suciu 30:990ce210e8c2 392 #define AD7124_CFG_REG_REF_BUFP (1 << 8)
Adrian Suciu 30:990ce210e8c2 393 #define AD7124_CFG_REG_REF_BUFM (1 << 7)
Adrian Suciu 30:990ce210e8c2 394 #define AD7124_CFG_REG_AIN_BUFP (1 << 6)
Adrian Suciu 30:990ce210e8c2 395 #define AD7124_CFG_REG_AINN_BUFM (1 << 5)
Adrian Suciu 30:990ce210e8c2 396 #define AD7124_CFG_REG_REF_SEL(x) ((x) & 0x3) << 3
Adrian Suciu 30:990ce210e8c2 397 #define AD7124_CFG_REG_PGA(x) (((x) & 0x7) << 0)
Adrian Suciu 30:990ce210e8c2 398
Adrian Suciu 30:990ce210e8c2 399 /* Filter Register 0-7 bits */
Adrian Suciu 30:990ce210e8c2 400 #define AD7124_FILT_REG_FILTER(x) ((uint32_t)((x) & 0x7) << 21)
Adrian Suciu 30:990ce210e8c2 401 #define AD7124_FILT_REG_REJ60 ((uint32_t)1 << 20)
Adrian Suciu 30:990ce210e8c2 402 #define AD7124_FILT_REG_POST_FILTER(x) ((uint32_t)((x) & 0x7) << 17)
Adrian Suciu 30:990ce210e8c2 403 #define AD7124_FILT_REG_SINGLE_CYCLE ((uint32_t)1 << 16)
Adrian Suciu 30:990ce210e8c2 404 #define AD7124_FILT_REG_FS(x) ((uint32_t)((x) & 0x7FF) << 0)
Adrian Suciu 30:990ce210e8c2 405
Adrian Suciu 30:990ce210e8c2 406 public:
Adrian Suciu 30:990ce210e8c2 407
Adrian Suciu 30:990ce210e8c2 408 /** SPI configuration & constructor */
Adrian Suciu 30:990ce210e8c2 409 AD7124( PinName CS = SPI_CS, PinName MOSI = SPI_MOSI, PinName MISO = SPI_MISO, PinName SCK = SPI_SCK);
Adrian Suciu 30:990ce210e8c2 410 void frequency(int hz);
Adrian Suciu 30:990ce210e8c2 411
Adrian Suciu 30:990ce210e8c2 412 /** Low level SPI bus comm methods */
Adrian Suciu 30:990ce210e8c2 413 void reset(void);
Adrian Suciu 30:990ce210e8c2 414
Adrian Suciu 30:990ce210e8c2 415 void write_reg(uint8_t regAddress, uint8_t regValue);
Adrian Suciu 30:990ce210e8c2 416 uint16_t write_spi(uint16_t data);
Adrian Suciu 30:990ce210e8c2 417 uint16_t read_reg (uint8_t regAddress);
Adrian Suciu 30:990ce210e8c2 418 bool get_miso();
Adrian Suciu 30:990ce210e8c2 419
Adrian Suciu 30:990ce210e8c2 420
Adrian Suciu 30:990ce210e8c2 421 int32_t Reset();
Adrian Suciu 30:990ce210e8c2 422 /* Reads and returns the value of a device register. */
Adrian Suciu 30:990ce210e8c2 423 uint32_t ReadDeviceRegister(enum ad7124_registers reg);
Adrian Suciu 30:990ce210e8c2 424
Adrian Suciu 30:990ce210e8c2 425 /* Writes the specified value to a device register. */
Adrian Suciu 30:990ce210e8c2 426 int32_t WriteDeviceRegister(enum ad7124_registers reg, uint32_t value);
Adrian Suciu 30:990ce210e8c2 427
Adrian Suciu 30:990ce210e8c2 428 /*! Reads the value of the specified register. */
Adrian Suciu 30:990ce210e8c2 429 int32_t ReadRegister(ad7124_st_reg* pReg);
Adrian Suciu 30:990ce210e8c2 430
Adrian Suciu 30:990ce210e8c2 431 /*! Writes the value of the specified register. */
Adrian Suciu 30:990ce210e8c2 432 int32_t WriteRegister(ad7124_st_reg reg);
Adrian Suciu 30:990ce210e8c2 433
Adrian Suciu 30:990ce210e8c2 434 /*! Reads the value of the specified register without a device state check. */
Adrian Suciu 30:990ce210e8c2 435 int32_t NoCheckReadRegister(ad7124_st_reg* pReg);
Adrian Suciu 30:990ce210e8c2 436
Adrian Suciu 30:990ce210e8c2 437 /*! Writes the value of the specified register without a device state check. */
Adrian Suciu 30:990ce210e8c2 438 int32_t NoCheckWriteRegister(ad7124_st_reg reg);
Adrian Suciu 30:990ce210e8c2 439
Adrian Suciu 30:990ce210e8c2 440 /*! Waits until the device can accept read and write user actions. */
Adrian Suciu 30:990ce210e8c2 441 int32_t WaitForSpiReady(uint32_t timeout);
Adrian Suciu 30:990ce210e8c2 442
Adrian Suciu 30:990ce210e8c2 443 /*! Waits until a new conversion result is available. */
Adrian Suciu 30:990ce210e8c2 444 int32_t WaitForConvReady(uint32_t timeout);
Adrian Suciu 30:990ce210e8c2 445
Adrian Suciu 30:990ce210e8c2 446 /*! Reads the conversion result from the device. */
Adrian Suciu 30:990ce210e8c2 447 int32_t ReadData(int32_t* pData);
Adrian Suciu 30:990ce210e8c2 448
Adrian Suciu 30:990ce210e8c2 449 /*! Computes the CRC checksum for a data buffer. */
Adrian Suciu 30:990ce210e8c2 450 uint8_t ComputeCRC8(uint8_t* pBuf, uint8_t bufSize);
Adrian Suciu 30:990ce210e8c2 451
Adrian Suciu 30:990ce210e8c2 452 /*! Updates the device SPI interface settings. */
Adrian Suciu 30:990ce210e8c2 453 void UpdateDevSpiSettings();
Adrian Suciu 30:990ce210e8c2 454
Adrian Suciu 30:990ce210e8c2 455 /*! Initializes the AD7124. */
Adrian Suciu 30:990ce210e8c2 456 int32_t Setup();
Adrian Suciu 30:990ce210e8c2 457
Adrian Suciu 30:990ce210e8c2 458 uint8_t SPI_Read(uint8_t *data, uint8_t bytes_number);
Adrian Suciu 30:990ce210e8c2 459 uint8_t SPI_Write(uint8_t *data, uint8_t bytes_number);
Adrian Suciu 30:990ce210e8c2 460
Adrian Suciu 30:990ce210e8c2 461 DigitalIn miso;///< DigitalIn must be initialized before SPI to prevent pin MUX overwrite
Adrian Suciu 30:990ce210e8c2 462 SPI ad7124; ///< SPI instance of the AD7790
Adrian Suciu 30:990ce210e8c2 463 DigitalOut cs; ///< DigitalOut instance for the chipselect of the AD7790
Adrian Suciu 30:990ce210e8c2 464
Adrian Suciu 30:990ce210e8c2 465 private:
Adrian Suciu 30:990ce210e8c2 466
Adrian Suciu 30:990ce210e8c2 467
Adrian Suciu 30:990ce210e8c2 468 ad7124_st_reg *regs; // reg map 38 bytes ?
Adrian Suciu 30:990ce210e8c2 469 uint8_t useCRC; // boolean ?
Adrian Suciu 30:990ce210e8c2 470 int check_ready; // ?
Adrian Suciu 30:990ce210e8c2 471 int spi_rdy_poll_cnt; // timer ?
Adrian Suciu 30:990ce210e8c2 472
Adrian Suciu 30:990ce210e8c2 473 const static uint8_t _SPI_MODE = 0x03;
Adrian Suciu 30:990ce210e8c2 474 const static uint8_t _RESET = 0xFF;
Adrian Suciu 30:990ce210e8c2 475 const static uint8_t _DUMMY_BYTE = 0xFF;
Adrian Suciu 30:990ce210e8c2 476 const static uint16_t _READ_FLAG = 0x4000;
Adrian Suciu 30:990ce210e8c2 477 const static uint8_t _DELAY_TIMING = 0x02;
Adrian Suciu 30:990ce210e8c2 478
Adrian Suciu 30:990ce210e8c2 479 #define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */
Adrian Suciu 30:990ce210e8c2 480 #define AD7124_DISABLE_CRC 0
Adrian Suciu 30:990ce210e8c2 481 #define AD7124_USE_CRC 1
Adrian Suciu 30:990ce210e8c2 482 #define AD7124_READ_DATA 2
Adrian Suciu 30:990ce210e8c2 483
Adrian Suciu 30:990ce210e8c2 484 #define INVALID_VAL -1 /* Invalid argument */
Adrian Suciu 30:990ce210e8c2 485 #define COMM_ERR -2 /* Communication error on receive */
Adrian Suciu 30:990ce210e8c2 486 #define TIMEOUT -3 /* A timeout has occured */
Adrian Suciu 30:990ce210e8c2 487
Adrian Suciu 30:990ce210e8c2 488 };
Adrian Suciu 30:990ce210e8c2 489 #endif
Adrian Suciu 30:990ce210e8c2 490
Adrian Suciu 30:990ce210e8c2 491