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Program files for Example program for EVAL-AD7768-1
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ad77681.h
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00001 /***************************************************************************//** 00002 * @file ad77681.h 00003 * @brief Header file of the AD7768-1 Driver. 00004 * @author SPopa (stefan.popa@analog.com) 00005 ******************************************************************************** 00006 * Copyright 2017(c) Analog Devices, Inc. 00007 * 00008 * All rights reserved. 00009 * 00010 * Redistribution and use in source and binary forms, with or without 00011 * modification, are permitted provided that the following conditions are met: 00012 * - Redistributions of source code must retain the above copyright 00013 * notice, this list of conditions and the following disclaimer. 00014 * - Redistributions in binary form must reproduce the above copyright 00015 * notice, this list of conditions and the following disclaimer in 00016 * the documentation and/or other materials provided with the 00017 * distribution. 00018 * - Neither the name of Analog Devices, Inc. nor the names of its 00019 * contributors may be used to endorse or promote products derived 00020 * from this software without specific prior written permission. 00021 * - The use of this software may or may not infringe the patent rights 00022 * of one or more patent holders. This license does not release you 00023 * from the requirement that you obtain separate licenses from these 00024 * patent holders to use this software. 00025 * - Use of the software either in source or binary form, must be run 00026 * on or directly connected to an Analog Devices Inc. component. 00027 * 00028 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR 00029 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, 00030 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 00031 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, 00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00033 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR 00034 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00036 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00037 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00038 *******************************************************************************/ 00039 00040 #ifndef SRC_AD77681_H_ 00041 #define SRC_AD77681_H_ 00042 00043 //#include "spi_engine.h" 00044 00045 #include "spi.h" 00046 #include <stdbool.h> 00047 00048 /******************************************************************************/ 00049 /********************** Macros and Constants Definitions **********************/ 00050 /******************************************************************************/ 00051 #define AD77681_REG_CHIP_TYPE 0x3 00052 #define AD77681_REG_PROD_ID_L 0x4 00053 #define AD77681_REG_PROD_ID_H 0x5 00054 #define AD77681_REG_CHIP_GRADE 0x6 00055 #define AD77681_REG_SCRATCH_PAD 0x0A 00056 #define AD77681_REG_VENDOR_L 0x0C 00057 #define AD77681_REG_VENDOR_H 0x0D 00058 #define AD77681_REG_INTERFACE_FORMAT 0x14 00059 #define AD77681_REG_POWER_CLOCK 0x15 00060 #define AD77681_REG_ANALOG 0x16 00061 #define AD77681_REG_ANALOG2 0x17 00062 #define AD77681_REG_CONVERSION 0x18 00063 #define AD77681_REG_DIGITAL_FILTER 0x19 00064 #define AD77681_REG_SINC3_DEC_RATE_MSB 0x1A 00065 #define AD77681_REG_SINC3_DEC_RATE_LSB 0x1B 00066 #define AD77681_REG_DUTY_CYCLE_RATIO 0x1C 00067 #define AD77681_REG_SYNC_RESET 0x1D 00068 #define AD77681_REG_GPIO_CONTROL 0x1E 00069 #define AD77681_REG_GPIO_WRITE 0x1F 00070 #define AD77681_REG_GPIO_READ 0x20 00071 #define AD77681_REG_OFFSET_HI 0x21 00072 #define AD77681_REG_OFFSET_MID 0x22 00073 #define AD77681_REG_OFFSET_LO 0x23 00074 #define AD77681_REG_GAIN_HI 0x24 00075 #define AD77681_REG_GAIN_MID 0x25 00076 #define AD77681_REG_GAIN_LO 0x26 00077 #define AD77681_REG_SPI_DIAG_ENABLE 0x28 00078 #define AD77681_REG_ADC_DIAG_ENABLE 0x29 00079 #define AD77681_REG_DIG_DIAG_ENABLE 0x2A 00080 #define AD77681_REG_ADC_DATA 0x2C 00081 #define AD77681_REG_MASTER_STATUS 0x2D 00082 #define AD77681_REG_SPI_DIAG_STATUS 0x2E 00083 #define AD77681_REG_ADC_DIAG_STATUS 0x2F 00084 #define AD77681_REG_DIG_DIAG_STATUS 0x30 00085 #define AD77681_REG_MCLK_COUNTER 0x31 00086 00087 /* AD77681_REG_INTERFACE_FORMAT */ 00088 #define AD77681_INTERFACE_CRC_EN_MSK (0x1 << 6) 00089 #define AD77681_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6) 00090 #define AD77681_INTERFACE_CRC_TYPE_MSK (0x1 << 5) 00091 #define AD77681_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5) 00092 #define AD77681_INTERFACE_STATUS_EN_MSK (0x1 << 4) 00093 #define AD77681_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4) 00094 #define AD77681_INTERFACE_CONVLEN_MSK (0x1 << 3) 00095 #define AD77681_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3) 00096 #define AD77681_INTERFACE_RDY_EN_MSK (0x1 << 2) 00097 #define AD77681_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3) 00098 #define AD77681_INTERFACE_CONT_READ_MSK (0x1 << 0) 00099 #define AD77681_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0) 00100 #define AD77681_REG_COEFF_CONTROL 0x32 00101 #define AD77681_REG_COEFF_DATA 0x33 00102 #define AD77681_REG_ACCESS_KEY 0x34 00103 00104 /* AD77681_REG_SCRATCH_PAD*/ 00105 #define AD77681_SCRATCHPAD_MSK (0xFF << 0) 00106 #define AD77681_SCRATCHPAD(x) (((x) & 0xFF) << 0) 00107 00108 /* AD77681_REG_POWER_CLOCK */ 00109 #define AD77681_POWER_CLK_PWRMODE_MSK 0x3 00110 #define AD77681_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0) 00111 #define AD77681_POWER_CLK_MOD_OUT_MSK (0x1 << 2) 00112 #define AD77681_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2) 00113 #define AD77681_POWER_CLK_POWER_DOWN 0x08 00114 #define AD77681_POWER_CLK_MCLK_DIV_MSK (0x3 << 4) 00115 #define AD77681_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4) 00116 #define AD77681_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6) 00117 #define AD77681_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6) 00118 00119 /* AD77681_CONVERSION_REG */ 00120 #define AD77681_CONVERSION_DIAG_MUX_MSK (0xF << 4) 00121 #define AD77681_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4) 00122 #define AD77681_CONVERSION_DIAG_SEL_MSK (0x1 << 3) 00123 #define AD77681_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3) 00124 #define AD77681_CONVERSION_MODE_MSK (0x7 << 0) 00125 #define AD77681_CONVERSION_MODE(x) (((x) & 0x7) << 0) 00126 00127 /* AD77681_REG_ANALOG */ 00128 #define AD77681_ANALOG_REF_BUF_POS_MSK (0x3 << 6) 00129 #define AD77681_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6) 00130 #define AD77681_ANALOG_REF_BUF_NEG_MSK (0x3 << 4) 00131 #define AD77681_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4) 00132 #define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1) 00133 #define AD77681_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1) 00134 #define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0) 00135 #define AD77681_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0) 00136 00137 /* AD77681_REG_ANALOG2 */ 00138 #define AD77681_ANALOG2_VCM_MSK (0x7 << 0) 00139 #define AD77681_ANALOG2_VCM(x) (((x) & 0x7) << 0) 00140 00141 /* AD77681_REG_DIGITAL_FILTER */ 00142 #define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7) 00143 #define AD77681_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7) 00144 #define AD77681_DIGI_FILTER_FILTER_MSK (0x7 << 4) 00145 #define AD77681_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4) 00146 #define AD77681_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0) 00147 #define AD77681_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0) 00148 00149 /* AD77681_REG_SINC3_DEC_RATE_MSB */ 00150 #define AD77681_SINC3_DEC_RATE_MSB_MSK (0x0F << 0) 00151 #define AD77681_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0) 00152 00153 /* AD77681_REG_SINC3_DEC_RATE_LSB */ 00154 #define AD77681_SINC3_DEC_RATE_LSB_MSK (0xFF << 0) 00155 #define AD77681_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0) 00156 00157 /* AD77681_REG_DUTY_CYCLE_RATIO */ 00158 #define AD77681_DC_RATIO_IDLE_TIME_MSK (0xFF << 0) 00159 #define AD77681_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0) 00160 00161 /* AD77681_REG_SYNC_RESET */ 00162 #define AD77681_SYNC_RST_SPI_STARTB_MSK (0x1 << 7) 00163 #define AD77681_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7) 00164 #define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6) 00165 #define AD77681_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6) 00166 #define AD77681_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3) 00167 #define AD77681_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3) 00168 #define AD77681_SYNC_RST_SPI_RESET_MSK (0x3 << 0) 00169 #define AD77681_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0) 00170 00171 /* AD77681_REG_GPIO_CONTROL */ 00172 #define AD77681_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7) 00173 #define AD77681_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7) 00174 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6) 00175 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6) 00176 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5) 00177 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5) 00178 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4) 00179 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4) 00180 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4) 00181 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4) 00182 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3) 00183 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3) 00184 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2) 00185 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2) 00186 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1) 00187 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1) 00188 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0) 00189 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0) 00190 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0) 00191 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0) 00192 00193 /* AD77681_REG_GPIO_WRITE */ 00194 #define AD77681_GPIO_WRITE_3_MSK (0x1 << 3) 00195 #define AD77681_GPIO_WRITE_3(x) (((x) & 0x1) << 3) 00196 #define AD77681_GPIO_WRITE_2_MSK (0x1 << 2) 00197 #define AD77681_GPIO_WRITE_2(x) (((x) & 0x1) << 2) 00198 #define AD77681_GPIO_WRITE_1_MSK (0x1 << 1) 00199 #define AD77681_GPIO_WRITE_1(x) (((x) & 0x1) << 1) 00200 #define AD77681_GPIO_WRITE_0_MSK (0x1 << 0) 00201 #define AD77681_GPIO_WRITE_0(x) (((x) & 0x1) << 0) 00202 #define AD77681_GPIO_WRITE_ALL_MSK (0xF << 0) 00203 #define AD77681_GPIO_WRITE_ALL(x) (((x) & 0xF)) 00204 00205 /* AD77681_REG_GPIO_READ */ 00206 #define AD77681_GPIO_READ_3_MSK (0x1 << 3) 00207 #define AD77681_GPIO_READ_2_MSK (0x1 << 2) 00208 #define AD77681_GPIO_READ_1_MSK (0x1 << 1) 00209 #define AD77681_GPIO_READ_0_MSK (0x1 << 0) 00210 #define AD77681_GPIO_READ_ALL_MSK (0xF << 0) 00211 00212 /* AD77681_REG_OFFSET_HI */ 00213 #define AD77681_OFFSET_HI_MSK (0xFF << 0) 00214 #define AD77681_OFFSET_HI(x) (((x) & 0xFF) << 0) 00215 00216 /* AD77681_REG_OFFSET_MID */ 00217 #define AD77681_OFFSET_MID_MSK (0xFF << 0) 00218 #define AD77681_OFFSET_MID(x) (((x) & 0xFF) << 0) 00219 00220 /* AD77681_REG_OFFSET_LO */ 00221 #define AD77681_OFFSET_LO_MSK (0xFF << 0) 00222 #define AD77681_OFFSET_LO(x) (((x) & 0xFF) << 0) 00223 00224 /* AD77681_REG_GAIN_HI */ 00225 #define AD77681_GAIN_HI_MSK (0xFF << 0) 00226 #define AD77681_GAIN_HI(x) (((x) & 0xFF) << 0) 00227 00228 /* AD77681_REG_GAIN_MID */ 00229 #define AD77681_GAIN_MID_MSK (0xFF << 0) 00230 #define AD77681_GAIN_MID(x) (((x) & 0xFF) << 0) 00231 00232 /* AD77681_REG_GAIN_HI */ 00233 #define AD77681_GAIN_LOW_MSK (0xFF << 0) 00234 #define AD77681_GAIN_LOW(x) (((x) & 0xFF) << 0) 00235 00236 /* AD77681_REG_SPI_DIAG_ENABLE */ 00237 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4) 00238 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4) 00239 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3) 00240 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3) 00241 #define AD77681_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2) 00242 #define AD77681_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2) 00243 #define AD77681_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1) 00244 #define AD77681_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1) 00245 00246 /* AD77681_REG_ADC_DIAG_ENABLE */ 00247 #define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5) 00248 #define AD77681_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5) 00249 #define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4) 00250 #define AD77681_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4) 00251 #define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2) 00252 #define AD77681_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2) 00253 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1) 00254 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1) 00255 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0) 00256 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0) 00257 00258 /* AD77681_REG_DIG_DIAG_ENABLE */ 00259 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4) 00260 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4) 00261 #define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3) 00262 #define AD77681_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3) 00263 #define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2) 00264 #define AD77681_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2) 00265 #define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0) 00266 #define AD77681_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0) 00267 00268 /* AD77681_REG_MASTER_STATUS */ 00269 #define AD77681_MASTER_ERROR_MSK (0x1 << 7) 00270 #define AD77681_MASTER_ADC_ERROR_MSK (0x1 << 6) 00271 #define AD77681_MASTER_DIG_ERROR_MSK (0x1 << 5) 00272 #define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4) 00273 #define AD77681_MASTER_FILT_SAT_MSK (0x1 << 3) 00274 #define AD77681_MASTER_FILT_NOT_SET_MSK (0x1 << 2) 00275 #define AD77681_MASTER_SPI_ERROR_MSK (0x1 << 1) 00276 #define AD77681_MASTER_POR_FLAG_MSK (0x1 << 0) 00277 00278 /* AD77681_REG_SPI_DIAG_STATUS */ 00279 #define AD77681_SPI_IGNORE_ERROR_MSK (0x1 << 4) 00280 #define AD77681_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4) 00281 #define AD77681_SPI_CLK_CNT_ERROR_MSK (0x1 << 3) 00282 #define AD77681_SPI_READ_ERROR_MSK (0x1 << 2) 00283 #define AD77681_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2) 00284 #define AD77681_SPI_WRITE_ERROR_MSK (0x1 << 1) 00285 #define AD77681_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1) 00286 #define AD77681_SPI_CRC_ERROR_MSK (0x1 << 0) 00287 #define AD77681_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0) 00288 00289 /* AD77681_REG_ADC_DIAG_STATUS */ 00290 #define AD77681_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5) 00291 #define AD77681_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4) 00292 #define AD77681_ADC_REF_DET_ERROR_MSK (0x1 << 3) 00293 #define AD77681_ADC_FILT_SAT_MSK (0x1 << 2) 00294 #define AD77681_ADC_FILT_NOT_SET_MSK (0x1 << 1) 00295 #define AD77681_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0) 00296 00297 /* AD77681_REG_DIG_DIAG_STATUS */ 00298 #define AD77681_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4) 00299 #define AD77681_DIG_RAM_CRC_ERROR_MSK (0x1 << 3) 00300 #define AD77681_DIG_FUS_CRC_ERROR_MSK (0x1 << 2) 00301 00302 /* AD77681_REG_MCLK_COUNTER */ 00303 #define AD77681_MCLK_COUNTER_MSK (0xFF << 0) 00304 #define AD77681_MCLK_COUNTER(x) (((x) & 0xFF) << 0) 00305 00306 /* AD77681_REG_COEFF_CONTROL */ 00307 #define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7) 00308 #define AD77681_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7) 00309 #define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6) 00310 #define AD77681_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6) 00311 #define AD77681_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5) 00312 #define AD77681_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5) 00313 00314 /* AD77681_REG_COEFF_DATA */ 00315 #define AD77681_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23) 00316 #define AD77681_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23) 00317 #define AD77681_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22) 00318 #define AD77681_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22) 00319 00320 /* AD77681_REG_ACCESS_KEY */ 00321 #define AD77681_ACCESS_KEY_MSK (0xFF << 0) 00322 #define AD77681_ACCESS_KEY(x) (((x) & 0xFF) << 0) 00323 #define AD77681_ACCESS_KEY_CHECK_MSK (0x1 << 0) 00324 00325 #define AD77681_REG_READ(x) ( (1 << 6) | (x & 0xFF) ) // Read from register x 00326 #define AD77681_REG_WRITE(x) ( (~(1 << 6)) & (x & 0xFF) ) // Write to register x 00327 00328 /* 8-bits wide checksum generated using the polynomial */ 00329 #define AD77681_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0 00330 00331 /* Initial CRC for continuous read mode */ 00332 #define INITIAL_CRC_CRC8 0x03 00333 #define INITIAL_CRC_XOR 0x6C 00334 #define INITIAL_CRC 0x00 00335 00336 #define CRC_DEBUG 00337 00338 /* AD7768-1 */ 00339 /* A special key for exit the contiuous read mode, taken from the AD7768-1 datasheet */ 00340 #define EXIT_CONT_READ 0x6C 00341 /* Bit resolution of the AD7768-1 */ 00342 #define AD7768_N_BITS 24 00343 /* Full scale of the AD7768-1 = 2^24 = 16777216 */ 00344 #define AD7768_FULL_SCALE (1 << AD7768_N_BITS) 00345 /* Half scale of the AD7768-1 = 2^23 = 8388608 */ 00346 #define AD7768_HALF_SCALE (1 << (AD7768_N_BITS - 1)) 00347 00348 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 00349 00350 #define ENABLE 1 00351 #define DISABLE 0 00352 00353 /*****************************************************************************/ 00354 /*************************** Types Declarations *******************************/ 00355 /******************************************************************************/ 00356 enum ad77681_power_mode { 00357 AD77681_ECO = 0, 00358 AD77681_MEDIAN = 2, 00359 AD77681_FAST = 3, 00360 }; 00361 00362 enum ad77681_mclk_div { 00363 AD77681_MCLK_DIV_16 = 0, 00364 AD77681_MCLK_DIV_8 = 1, 00365 AD77681_MCLK_DIV_4 = 2, 00366 AD77681_MCLK_DIV_2 = 3 00367 }; 00368 00369 enum ad77681_conv_mode { 00370 AD77681_CONV_CONTINUOUS = 0, 00371 AD77681_CONV_ONE_SHOT = 1, 00372 AD77681_CONV_SINGLE = 2, 00373 AD77681_CONV_PERIODIC = 3, 00374 AD77681_CONV_STANDBY = 4 00375 }; 00376 00377 enum ad77681_conv_len { 00378 AD77681_CONV_24BIT = 0, 00379 AD77681_CONV_16BIT = 1 00380 }; 00381 00382 enum ad77681_rdy_dout { 00383 AD77681_RDY_DOUT_EN, 00384 AD77681_RDY_DOUT_DIS 00385 }; 00386 00387 enum ad77681_conv_diag_mux { 00388 AD77681_TEMP_SENSOR = 0x0, 00389 AD77681_AIN_SHORT= 0x8, 00390 AD77681_POSITIVE_FS = 0x9, 00391 AD77681_NEGATIVE_FS = 0xA 00392 }; 00393 00394 enum ad77681_crc_sel { 00395 AD77681_CRC, 00396 AD77681_XOR, 00397 AD77681_NO_CRC 00398 }; 00399 00400 /* Filter tye FIR, SINC3, SINC5 */ 00401 enum ad77681_filter_type { 00402 AD77681_SINC5 = 0, 00403 AD77681_SINC5_DECx8 = 1, 00404 AD77681_SINC5_DECx16 = 2, 00405 AD77681_SINC3 = 3, 00406 AD77681_FIR = 4 00407 }; 00408 00409 /* Dectimation ratios for SINC5 and FIR */ 00410 enum ad77681_sinc5_fir_decimate { 00411 AD77681_SINC5_FIR_DECx32 = 0, 00412 AD77681_SINC5_FIR_DECx64 = 1, 00413 AD77681_SINC5_FIR_DECx128 = 2, 00414 AD77681_SINC5_FIR_DECx256 = 3, 00415 AD77681_SINC5_FIR_DECx512 = 4, 00416 AD77681_SINC5_FIR_DECx1024 = 5 00417 }; 00418 00419 /* Sleep / Power up */ 00420 enum ad77681_sleep_wake { 00421 AD77681_SLEEP = 1, 00422 AD77681_WAKE = 0 00423 }; 00424 00425 /* Reset option */ 00426 enum ad7761_reset_option { 00427 AD77681_SOFT_RESET, 00428 AD77681_HARD_RESET 00429 }; 00430 /* AIN- precharge */ 00431 enum ad77681_AINn_precharge { 00432 AD77681_AINn_ENABLED = 0, 00433 AD77681_AINn_DISABLED = 1 00434 }; 00435 00436 /* AIN+ precharge */ 00437 enum ad77681_AINp_precharge { 00438 AD77681_AINp_ENABLED = 0, 00439 AD77681_AINp_DISABLED = 1 00440 }; 00441 00442 /* REF- buffer */ 00443 enum ad77681_REFn_buffer { 00444 AD77681_BUFn_ENABLED = 0, 00445 AD77681_BUFn_DISABLED = 1, 00446 AD77681_BUFn_FULL_BUFFER_ON = 2 00447 }; 00448 00449 /* REF+ buffer */ 00450 enum ad77681_REFp_buffer { 00451 AD77681_BUFp_ENABLED = 0, 00452 AD77681_BUFp_DISABLED = 1, 00453 AD77681_BUFp_FULL_BUFFER_ON = 2 00454 }; 00455 00456 /* VCM output voltage */ 00457 enum ad77681_VCM_out { 00458 AD77681_VCM_HALF_VCC = 0, 00459 AD77681_VCM_2_5V = 1, 00460 AD77681_VCM_2_05V = 2, 00461 AD77681_VCM_1_9V = 3, 00462 AD77681_VCM_1_65V = 4, 00463 AD77681_VCM_1_1V = 5, 00464 AD77681_VCM_0_9V = 6, 00465 AD77681_VCM_OFF = 7 00466 }; 00467 00468 /* Global GPIO enable/disable */ 00469 enum ad77681_gobal_gpio_enable { 00470 AD77681_GLOBAL_GPIO_ENABLE = 1, 00471 AD77681_GLOBAL_GPIO_DISABLE = 0 00472 }; 00473 00474 /* ADCs GPIO numbering */ 00475 enum ad77681_gpios { 00476 AD77681_GPIO0 = 0, 00477 AD77681_GPIO1 = 1, 00478 AD77681_GPIO2 = 2, 00479 AD77681_GPIO3 = 3, 00480 AD77681_ALL_GPIOS = 4 00481 }; 00482 00483 enum ad77681_gpio_output_type { 00484 AD77681_GPIO_STRONG_DRIVER = 0, 00485 AD77681_GPIO_OPEN_DRAIN = 1 00486 }; 00487 00488 /* Continuous ADC read */ 00489 enum ad77681_continuous_read { 00490 AD77681_CONTINUOUS_READ_ENABLE = 1, 00491 AD77681_CONTINUOUS_READ_DISABLE = 0, 00492 }; 00493 00494 /* ADC data read mode */ 00495 enum ad77681_data_read_mode { 00496 AD77681_REGISTER_DATA_READ = 0, 00497 AD77681_CONTINUOUS_DATA_READ = 1, 00498 }; 00499 00500 /* ADC data structure */ 00501 struct adc_data { 00502 bool finish; 00503 uint16_t count; 00504 uint16_t samples; 00505 uint32_t raw_data[4096]; 00506 }; 00507 /* ADC status registers structure */ 00508 struct ad77681_status_registers { 00509 bool master_error; 00510 bool adc_error; 00511 bool dig_error; 00512 bool adc_err_ext_clk_qual; 00513 bool adc_filt_saturated; 00514 bool adc_filt_not_settled; 00515 bool spi_error; 00516 bool por_flag; 00517 bool spi_ignore; 00518 bool spi_clock_count; 00519 bool spi_read_error; 00520 bool spi_write_error; 00521 bool spi_crc_error; 00522 bool dldo_psm_error; 00523 bool aldo_psm_error; 00524 bool ref_det_error; 00525 bool filt_sat_error; 00526 bool filt_not_set_error; 00527 bool ext_clk_qual_error; 00528 bool memoy_map_crc_error; 00529 bool ram_crc_error; 00530 bool fuse_crc_error; 00531 }; 00532 00533 struct ad77681_dev { 00534 /* SPI */ 00535 spi_desc *spi_desc; 00536 /* Configuration */ 00537 enum ad77681_power_mode power_mode; 00538 enum ad77681_mclk_div mclk_div; 00539 enum ad77681_conv_mode conv_mode; 00540 enum ad77681_conv_diag_mux diag_mux_sel; 00541 bool conv_diag_sel; 00542 enum ad77681_conv_len conv_len; 00543 enum ad77681_crc_sel crc_sel; 00544 uint8_t status_bit; 00545 enum ad77681_VCM_out VCM_out; 00546 enum ad77681_AINn_precharge AINn; 00547 enum ad77681_AINp_precharge AINp; 00548 enum ad77681_REFn_buffer REFn; 00549 enum ad77681_REFp_buffer REFp; 00550 enum ad77681_filter_type filter; 00551 enum ad77681_sinc5_fir_decimate decimate; 00552 uint16_t sinc3_osr; 00553 uint16_t vref; /* Reference voltage*/ 00554 uint16_t mclk; /* Mater clock*/ 00555 uint32_t sample_rate; /* Sample rate*/ 00556 uint8_t data_frame_byte; /* SPI 8bit frames*/ 00557 }; 00558 00559 struct ad77681_init_param { 00560 /* SPI */ 00561 spi_init_param spi_eng_dev_init; 00562 /* Configuration */ 00563 enum ad77681_power_mode power_mode; 00564 enum ad77681_mclk_div mclk_div; 00565 enum ad77681_conv_mode conv_mode; 00566 enum ad77681_conv_diag_mux diag_mux_sel; 00567 bool conv_diag_sel; 00568 enum ad77681_conv_len conv_len; 00569 enum ad77681_crc_sel crc_sel; 00570 uint8_t status_bit; 00571 enum ad77681_VCM_out VCM_out; 00572 enum ad77681_AINn_precharge AINn; 00573 enum ad77681_AINp_precharge AINp; 00574 enum ad77681_REFn_buffer REFn; 00575 enum ad77681_REFp_buffer REFp; 00576 enum ad77681_filter_type filter; 00577 enum ad77681_sinc5_fir_decimate decimate; 00578 uint16_t sinc3_osr; 00579 uint16_t vref; 00580 uint16_t mclk; 00581 uint32_t sample_rate; 00582 uint8_t data_frame_byte; 00583 }; 00584 00585 /******************************************************************************/ 00586 /************************ Functions Declarations ******************************/ 00587 /******************************************************************************/ 00588 uint8_t ad77681_compute_crc8(uint8_t *data, 00589 uint8_t data_size, 00590 uint8_t init_val); 00591 uint8_t ad77681_compute_xor(uint8_t *data, 00592 uint8_t data_size, 00593 uint8_t init_val); 00594 int32_t ad77681_setup(struct ad77681_dev **device, 00595 struct ad77681_init_param init_param, 00596 struct ad77681_status_registers **status); 00597 int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, 00598 uint8_t reg_addr, 00599 uint8_t *reg_data); 00600 int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, 00601 uint8_t reg_addr, 00602 uint8_t mask, 00603 uint8_t *data); 00604 int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, 00605 uint8_t reg_addr, 00606 uint8_t reg_data); 00607 int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, 00608 uint8_t reg_addr, 00609 uint8_t mask, 00610 uint8_t data); 00611 int32_t ad77681_set_power_mode(struct ad77681_dev *dev, 00612 enum ad77681_power_mode mode); 00613 int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, 00614 enum ad77681_mclk_div clk_div); 00615 int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, 00616 uint8_t *adc_data, 00617 enum ad77681_data_read_mode mode); 00618 int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, 00619 enum ad77681_conv_mode conv_mode, 00620 enum ad77681_conv_diag_mux diag_mux_sel, 00621 bool conv_diag_sel); 00622 int32_t ad77681_set_convlen(struct ad77681_dev *dev, 00623 enum ad77681_conv_len conv_len); 00624 int32_t ad77681_soft_reset(struct ad77681_dev *dev); 00625 int32_t ad77681_initiate_sync(struct ad77681_dev *dev); 00626 int32_t ad77681_programmable_filter(struct ad77681_dev *dev, 00627 const float *coeffs, 00628 uint8_t num_coeffs); 00629 int32_t ad77681_gpio_read(struct ad77681_dev *dev, 00630 uint8_t *value, 00631 enum ad77681_gpios gpio_number); 00632 int32_t ad77681_apply_offset(struct ad77681_dev *dev, 00633 uint32_t value); 00634 int32_t ad77681_apply_gain(struct ad77681_dev *dev, 00635 uint32_t value); 00636 int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, 00637 enum ad77681_crc_sel crc_sel); 00638 int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, 00639 enum ad77681_gpios gpio_number, 00640 enum ad77681_gpio_output_type output_type); 00641 int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, 00642 enum ad77681_continuous_read continuous_enable); 00643 int32_t ad77681_clear_error_flags(struct ad77681_dev *dev); 00644 int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, 00645 uint32_t *raw_code, 00646 double *voltage); 00647 int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, 00648 uint16_t *data_buffer); 00649 int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, 00650 enum ad77681_AINn_precharge AINn); 00651 int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, 00652 enum ad77681_AINp_precharge AINp); 00653 int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, 00654 enum ad77681_REFn_buffer REFn); 00655 int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, 00656 enum ad77681_REFp_buffer REFp); 00657 int32_t ad77681_set_filter_type(struct ad77681_dev *dev, 00658 enum ad77681_sinc5_fir_decimate decimate, 00659 enum ad77681_filter_type filter, 00660 uint16_t sinc3_osr); 00661 int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, 00662 uint8_t enable); 00663 int32_t ad77681_power_down(struct ad77681_dev *dev, 00664 enum ad77681_sleep_wake sleep_wake); 00665 int32_t ad77681_set_status_bit(struct ad77681_dev *dev, 00666 bool status_bit); 00667 int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, 00668 enum ad77681_VCM_out VCM_out); 00669 int32_t ad77681_gpio_write(struct ad77681_dev *dev, 00670 uint8_t value, 00671 enum ad77681_gpios gpio_number); 00672 int32_t ad77681_gpio_inout(struct ad77681_dev *dev, 00673 uint8_t direction, 00674 enum ad77681_gpios gpio_number); 00675 int32_t ad77681_global_gpio(struct ad77681_dev *devices, 00676 enum ad77681_gobal_gpio_enable gpio_enable); 00677 int32_t ad77681_scratchpad(struct ad77681_dev *dev, 00678 uint8_t *sequence); 00679 int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev); 00680 int32_t ad77681_update_sample_rate(struct ad77681_dev *dev); 00681 int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, 00682 uint16_t *sinc3_dec_reg, 00683 float sinc3_odr); 00684 int32_t ad77681_status(struct ad77681_dev *dev, 00685 struct ad77681_status_registers *status); 00686 #endif /* SRC_AD77681_H_ */
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