Analog Devices / Mbed OS EVAL-AD7768-1

Program files for Example program for EVAL-AD7768-1

Dependencies:   platform_drivers

app/ad77681.c@1:260e834a8dc1, 2021-09-24 (annotated)

Committer:
Kjansen
Date:
Fri Sep 24 15:14:06 2021 +0100
Revision:
1:260e834a8dc1
Adding released source code of ad7768-1

Deleting the redefinition of data_capture_ops

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kjansen 1:260e834a8dc1 1 /***************************************************************************//**
Kjansen 1:260e834a8dc1 2 * @file ad77681.c
Kjansen 1:260e834a8dc1 3 * @brief Implementation of AD7768-1 Driver.
Kjansen 1:260e834a8dc1 4 * @author SPopa (stefan.popa@analog.com)
Kjansen 1:260e834a8dc1 5 ********************************************************************************
Kjansen 1:260e834a8dc1 6 * Copyright 2017(c) Analog Devices, Inc.
Kjansen 1:260e834a8dc1 7 *
Kjansen 1:260e834a8dc1 8 * All rights reserved.
Kjansen 1:260e834a8dc1 9 *
Kjansen 1:260e834a8dc1 10 * Redistribution and use in source and binary forms, with or without
Kjansen 1:260e834a8dc1 11 * modification, are permitted provided that the following conditions are met:
Kjansen 1:260e834a8dc1 12 * - Redistributions of source code must retain the above copyright
Kjansen 1:260e834a8dc1 13 * notice, this list of conditions and the following disclaimer.
Kjansen 1:260e834a8dc1 14 * - Redistributions in binary form must reproduce the above copyright
Kjansen 1:260e834a8dc1 15 * notice, this list of conditions and the following disclaimer in
Kjansen 1:260e834a8dc1 16 * the documentation and/or other materials provided with the
Kjansen 1:260e834a8dc1 17 * distribution.
Kjansen 1:260e834a8dc1 18 * - Neither the name of Analog Devices, Inc. nor the names of its
Kjansen 1:260e834a8dc1 19 * contributors may be used to endorse or promote products derived
Kjansen 1:260e834a8dc1 20 * from this software without specific prior written permission.
Kjansen 1:260e834a8dc1 21 * - The use of this software may or may not infringe the patent rights
Kjansen 1:260e834a8dc1 22 * of one or more patent holders. This license does not release you
Kjansen 1:260e834a8dc1 23 * from the requirement that you obtain separate licenses from these
Kjansen 1:260e834a8dc1 24 * patent holders to use this software.
Kjansen 1:260e834a8dc1 25 * - Use of the software either in source or binary form, must be run
Kjansen 1:260e834a8dc1 26 * on or directly connected to an Analog Devices Inc. component.
Kjansen 1:260e834a8dc1 27 *
Kjansen 1:260e834a8dc1 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
Kjansen 1:260e834a8dc1 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
Kjansen 1:260e834a8dc1 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
Kjansen 1:260e834a8dc1 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
Kjansen 1:260e834a8dc1 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
Kjansen 1:260e834a8dc1 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
Kjansen 1:260e834a8dc1 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kjansen 1:260e834a8dc1 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kjansen 1:260e834a8dc1 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kjansen 1:260e834a8dc1 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kjansen 1:260e834a8dc1 38 *******************************************************************************/
Kjansen 1:260e834a8dc1 39
Kjansen 1:260e834a8dc1 40 /******************************************************************************/
Kjansen 1:260e834a8dc1 41 /***************************** Include Files **********************************/
Kjansen 1:260e834a8dc1 42 /******************************************************************************/
Kjansen 1:260e834a8dc1 43 #include "stdio.h"
Kjansen 1:260e834a8dc1 44 #include "stdlib.h"
Kjansen 1:260e834a8dc1 45 #include "stdbool.h"
Kjansen 1:260e834a8dc1 46 #include <string.h>
Kjansen 1:260e834a8dc1 47 #include "ad77681.h"
Kjansen 1:260e834a8dc1 48 #include "error.h"
Kjansen 1:260e834a8dc1 49 #include "delay.h"
Kjansen 1:260e834a8dc1 50
Kjansen 1:260e834a8dc1 51 /******************************************************************************/
Kjansen 1:260e834a8dc1 52 /************************** Functions Implementation **************************/
Kjansen 1:260e834a8dc1 53 /******************************************************************************/
Kjansen 1:260e834a8dc1 54 /**
Kjansen 1:260e834a8dc1 55 * Compute CRC8 checksum.
Kjansen 1:260e834a8dc1 56 * @param data - The data buffer.
Kjansen 1:260e834a8dc1 57 * @param data_size - The size of the data buffer.
Kjansen 1:260e834a8dc1 58 * @param init_val - CRC initial value.
Kjansen 1:260e834a8dc1 59 * @return CRC8 checksum.
Kjansen 1:260e834a8dc1 60 */
Kjansen 1:260e834a8dc1 61 uint8_t ad77681_compute_crc8(uint8_t *data,
Kjansen 1:260e834a8dc1 62 uint8_t data_size,
Kjansen 1:260e834a8dc1 63 uint8_t init_val)
Kjansen 1:260e834a8dc1 64 {
Kjansen 1:260e834a8dc1 65 uint8_t i;
Kjansen 1:260e834a8dc1 66 uint8_t crc = init_val;
Kjansen 1:260e834a8dc1 67
Kjansen 1:260e834a8dc1 68 while (data_size) {
Kjansen 1:260e834a8dc1 69 for (i = 0x80; i != 0; i >>= 1) {
Kjansen 1:260e834a8dc1 70 if (((crc & 0x80) != 0) != ((*data & i) != 0)) {
Kjansen 1:260e834a8dc1 71 crc <<= 1;
Kjansen 1:260e834a8dc1 72 crc ^= AD77681_CRC8_POLY;
Kjansen 1:260e834a8dc1 73 } else
Kjansen 1:260e834a8dc1 74 crc <<= 1;
Kjansen 1:260e834a8dc1 75 }
Kjansen 1:260e834a8dc1 76 data++;
Kjansen 1:260e834a8dc1 77 data_size--;
Kjansen 1:260e834a8dc1 78 }
Kjansen 1:260e834a8dc1 79 return crc;
Kjansen 1:260e834a8dc1 80 }
Kjansen 1:260e834a8dc1 81
Kjansen 1:260e834a8dc1 82 /**
Kjansen 1:260e834a8dc1 83 * Compute XOR checksum.
Kjansen 1:260e834a8dc1 84 * @param data - The data buffer.
Kjansen 1:260e834a8dc1 85 * @param data_size - The size of the data buffer.
Kjansen 1:260e834a8dc1 86 * @param init_val - CRC initial value.
Kjansen 1:260e834a8dc1 87 * @return XOR checksum.
Kjansen 1:260e834a8dc1 88 */
Kjansen 1:260e834a8dc1 89 uint8_t ad77681_compute_xor(uint8_t *data,
Kjansen 1:260e834a8dc1 90 uint8_t data_size,
Kjansen 1:260e834a8dc1 91 uint8_t init_val)
Kjansen 1:260e834a8dc1 92 {
Kjansen 1:260e834a8dc1 93 uint8_t crc = init_val;
Kjansen 1:260e834a8dc1 94 uint8_t buf[3];
Kjansen 1:260e834a8dc1 95 uint8_t i;
Kjansen 1:260e834a8dc1 96
Kjansen 1:260e834a8dc1 97 for (i = 0; i < data_size; i++) {
Kjansen 1:260e834a8dc1 98 buf[i] = *data;
Kjansen 1:260e834a8dc1 99 crc ^= buf[i];
Kjansen 1:260e834a8dc1 100 data++;
Kjansen 1:260e834a8dc1 101 }
Kjansen 1:260e834a8dc1 102 return crc;
Kjansen 1:260e834a8dc1 103 }
Kjansen 1:260e834a8dc1 104
Kjansen 1:260e834a8dc1 105 /**
Kjansen 1:260e834a8dc1 106 * Read from device.
Kjansen 1:260e834a8dc1 107 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 108 * @param reg_addr - The register address.
Kjansen 1:260e834a8dc1 109 * @param reg_data - The register data.
Kjansen 1:260e834a8dc1 110 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 111 */
Kjansen 1:260e834a8dc1 112 int32_t ad77681_spi_reg_read(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 113 uint8_t reg_addr,
Kjansen 1:260e834a8dc1 114 uint8_t *reg_data)
Kjansen 1:260e834a8dc1 115 {
Kjansen 1:260e834a8dc1 116 int32_t ret;
Kjansen 1:260e834a8dc1 117 uint8_t crc;
Kjansen 1:260e834a8dc1 118 uint8_t buf[3], crc_buf[2];
Kjansen 1:260e834a8dc1 119 uint8_t buf_len = (dev->crc_sel == AD77681_NO_CRC) ? 2 : 3;
Kjansen 1:260e834a8dc1 120
Kjansen 1:260e834a8dc1 121 buf[0] = AD77681_REG_READ(reg_addr);
Kjansen 1:260e834a8dc1 122 buf[1] = 0x00;
Kjansen 1:260e834a8dc1 123
Kjansen 1:260e834a8dc1 124 ret = spi_write_and_read(dev->spi_desc, buf, buf_len);
Kjansen 1:260e834a8dc1 125 if (ret < 0)
Kjansen 1:260e834a8dc1 126 return ret;
Kjansen 1:260e834a8dc1 127
Kjansen 1:260e834a8dc1 128 /* XOR or CRC checksum for read transactions */
Kjansen 1:260e834a8dc1 129 if (dev->crc_sel != AD77681_NO_CRC) {
Kjansen 1:260e834a8dc1 130 crc_buf[0] = AD77681_REG_READ(reg_addr);
Kjansen 1:260e834a8dc1 131 crc_buf[1] = buf[1];
Kjansen 1:260e834a8dc1 132
Kjansen 1:260e834a8dc1 133 if (dev->crc_sel == AD77681_XOR)
Kjansen 1:260e834a8dc1 134 /* INITIAL_CRC is 0, when ADC is not in continuous-read mode */
Kjansen 1:260e834a8dc1 135 crc = ad77681_compute_xor(crc_buf, 2, INITIAL_CRC);
Kjansen 1:260e834a8dc1 136 else if(dev->crc_sel == AD77681_CRC)
Kjansen 1:260e834a8dc1 137 /* INITIAL_CRC is 0, when ADC is not in continuous-read mode */
Kjansen 1:260e834a8dc1 138 crc = ad77681_compute_crc8(crc_buf, 2, INITIAL_CRC);
Kjansen 1:260e834a8dc1 139
Kjansen 1:260e834a8dc1 140 /* In buf[2] is CRC from the ADC */
Kjansen 1:260e834a8dc1 141 if (crc != buf[2])
Kjansen 1:260e834a8dc1 142 ret = FAILURE;
Kjansen 1:260e834a8dc1 143 #ifdef CRC_DEBUG
Kjansen 1:260e834a8dc1 144 printf("\n%x\t%x\tCRC/XOR: %s\n", crc,
Kjansen 1:260e834a8dc1 145 buf[2], ((crc != buf[2]) ? "FAULT" : "OK"));
Kjansen 1:260e834a8dc1 146 #endif /* CRC_DEBUG */
Kjansen 1:260e834a8dc1 147 }
Kjansen 1:260e834a8dc1 148
Kjansen 1:260e834a8dc1 149 reg_data[0] = AD77681_REG_READ(reg_addr);
Kjansen 1:260e834a8dc1 150 memcpy(reg_data + 1, buf + 1, ARRAY_SIZE(buf) - 1);
Kjansen 1:260e834a8dc1 151
Kjansen 1:260e834a8dc1 152 return ret;
Kjansen 1:260e834a8dc1 153 }
Kjansen 1:260e834a8dc1 154
Kjansen 1:260e834a8dc1 155 /**
Kjansen 1:260e834a8dc1 156 * Write to device.
Kjansen 1:260e834a8dc1 157 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 158 * @param reg_addr - The register address.
Kjansen 1:260e834a8dc1 159 * @param reg_data - The register data.
Kjansen 1:260e834a8dc1 160 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 161 */
Kjansen 1:260e834a8dc1 162 int32_t ad77681_spi_reg_write(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 163 uint8_t reg_addr,
Kjansen 1:260e834a8dc1 164 uint8_t reg_data)
Kjansen 1:260e834a8dc1 165 {
Kjansen 1:260e834a8dc1 166 uint8_t buf[3];
Kjansen 1:260e834a8dc1 167 /* Buffer length in case of checksum usage */
Kjansen 1:260e834a8dc1 168 uint8_t buf_len = (dev->crc_sel == AD77681_NO_CRC) ? 2 : 3;
Kjansen 1:260e834a8dc1 169
Kjansen 1:260e834a8dc1 170 buf[0] = AD77681_REG_WRITE(reg_addr);
Kjansen 1:260e834a8dc1 171 buf[1] = reg_data;
Kjansen 1:260e834a8dc1 172
Kjansen 1:260e834a8dc1 173 /* CRC only for read transactions, CRC and XOR for write transactions*/
Kjansen 1:260e834a8dc1 174 if (dev->crc_sel != AD77681_NO_CRC)
Kjansen 1:260e834a8dc1 175 buf[2] = ad77681_compute_crc8(buf, 2, INITIAL_CRC);
Kjansen 1:260e834a8dc1 176
Kjansen 1:260e834a8dc1 177 return spi_write_and_read(dev->spi_desc, buf, buf_len);
Kjansen 1:260e834a8dc1 178 }
Kjansen 1:260e834a8dc1 179
Kjansen 1:260e834a8dc1 180 /**
Kjansen 1:260e834a8dc1 181 * SPI read from device using a mask.
Kjansen 1:260e834a8dc1 182 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 183 * @param reg_addr - The register address.
Kjansen 1:260e834a8dc1 184 * @param mask - The mask.
Kjansen 1:260e834a8dc1 185 * @param data - The register data.
Kjansen 1:260e834a8dc1 186 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 187 */
Kjansen 1:260e834a8dc1 188 int32_t ad77681_spi_read_mask(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 189 uint8_t reg_addr,
Kjansen 1:260e834a8dc1 190 uint8_t mask,
Kjansen 1:260e834a8dc1 191 uint8_t *data)
Kjansen 1:260e834a8dc1 192 {
Kjansen 1:260e834a8dc1 193 uint8_t reg_data[3];
Kjansen 1:260e834a8dc1 194 int32_t ret;
Kjansen 1:260e834a8dc1 195
Kjansen 1:260e834a8dc1 196 ret = ad77681_spi_reg_read(dev, reg_addr, reg_data);
Kjansen 1:260e834a8dc1 197 *data = (reg_data[1] & mask);
Kjansen 1:260e834a8dc1 198
Kjansen 1:260e834a8dc1 199 return ret;
Kjansen 1:260e834a8dc1 200 }
Kjansen 1:260e834a8dc1 201
Kjansen 1:260e834a8dc1 202 /**
Kjansen 1:260e834a8dc1 203 * SPI write to device using a mask.
Kjansen 1:260e834a8dc1 204 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 205 * @param reg_addr - The register address.
Kjansen 1:260e834a8dc1 206 * @param mask - The mask.
Kjansen 1:260e834a8dc1 207 * @param data - The register data.
Kjansen 1:260e834a8dc1 208 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 209 */
Kjansen 1:260e834a8dc1 210 int32_t ad77681_spi_write_mask(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 211 uint8_t reg_addr,
Kjansen 1:260e834a8dc1 212 uint8_t mask,
Kjansen 1:260e834a8dc1 213 uint8_t data)
Kjansen 1:260e834a8dc1 214 {
Kjansen 1:260e834a8dc1 215 uint8_t reg_data[3];
Kjansen 1:260e834a8dc1 216 int32_t ret;
Kjansen 1:260e834a8dc1 217
Kjansen 1:260e834a8dc1 218 ret = ad77681_spi_reg_read(dev, reg_addr, reg_data);
Kjansen 1:260e834a8dc1 219 reg_data[1] &= ~mask;
Kjansen 1:260e834a8dc1 220 reg_data[1] |= data;
Kjansen 1:260e834a8dc1 221 ret |= ad77681_spi_reg_write(dev, reg_addr, reg_data[1]);
Kjansen 1:260e834a8dc1 222
Kjansen 1:260e834a8dc1 223 return ret;
Kjansen 1:260e834a8dc1 224 }
Kjansen 1:260e834a8dc1 225
Kjansen 1:260e834a8dc1 226 /**
Kjansen 1:260e834a8dc1 227 * Helper function to get the number of rx bytes
Kjansen 1:260e834a8dc1 228 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 229 * @return rx_buf_len - the number of rx bytes
Kjansen 1:260e834a8dc1 230 */
Kjansen 1:260e834a8dc1 231 uint8_t ad77681_get_rx_buf_len(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 232 {
Kjansen 1:260e834a8dc1 233 uint8_t rx_buf_len = 0;
Kjansen 1:260e834a8dc1 234 uint8_t data_len = 0;
Kjansen 1:260e834a8dc1 235 uint8_t crc = 0;
Kjansen 1:260e834a8dc1 236 uint8_t status_bit = 0;
Kjansen 1:260e834a8dc1 237
Kjansen 1:260e834a8dc1 238 data_len = 3;
Kjansen 1:260e834a8dc1 239 crc = (dev->crc_sel == AD77681_NO_CRC) ? 0 : 1; // 1 byte for crc
Kjansen 1:260e834a8dc1 240 status_bit = dev->status_bit; // one byte for status
Kjansen 1:260e834a8dc1 241
Kjansen 1:260e834a8dc1 242 rx_buf_len = data_len + crc + status_bit;
Kjansen 1:260e834a8dc1 243
Kjansen 1:260e834a8dc1 244 return rx_buf_len;
Kjansen 1:260e834a8dc1 245 }
Kjansen 1:260e834a8dc1 246
Kjansen 1:260e834a8dc1 247 /**
Kjansen 1:260e834a8dc1 248 * Helper function to get the number of SPI 16bit frames for INTERRUPT ADC DATA READ
Kjansen 1:260e834a8dc1 249 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 250 * @return frame_16bit - the number of 16 bit SPI frames
Kjansen 1:260e834a8dc1 251 */
Kjansen 1:260e834a8dc1 252 uint8_t ad77681_get_frame_byte(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 253 {
Kjansen 1:260e834a8dc1 254 /* number of 8bit frames */
Kjansen 1:260e834a8dc1 255 uint8_t frame_bytes;
Kjansen 1:260e834a8dc1 256 if (dev->conv_len == AD77681_CONV_24BIT)
Kjansen 1:260e834a8dc1 257 frame_bytes = 3;
Kjansen 1:260e834a8dc1 258 else
Kjansen 1:260e834a8dc1 259 frame_bytes = 2;
Kjansen 1:260e834a8dc1 260 if (dev->crc_sel != AD77681_NO_CRC)
Kjansen 1:260e834a8dc1 261 frame_bytes++;
Kjansen 1:260e834a8dc1 262 if (dev->status_bit)
Kjansen 1:260e834a8dc1 263 frame_bytes++;
Kjansen 1:260e834a8dc1 264
Kjansen 1:260e834a8dc1 265 dev->data_frame_byte = frame_bytes;
Kjansen 1:260e834a8dc1 266
Kjansen 1:260e834a8dc1 267 return frame_bytes;
Kjansen 1:260e834a8dc1 268 }
Kjansen 1:260e834a8dc1 269
Kjansen 1:260e834a8dc1 270 /**
Kjansen 1:260e834a8dc1 271 * Read conversion result from device.
Kjansen 1:260e834a8dc1 272 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 273 * @param adc_data - The conversion result data
Kjansen 1:260e834a8dc1 274 * @param mode - Data read mode
Kjansen 1:260e834a8dc1 275 * Accepted values: AD77681_REGISTER_DATA_READ
Kjansen 1:260e834a8dc1 276 * AD77681_CONTINUOUS_DATA_READ
Kjansen 1:260e834a8dc1 277 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 278 */
Kjansen 1:260e834a8dc1 279 int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 280 uint8_t *adc_data,
Kjansen 1:260e834a8dc1 281 enum ad77681_data_read_mode mode)
Kjansen 1:260e834a8dc1 282 {
Kjansen 1:260e834a8dc1 283 uint8_t buf[6], crc_xor, add_buff;
Kjansen 1:260e834a8dc1 284 int32_t ret;
Kjansen 1:260e834a8dc1 285
Kjansen 1:260e834a8dc1 286 if (mode == AD77681_REGISTER_DATA_READ) {
Kjansen 1:260e834a8dc1 287 buf[0] = AD77681_REG_READ(AD77681_REG_ADC_DATA);
Kjansen 1:260e834a8dc1 288 add_buff = 1;
Kjansen 1:260e834a8dc1 289 } else {
Kjansen 1:260e834a8dc1 290 buf[0] = 0x00;
Kjansen 1:260e834a8dc1 291 add_buff = 0;
Kjansen 1:260e834a8dc1 292 }
Kjansen 1:260e834a8dc1 293 buf[1] = 0x00; /* added 2 more array places for max data length read */
Kjansen 1:260e834a8dc1 294 buf[2] = 0x00; /* For register data read */
Kjansen 1:260e834a8dc1 295 buf[3] = 0x00; /* register address + 3 bytes of data (24bit format) + Status bit + CRC */
Kjansen 1:260e834a8dc1 296 buf[4] = 0x00; /* For continuous data read */
Kjansen 1:260e834a8dc1 297 buf[5] = 0x00; /* 3 bytes of data (24bit format) + Status bit + CRC */
Kjansen 1:260e834a8dc1 298
Kjansen 1:260e834a8dc1 299
Kjansen 1:260e834a8dc1 300 ret = spi_write_and_read(dev->spi_desc, buf, dev->data_frame_byte + add_buff);
Kjansen 1:260e834a8dc1 301 if (ret < 0)
Kjansen 1:260e834a8dc1 302 return ret;
Kjansen 1:260e834a8dc1 303
Kjansen 1:260e834a8dc1 304 if (dev->crc_sel != AD77681_NO_CRC) {
Kjansen 1:260e834a8dc1 305 if (dev->crc_sel == AD77681_CRC)
Kjansen 1:260e834a8dc1 306 crc_xor = ad77681_compute_crc8(buf + add_buff, dev->data_frame_byte - 1,
Kjansen 1:260e834a8dc1 307 INITIAL_CRC_CRC8);
Kjansen 1:260e834a8dc1 308 else
Kjansen 1:260e834a8dc1 309 crc_xor = ad77681_compute_xor(buf + add_buff, dev->data_frame_byte - 1,
Kjansen 1:260e834a8dc1 310 INITIAL_CRC_XOR);
Kjansen 1:260e834a8dc1 311
Kjansen 1:260e834a8dc1 312 if (crc_xor != buf[dev->data_frame_byte - (1 - add_buff)]) {
Kjansen 1:260e834a8dc1 313 printf("%s: CRC Error.\n", __func__);
Kjansen 1:260e834a8dc1 314 ret = FAILURE;
Kjansen 1:260e834a8dc1 315 }
Kjansen 1:260e834a8dc1 316 #ifdef CRC_DEBUG
Kjansen 1:260e834a8dc1 317 printf("\n%x\t%x\tCRC/XOR: %s\n", crc_xor,
Kjansen 1:260e834a8dc1 318 buf[dev->data_frame_byte - (1 - add_buff)],
Kjansen 1:260e834a8dc1 319 ((crc_xor != buf[dev->data_frame_byte - (1 - add_buff)]) ? "FAULT" : "OK"));
Kjansen 1:260e834a8dc1 320 #endif /* CRC_DEBUG */
Kjansen 1:260e834a8dc1 321 }
Kjansen 1:260e834a8dc1 322
Kjansen 1:260e834a8dc1 323 /* Fill the adc_data buffer */
Kjansen 1:260e834a8dc1 324 memcpy(adc_data, buf, ARRAY_SIZE(buf));
Kjansen 1:260e834a8dc1 325
Kjansen 1:260e834a8dc1 326 return ret;
Kjansen 1:260e834a8dc1 327 }
Kjansen 1:260e834a8dc1 328
Kjansen 1:260e834a8dc1 329 /**
Kjansen 1:260e834a8dc1 330 * CRC and status bit handling after each readout form the ADC
Kjansen 1:260e834a8dc1 331 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 332 * @param *data_buffer - 16-bit buffer readed from the ADC containing the CRC,
Kjansen 1:260e834a8dc1 333 * data and the stattus bit.
Kjansen 1:260e834a8dc1 334 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 335 */
Kjansen 1:260e834a8dc1 336 int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 337 uint16_t *data_buffer)
Kjansen 1:260e834a8dc1 338 {
Kjansen 1:260e834a8dc1 339 int32_t ret = 0;
Kjansen 1:260e834a8dc1 340 uint8_t status_byte = 0, checksum = 0, checksum_byte = 0, checksum_buf[5],
Kjansen 1:260e834a8dc1 341 checksum_length = 0, i;
Kjansen 1:260e834a8dc1 342 char print_buf[50];
Kjansen 1:260e834a8dc1 343
Kjansen 1:260e834a8dc1 344 /* Status bit handling */
Kjansen 1:260e834a8dc1 345 if (dev->status_bit) {
Kjansen 1:260e834a8dc1 346 /* 24bit ADC data + 8bit of status = 2 16bit frames */
Kjansen 1:260e834a8dc1 347 if (dev->conv_len == AD77681_CONV_24BIT)
Kjansen 1:260e834a8dc1 348 status_byte = data_buffer[1] & 0xFF;
Kjansen 1:260e834a8dc1 349 /* 16bit ADC data + 8bit of status = 2 16bit frames */
Kjansen 1:260e834a8dc1 350 else
Kjansen 1:260e834a8dc1 351 status_byte = data_buffer[1] >> 8;
Kjansen 1:260e834a8dc1 352 }
Kjansen 1:260e834a8dc1 353
Kjansen 1:260e834a8dc1 354 /* Checksum bit handling */
Kjansen 1:260e834a8dc1 355 if (dev->crc_sel != AD77681_NO_CRC) {
Kjansen 1:260e834a8dc1 356 if ((dev->status_bit == true) & (dev->conv_len == AD77681_CONV_24BIT)) {
Kjansen 1:260e834a8dc1 357 /* 24bit ADC data + 8bit of status + 8bit of CRC = 3 16bit frames */
Kjansen 1:260e834a8dc1 358 checksum_byte = data_buffer[2] >> 8;
Kjansen 1:260e834a8dc1 359 checksum_length = 4;
Kjansen 1:260e834a8dc1 360 } else if ((dev->status_bit == true) & (dev->conv_len == AD77681_CONV_16BIT)) {
Kjansen 1:260e834a8dc1 361 /* 16bit ADC data + 8bit of status + 8bit of CRC = 2 16bit frames */
Kjansen 1:260e834a8dc1 362 checksum_byte = data_buffer[1] & 0xFF;
Kjansen 1:260e834a8dc1 363 checksum_length = 3;
Kjansen 1:260e834a8dc1 364 } else if ((dev->status_bit == false) & (dev->conv_len == AD77681_CONV_24BIT)) {
Kjansen 1:260e834a8dc1 365 /* 24bit ADC data + 8bit of CRC = 2 16bit frames */
Kjansen 1:260e834a8dc1 366 checksum_byte = data_buffer[1] & 0xFF;
Kjansen 1:260e834a8dc1 367 checksum_length = 3;
Kjansen 1:260e834a8dc1 368 } else if ((dev->status_bit == false) & (dev->conv_len == AD77681_CONV_16BIT)) {
Kjansen 1:260e834a8dc1 369 /* 16bit ADC data + 8bit of CRC = 2 16bit frames */
Kjansen 1:260e834a8dc1 370 checksum_byte = data_buffer[1] >> 8;
Kjansen 1:260e834a8dc1 371 checksum_length = 2;
Kjansen 1:260e834a8dc1 372 }
Kjansen 1:260e834a8dc1 373
Kjansen 1:260e834a8dc1 374 for (i = 0; i < checksum_length; i++) {
Kjansen 1:260e834a8dc1 375 if (i % 2)
Kjansen 1:260e834a8dc1 376 checksum_buf[i] = data_buffer[i / 2] & 0xFF;
Kjansen 1:260e834a8dc1 377 else
Kjansen 1:260e834a8dc1 378 checksum_buf[i] = data_buffer[i / 2] >> 8;
Kjansen 1:260e834a8dc1 379 }
Kjansen 1:260e834a8dc1 380
Kjansen 1:260e834a8dc1 381 if (dev->crc_sel == AD77681_CRC)
Kjansen 1:260e834a8dc1 382 checksum = ad77681_compute_crc8(checksum_buf, checksum_length,
Kjansen 1:260e834a8dc1 383 INITIAL_CRC_CRC8);
Kjansen 1:260e834a8dc1 384 else if (dev->crc_sel == AD77681_XOR)
Kjansen 1:260e834a8dc1 385 checksum = ad77681_compute_xor(checksum_buf, checksum_length, INITIAL_CRC_XOR);
Kjansen 1:260e834a8dc1 386
Kjansen 1:260e834a8dc1 387 if (checksum != checksum_byte)
Kjansen 1:260e834a8dc1 388 ret = FAILURE;
Kjansen 1:260e834a8dc1 389
Kjansen 1:260e834a8dc1 390 #ifdef CRC_DEBUG
Kjansen 1:260e834a8dc1 391
Kjansen 1:260e834a8dc1 392 char ok[3] = { 'O', 'K' }, fault[6] = { 'F', 'A', 'U', 'L', 'T' };
Kjansen 1:260e834a8dc1 393 sprintf(print_buf, "\n%x\t%x\t%x\tCRC %s", checksum_byte, checksum, status_byte,
Kjansen 1:260e834a8dc1 394 ((ret == FAILURE) ? (fault) : (ok)));
Kjansen 1:260e834a8dc1 395 printf(print_buf);
Kjansen 1:260e834a8dc1 396
Kjansen 1:260e834a8dc1 397 #endif /* CRC_DEBUG */
Kjansen 1:260e834a8dc1 398 }
Kjansen 1:260e834a8dc1 399
Kjansen 1:260e834a8dc1 400 return ret;
Kjansen 1:260e834a8dc1 401 }
Kjansen 1:260e834a8dc1 402
Kjansen 1:260e834a8dc1 403 /**
Kjansen 1:260e834a8dc1 404 * Conversion from measured data to voltage
Kjansen 1:260e834a8dc1 405 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 406 * @param raw_code - ADC raw code measurements
Kjansen 1:260e834a8dc1 407 * @param voltage - Converted ADC code to voltage
Kjansen 1:260e834a8dc1 408 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 409 */
Kjansen 1:260e834a8dc1 410 int32_t ad77681_data_to_voltage(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 411 uint32_t *raw_code,
Kjansen 1:260e834a8dc1 412 double *voltage)
Kjansen 1:260e834a8dc1 413 {
Kjansen 1:260e834a8dc1 414 int32_t converted_data;
Kjansen 1:260e834a8dc1 415
Kjansen 1:260e834a8dc1 416 if (*raw_code & 0x800000)
Kjansen 1:260e834a8dc1 417 converted_data = (int32_t)((0xFF << 24) | *raw_code);
Kjansen 1:260e834a8dc1 418 else
Kjansen 1:260e834a8dc1 419 converted_data = (int32_t)((0x00 << 24) | *raw_code);
Kjansen 1:260e834a8dc1 420
Kjansen 1:260e834a8dc1 421 /* ((2*Vref)*code)/2^24 */
Kjansen 1:260e834a8dc1 422 *voltage = (double)(((2.0 * (((double)(dev->vref)) / 1000.0)) /
Kjansen 1:260e834a8dc1 423 AD7768_FULL_SCALE) * converted_data);
Kjansen 1:260e834a8dc1 424
Kjansen 1:260e834a8dc1 425 return SUCCESS;
Kjansen 1:260e834a8dc1 426 }
Kjansen 1:260e834a8dc1 427
Kjansen 1:260e834a8dc1 428 /**
Kjansen 1:260e834a8dc1 429 * Update ADCs sample rate depending on MCLK, MCLK_DIV and filter settings
Kjansen 1:260e834a8dc1 430 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 431 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 432 */
Kjansen 1:260e834a8dc1 433 int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 434 {
Kjansen 1:260e834a8dc1 435 uint8_t mclk_div;
Kjansen 1:260e834a8dc1 436 uint16_t osr;
Kjansen 1:260e834a8dc1 437
Kjansen 1:260e834a8dc1 438 /* Finding out MCLK divider */
Kjansen 1:260e834a8dc1 439 switch (dev->mclk_div) {
Kjansen 1:260e834a8dc1 440 case AD77681_MCLK_DIV_16:
Kjansen 1:260e834a8dc1 441 mclk_div = 16;
Kjansen 1:260e834a8dc1 442 break;
Kjansen 1:260e834a8dc1 443 case AD77681_MCLK_DIV_8:
Kjansen 1:260e834a8dc1 444 mclk_div = 8;
Kjansen 1:260e834a8dc1 445 break;
Kjansen 1:260e834a8dc1 446 case AD77681_MCLK_DIV_4:
Kjansen 1:260e834a8dc1 447 mclk_div = 4;
Kjansen 1:260e834a8dc1 448 break;
Kjansen 1:260e834a8dc1 449 case AD77681_MCLK_DIV_2:
Kjansen 1:260e834a8dc1 450 mclk_div = 2;
Kjansen 1:260e834a8dc1 451 break;
Kjansen 1:260e834a8dc1 452 default:
Kjansen 1:260e834a8dc1 453 return FAILURE;
Kjansen 1:260e834a8dc1 454 break;
Kjansen 1:260e834a8dc1 455 }
Kjansen 1:260e834a8dc1 456
Kjansen 1:260e834a8dc1 457 /* Finding out decimation ratio */
Kjansen 1:260e834a8dc1 458 switch (dev->filter) {
Kjansen 1:260e834a8dc1 459 case (AD77681_SINC5 | AD77681_FIR):
Kjansen 1:260e834a8dc1 460 /* Decimation ratio of FIR or SINC5 (x32 to x1024) */
Kjansen 1:260e834a8dc1 461 switch (dev->decimate) {
Kjansen 1:260e834a8dc1 462 case AD77681_SINC5_FIR_DECx32:
Kjansen 1:260e834a8dc1 463 osr = 32;
Kjansen 1:260e834a8dc1 464 break;
Kjansen 1:260e834a8dc1 465 case AD77681_SINC5_FIR_DECx64:
Kjansen 1:260e834a8dc1 466 osr = 64;
Kjansen 1:260e834a8dc1 467 break;
Kjansen 1:260e834a8dc1 468 case AD77681_SINC5_FIR_DECx128:
Kjansen 1:260e834a8dc1 469 osr = 128;
Kjansen 1:260e834a8dc1 470 break;
Kjansen 1:260e834a8dc1 471 case AD77681_SINC5_FIR_DECx256:
Kjansen 1:260e834a8dc1 472 osr = 256;
Kjansen 1:260e834a8dc1 473 break;
Kjansen 1:260e834a8dc1 474 case AD77681_SINC5_FIR_DECx512:
Kjansen 1:260e834a8dc1 475 osr = 512;
Kjansen 1:260e834a8dc1 476 break;
Kjansen 1:260e834a8dc1 477 case AD77681_SINC5_FIR_DECx1024:
Kjansen 1:260e834a8dc1 478 osr = 1024;
Kjansen 1:260e834a8dc1 479 break;
Kjansen 1:260e834a8dc1 480 default:
Kjansen 1:260e834a8dc1 481 return FAILURE;
Kjansen 1:260e834a8dc1 482 break;
Kjansen 1:260e834a8dc1 483 }
Kjansen 1:260e834a8dc1 484 break;
Kjansen 1:260e834a8dc1 485 /* Decimation ratio of SINC5 x8 */
Kjansen 1:260e834a8dc1 486 case AD77681_SINC5_DECx8:
Kjansen 1:260e834a8dc1 487 osr = 8;
Kjansen 1:260e834a8dc1 488 break;
Kjansen 1:260e834a8dc1 489 /* Decimation ratio of SINC5 x16 */
Kjansen 1:260e834a8dc1 490 case AD77681_SINC5_DECx16:
Kjansen 1:260e834a8dc1 491 osr = 16;
Kjansen 1:260e834a8dc1 492 break;
Kjansen 1:260e834a8dc1 493 /* Decimation ratio of SINC3 */
Kjansen 1:260e834a8dc1 494 case AD77681_SINC3:
Kjansen 1:260e834a8dc1 495 osr = (dev->sinc3_osr + 1) * 32;
Kjansen 1:260e834a8dc1 496 break;
Kjansen 1:260e834a8dc1 497 default:
Kjansen 1:260e834a8dc1 498 return FAILURE;
Kjansen 1:260e834a8dc1 499 break;
Kjansen 1:260e834a8dc1 500 }
Kjansen 1:260e834a8dc1 501
Kjansen 1:260e834a8dc1 502 /* Sample rate to Hz */
Kjansen 1:260e834a8dc1 503 dev->sample_rate = (dev->mclk / (osr*mclk_div)) * 1000;
Kjansen 1:260e834a8dc1 504
Kjansen 1:260e834a8dc1 505 return SUCCESS;
Kjansen 1:260e834a8dc1 506 }
Kjansen 1:260e834a8dc1 507
Kjansen 1:260e834a8dc1 508 /**
Kjansen 1:260e834a8dc1 509 * Get SINC3 filter oversampling ratio register value based on user's inserted
Kjansen 1:260e834a8dc1 510 * output data rate ODR
Kjansen 1:260e834a8dc1 511 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 512 * @param sinc3_dec_reg - Returned closest value of SINC3 register
Kjansen 1:260e834a8dc1 513 * @param sinc3_odr - Desired output data rage
Kjansen 1:260e834a8dc1 514 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 515 */
Kjansen 1:260e834a8dc1 516 int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 517 uint16_t *sinc3_dec_reg,
Kjansen 1:260e834a8dc1 518 float sinc3_odr)
Kjansen 1:260e834a8dc1 519 {
Kjansen 1:260e834a8dc1 520 uint8_t mclk_div;
Kjansen 1:260e834a8dc1 521 float odr;
Kjansen 1:260e834a8dc1 522
Kjansen 1:260e834a8dc1 523 if (sinc3_odr < 0)
Kjansen 1:260e834a8dc1 524 return FAILURE;
Kjansen 1:260e834a8dc1 525
Kjansen 1:260e834a8dc1 526 switch (dev->mclk_div) {
Kjansen 1:260e834a8dc1 527 case AD77681_MCLK_DIV_16:
Kjansen 1:260e834a8dc1 528 mclk_div = 16;
Kjansen 1:260e834a8dc1 529 break;
Kjansen 1:260e834a8dc1 530 case AD77681_MCLK_DIV_8:
Kjansen 1:260e834a8dc1 531 mclk_div = 8;
Kjansen 1:260e834a8dc1 532 break;
Kjansen 1:260e834a8dc1 533 case AD77681_MCLK_DIV_4:
Kjansen 1:260e834a8dc1 534 mclk_div = 4;
Kjansen 1:260e834a8dc1 535 break;
Kjansen 1:260e834a8dc1 536 case AD77681_MCLK_DIV_2:
Kjansen 1:260e834a8dc1 537 mclk_div = 2;
Kjansen 1:260e834a8dc1 538 break;
Kjansen 1:260e834a8dc1 539 default:
Kjansen 1:260e834a8dc1 540 return FAILURE;
Kjansen 1:260e834a8dc1 541 break;
Kjansen 1:260e834a8dc1 542 }
Kjansen 1:260e834a8dc1 543
Kjansen 1:260e834a8dc1 544 odr = ((float)(dev->mclk * 1000.0) / (sinc3_odr * (float)(32 * mclk_div))) - 1;
Kjansen 1:260e834a8dc1 545
Kjansen 1:260e834a8dc1 546 /* Sinc3 oversamplig register has 13 bits, biggest value = 8192 */
Kjansen 1:260e834a8dc1 547 if (odr < 8193)
Kjansen 1:260e834a8dc1 548 *sinc3_dec_reg = (uint16_t)(odr);
Kjansen 1:260e834a8dc1 549 else
Kjansen 1:260e834a8dc1 550 return FAILURE;
Kjansen 1:260e834a8dc1 551
Kjansen 1:260e834a8dc1 552 return SUCCESS;
Kjansen 1:260e834a8dc1 553 }
Kjansen 1:260e834a8dc1 554
Kjansen 1:260e834a8dc1 555 /**
Kjansen 1:260e834a8dc1 556 * Set the power consumption mode of the ADC core.
Kjansen 1:260e834a8dc1 557 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 558 * @param mode - The power mode.
Kjansen 1:260e834a8dc1 559 * Accepted values: AD77681_ECO
Kjansen 1:260e834a8dc1 560 * AD77681_MEDIAN
Kjansen 1:260e834a8dc1 561 * AD77681_FAST
Kjansen 1:260e834a8dc1 562 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 563 */
Kjansen 1:260e834a8dc1 564 int32_t ad77681_set_power_mode(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 565 enum ad77681_power_mode mode)
Kjansen 1:260e834a8dc1 566 {
Kjansen 1:260e834a8dc1 567 int32_t ret;
Kjansen 1:260e834a8dc1 568
Kjansen 1:260e834a8dc1 569 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 570 AD77681_REG_POWER_CLOCK,
Kjansen 1:260e834a8dc1 571 AD77681_POWER_CLK_PWRMODE_MSK,
Kjansen 1:260e834a8dc1 572 AD77681_POWER_CLK_PWRMODE(mode));
Kjansen 1:260e834a8dc1 573
Kjansen 1:260e834a8dc1 574 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 575 dev->power_mode = mode;
Kjansen 1:260e834a8dc1 576
Kjansen 1:260e834a8dc1 577 return ret;
Kjansen 1:260e834a8dc1 578 }
Kjansen 1:260e834a8dc1 579
Kjansen 1:260e834a8dc1 580 /**
Kjansen 1:260e834a8dc1 581 * Set the MCLK divider.
Kjansen 1:260e834a8dc1 582 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 583 * @param clk_div - The MCLK divider.
Kjansen 1:260e834a8dc1 584 * Accepted values: AD77681_MCLK_DIV_16
Kjansen 1:260e834a8dc1 585 * AD77681_MCLK_DIV_8
Kjansen 1:260e834a8dc1 586 * AD77681_MCLK_DIV_4
Kjansen 1:260e834a8dc1 587 * AD77681_MCLK_DIV_2
Kjansen 1:260e834a8dc1 588 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 589 */
Kjansen 1:260e834a8dc1 590 int32_t ad77681_set_mclk_div(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 591 enum ad77681_mclk_div clk_div)
Kjansen 1:260e834a8dc1 592 {
Kjansen 1:260e834a8dc1 593 int32_t ret;
Kjansen 1:260e834a8dc1 594
Kjansen 1:260e834a8dc1 595 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 596 AD77681_REG_POWER_CLOCK,
Kjansen 1:260e834a8dc1 597 AD77681_POWER_CLK_MCLK_DIV_MSK,
Kjansen 1:260e834a8dc1 598 AD77681_POWER_CLK_MCLK_DIV(clk_div));
Kjansen 1:260e834a8dc1 599
Kjansen 1:260e834a8dc1 600 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 601 dev->mclk_div = clk_div;
Kjansen 1:260e834a8dc1 602
Kjansen 1:260e834a8dc1 603 return ret;
Kjansen 1:260e834a8dc1 604 }
Kjansen 1:260e834a8dc1 605
Kjansen 1:260e834a8dc1 606 /**
Kjansen 1:260e834a8dc1 607 * Set the VCM output.
Kjansen 1:260e834a8dc1 608 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 609 * @param VCM_out - The VCM output voltage.
Kjansen 1:260e834a8dc1 610 * Accepted values: AD77681_VCM_HALF_VCC
Kjansen 1:260e834a8dc1 611 * AD77681_VCM_2_5V
Kjansen 1:260e834a8dc1 612 * AD77681_VCM_2_05V
Kjansen 1:260e834a8dc1 613 * AD77681_VCM_1_9V
Kjansen 1:260e834a8dc1 614 * AD77681_VCM_1_65V
Kjansen 1:260e834a8dc1 615 * AD77681_VCM_1_1V
Kjansen 1:260e834a8dc1 616 * AD77681_VCM_0_9V
Kjansen 1:260e834a8dc1 617 * AD77681_VCM_OFF
Kjansen 1:260e834a8dc1 618 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 619 */
Kjansen 1:260e834a8dc1 620 int32_t ad77681_set_VCM_output(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 621 enum ad77681_VCM_out VCM_out)
Kjansen 1:260e834a8dc1 622 {
Kjansen 1:260e834a8dc1 623 int32_t ret;
Kjansen 1:260e834a8dc1 624
Kjansen 1:260e834a8dc1 625 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 626 AD77681_REG_ANALOG2,
Kjansen 1:260e834a8dc1 627 AD77681_ANALOG2_VCM_MSK,
Kjansen 1:260e834a8dc1 628 AD77681_ANALOG2_VCM(VCM_out));
Kjansen 1:260e834a8dc1 629
Kjansen 1:260e834a8dc1 630 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 631 dev->VCM_out = VCM_out;
Kjansen 1:260e834a8dc1 632
Kjansen 1:260e834a8dc1 633 return ret;
Kjansen 1:260e834a8dc1 634 }
Kjansen 1:260e834a8dc1 635
Kjansen 1:260e834a8dc1 636 /**
Kjansen 1:260e834a8dc1 637 * Set the AIN- precharge buffer.
Kjansen 1:260e834a8dc1 638 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 639 * @param AINn - The negative analog input precharge buffer selector
Kjansen 1:260e834a8dc1 640 * Accepted values: AD77681_AINn_ENABLED
Kjansen 1:260e834a8dc1 641 * AD77681_AINn_DISABLED
Kjansen 1:260e834a8dc1 642 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 643 */
Kjansen 1:260e834a8dc1 644 int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 645 enum ad77681_AINn_precharge AINn)
Kjansen 1:260e834a8dc1 646 {
Kjansen 1:260e834a8dc1 647 int32_t ret;
Kjansen 1:260e834a8dc1 648
Kjansen 1:260e834a8dc1 649 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 650 AD77681_REG_ANALOG,
Kjansen 1:260e834a8dc1 651 AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK,
Kjansen 1:260e834a8dc1 652 AD77681_ANALOG_AIN_BUF_NEG_OFF(AINn));
Kjansen 1:260e834a8dc1 653
Kjansen 1:260e834a8dc1 654 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 655 dev->AINn = AINn;
Kjansen 1:260e834a8dc1 656
Kjansen 1:260e834a8dc1 657 return ret;
Kjansen 1:260e834a8dc1 658 }
Kjansen 1:260e834a8dc1 659
Kjansen 1:260e834a8dc1 660 /**
Kjansen 1:260e834a8dc1 661 * Set the AIN+ precharge buffer.
Kjansen 1:260e834a8dc1 662 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 663 * @param AINp - The positive analog input precharge buffer selector
Kjansen 1:260e834a8dc1 664 * Accepted values: AD77681_AINp_ENABLED
Kjansen 1:260e834a8dc1 665 * AD77681_AINp_DISABLED
Kjansen 1:260e834a8dc1 666 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 667 */
Kjansen 1:260e834a8dc1 668 int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 669 enum ad77681_AINp_precharge AINp)
Kjansen 1:260e834a8dc1 670 {
Kjansen 1:260e834a8dc1 671 int32_t ret;
Kjansen 1:260e834a8dc1 672
Kjansen 1:260e834a8dc1 673 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 674 AD77681_REG_ANALOG,
Kjansen 1:260e834a8dc1 675 AD77681_ANALOG_AIN_BUF_POS_OFF_MSK,
Kjansen 1:260e834a8dc1 676 AD77681_ANALOG_AIN_BUF_POS_OFF(AINp));
Kjansen 1:260e834a8dc1 677
Kjansen 1:260e834a8dc1 678 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 679 dev->AINp = AINp;
Kjansen 1:260e834a8dc1 680
Kjansen 1:260e834a8dc1 681 return ret;
Kjansen 1:260e834a8dc1 682 }
Kjansen 1:260e834a8dc1 683
Kjansen 1:260e834a8dc1 684 /**
Kjansen 1:260e834a8dc1 685 * Set the REF- reference buffer
Kjansen 1:260e834a8dc1 686 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 687 * @param REFn - The negative reference buffer selector
Kjansen 1:260e834a8dc1 688 * Accepted values: AD77681_BUFn_DISABLED
Kjansen 1:260e834a8dc1 689 * AD77681_BUFn_ENABLED
Kjansen 1:260e834a8dc1 690 * AD77681_BUFn_FULL_BUFFER_ON
Kjansen 1:260e834a8dc1 691 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 692 */
Kjansen 1:260e834a8dc1 693 int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 694 enum ad77681_REFn_buffer REFn)
Kjansen 1:260e834a8dc1 695 {
Kjansen 1:260e834a8dc1 696 int32_t ret;
Kjansen 1:260e834a8dc1 697
Kjansen 1:260e834a8dc1 698 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 699 AD77681_REG_ANALOG,
Kjansen 1:260e834a8dc1 700 AD77681_ANALOG_REF_BUF_NEG_MSK,
Kjansen 1:260e834a8dc1 701 AD77681_ANALOG_REF_BUF_NEG(REFn));
Kjansen 1:260e834a8dc1 702
Kjansen 1:260e834a8dc1 703 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 704 dev->REFn = REFn;
Kjansen 1:260e834a8dc1 705
Kjansen 1:260e834a8dc1 706 return ret;
Kjansen 1:260e834a8dc1 707 }
Kjansen 1:260e834a8dc1 708
Kjansen 1:260e834a8dc1 709 /**
Kjansen 1:260e834a8dc1 710 * Set the REF+ reference buffer
Kjansen 1:260e834a8dc1 711 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 712 * @param REFp - The positive reference buffer selector
Kjansen 1:260e834a8dc1 713 * Accepted values: AD77681_BUFp_DISABLED
Kjansen 1:260e834a8dc1 714 * AD77681_BUFp_ENABLED
Kjansen 1:260e834a8dc1 715 * AD77681_BUFp_FULL_BUFFER_ON
Kjansen 1:260e834a8dc1 716 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 717 */
Kjansen 1:260e834a8dc1 718 int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 719 enum ad77681_REFp_buffer REFp)
Kjansen 1:260e834a8dc1 720 {
Kjansen 1:260e834a8dc1 721 int32_t ret;
Kjansen 1:260e834a8dc1 722
Kjansen 1:260e834a8dc1 723 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 724 AD77681_REG_ANALOG,
Kjansen 1:260e834a8dc1 725 AD77681_ANALOG_REF_BUF_POS_MSK,
Kjansen 1:260e834a8dc1 726 AD77681_ANALOG_REF_BUF_POS(REFp));
Kjansen 1:260e834a8dc1 727
Kjansen 1:260e834a8dc1 728 if (ret == SUCCESS)
Kjansen 1:260e834a8dc1 729 dev->REFp = REFp;
Kjansen 1:260e834a8dc1 730 else
Kjansen 1:260e834a8dc1 731 return FAILURE;
Kjansen 1:260e834a8dc1 732
Kjansen 1:260e834a8dc1 733 return ret;
Kjansen 1:260e834a8dc1 734 }
Kjansen 1:260e834a8dc1 735
Kjansen 1:260e834a8dc1 736 /**
Kjansen 1:260e834a8dc1 737 * Set filter type and decimation ratio
Kjansen 1:260e834a8dc1 738 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 739 * @param decimate - Decimation ratio of filter
Kjansen 1:260e834a8dc1 740 * Accepted values: AD77681_SINC5_FIR_DECx32
Kjansen 1:260e834a8dc1 741 * AD77681_SINC5_FIR_DECx64
Kjansen 1:260e834a8dc1 742 * AD77681_SINC5_FIR_DECx128
Kjansen 1:260e834a8dc1 743 * AD77681_SINC5_FIR_DECx256
Kjansen 1:260e834a8dc1 744 * AD77681_SINC5_FIR_DECx512
Kjansen 1:260e834a8dc1 745 * AD77681_SINC5_FIR_DECx1024
Kjansen 1:260e834a8dc1 746 * @param filter - Select filter type
Kjansen 1:260e834a8dc1 747 * Accepted values: AD77681_SINC5
Kjansen 1:260e834a8dc1 748 * AD77681_SINC5_DECx8
Kjansen 1:260e834a8dc1 749 * AD77681_SINC5_DECx16
Kjansen 1:260e834a8dc1 750 * AD77681_SINC3
Kjansen 1:260e834a8dc1 751 * AD77681_FIR
Kjansen 1:260e834a8dc1 752 * @param sinc3_osr - Select decimation ratio for SINC3 filter separately as
Kjansen 1:260e834a8dc1 753 * integer from 0 to 8192.
Kjansen 1:260e834a8dc1 754 * See the AD7768-1 datasheet for more info
Kjansen 1:260e834a8dc1 755 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 756 */
Kjansen 1:260e834a8dc1 757 int32_t ad77681_set_filter_type(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 758 enum ad77681_sinc5_fir_decimate decimate,
Kjansen 1:260e834a8dc1 759 enum ad77681_filter_type filter,
Kjansen 1:260e834a8dc1 760 uint16_t sinc3_osr)
Kjansen 1:260e834a8dc1 761 {
Kjansen 1:260e834a8dc1 762 int32_t ret;
Kjansen 1:260e834a8dc1 763
Kjansen 1:260e834a8dc1 764 ret = ad77681_spi_reg_write(dev, AD77681_REG_DIGITAL_FILTER, 0x00);
Kjansen 1:260e834a8dc1 765
Kjansen 1:260e834a8dc1 766 /* SINC5 for OSR 8x and 16x*/
Kjansen 1:260e834a8dc1 767 if ((filter == AD77681_SINC5_DECx8) || (filter == AD77681_SINC5_DECx16)) {
Kjansen 1:260e834a8dc1 768 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 769 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 770 AD77681_DIGI_FILTER_FILTER_MSK,
Kjansen 1:260e834a8dc1 771 AD77681_DIGI_FILTER_FILTER(filter));
Kjansen 1:260e834a8dc1 772 /* SINC5 and FIR for osr 32x to 1024x */
Kjansen 1:260e834a8dc1 773 } else if ((filter == AD77681_SINC5) || (filter == AD77681_FIR)) {
Kjansen 1:260e834a8dc1 774 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 775 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 776 AD77681_DIGI_FILTER_FILTER_MSK,
Kjansen 1:260e834a8dc1 777 AD77681_DIGI_FILTER_FILTER(filter));
Kjansen 1:260e834a8dc1 778
Kjansen 1:260e834a8dc1 779 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 780 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 781 AD77681_DIGI_FILTER_DEC_RATE_MSK,
Kjansen 1:260e834a8dc1 782 AD77681_DIGI_FILTER_DEC_RATE(decimate));
Kjansen 1:260e834a8dc1 783 /* SINC3*/
Kjansen 1:260e834a8dc1 784 } else {
Kjansen 1:260e834a8dc1 785 uint8_t sinc3_LSB = 0, sinc3_MSB = 0;
Kjansen 1:260e834a8dc1 786
Kjansen 1:260e834a8dc1 787 sinc3_MSB = sinc3_osr >> 8;
Kjansen 1:260e834a8dc1 788 sinc3_LSB = sinc3_osr & 0x00FF;
Kjansen 1:260e834a8dc1 789
Kjansen 1:260e834a8dc1 790 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 791 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 792 AD77681_DIGI_FILTER_FILTER_MSK,
Kjansen 1:260e834a8dc1 793 AD77681_DIGI_FILTER_FILTER(filter));
Kjansen 1:260e834a8dc1 794
Kjansen 1:260e834a8dc1 795 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 796 AD77681_REG_SINC3_DEC_RATE_MSB,
Kjansen 1:260e834a8dc1 797 AD77681_SINC3_DEC_RATE_MSB_MSK,
Kjansen 1:260e834a8dc1 798 AD77681_SINC3_DEC_RATE_MSB(sinc3_MSB));
Kjansen 1:260e834a8dc1 799
Kjansen 1:260e834a8dc1 800 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 801 AD77681_REG_SINC3_DEC_RATE_LSB,
Kjansen 1:260e834a8dc1 802 AD77681_SINC3_DEC_RATE_LSB_MSK,
Kjansen 1:260e834a8dc1 803 AD77681_SINC3_DEC_RATE_LSB(sinc3_LSB));
Kjansen 1:260e834a8dc1 804 }
Kjansen 1:260e834a8dc1 805
Kjansen 1:260e834a8dc1 806 if ( ret == SUCCESS) {
Kjansen 1:260e834a8dc1 807 dev->decimate = decimate;
Kjansen 1:260e834a8dc1 808 dev->filter = filter;
Kjansen 1:260e834a8dc1 809 /* Sync pulse after each filter change */
Kjansen 1:260e834a8dc1 810 ret |= ad77681_initiate_sync(dev);
Kjansen 1:260e834a8dc1 811 }
Kjansen 1:260e834a8dc1 812
Kjansen 1:260e834a8dc1 813 return ret;
Kjansen 1:260e834a8dc1 814 }
Kjansen 1:260e834a8dc1 815
Kjansen 1:260e834a8dc1 816 /**
Kjansen 1:260e834a8dc1 817 * Enable 50/60 Hz rejection
Kjansen 1:260e834a8dc1 818 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 819 * @param enable - The positive reference buffer selector
Kjansen 1:260e834a8dc1 820 * Accepted values: true
Kjansen 1:260e834a8dc1 821 * false
Kjansen 1:260e834a8dc1 822 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 823 */
Kjansen 1:260e834a8dc1 824 int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 825 uint8_t enable)
Kjansen 1:260e834a8dc1 826 {
Kjansen 1:260e834a8dc1 827 int32_t ret;
Kjansen 1:260e834a8dc1 828
Kjansen 1:260e834a8dc1 829 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 830 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 831 AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK,
Kjansen 1:260e834a8dc1 832 AD77681_DIGI_FILTER_60HZ_REJ_EN(enable));
Kjansen 1:260e834a8dc1 833
Kjansen 1:260e834a8dc1 834 return ret;
Kjansen 1:260e834a8dc1 835 }
Kjansen 1:260e834a8dc1 836
Kjansen 1:260e834a8dc1 837 /**
Kjansen 1:260e834a8dc1 838 * Set the REF- reference buffer
Kjansen 1:260e834a8dc1 839 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 840 * @param continuous_enable - Continous read enable
Kjansen 1:260e834a8dc1 841 * Accepted values: AD77681_CONTINUOUS_READ_ENABLE
Kjansen 1:260e834a8dc1 842 * AD77681_CONTINUOUS_READ_DISABLE
Kjansen 1:260e834a8dc1 843 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 844 */
Kjansen 1:260e834a8dc1 845 int32_t ad77681_set_continuos_read(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 846 enum ad77681_continuous_read continuous_enable)
Kjansen 1:260e834a8dc1 847 {
Kjansen 1:260e834a8dc1 848 int32_t ret;
Kjansen 1:260e834a8dc1 849
Kjansen 1:260e834a8dc1 850 if (continuous_enable) {
Kjansen 1:260e834a8dc1 851 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 852 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 853 AD77681_INTERFACE_CONT_READ_MSK,
Kjansen 1:260e834a8dc1 854 AD77681_INTERFACE_CONT_READ_EN(continuous_enable));
Kjansen 1:260e834a8dc1 855 } else {
Kjansen 1:260e834a8dc1 856 /* To exit the continuous read mode, a key 0x6C must be
Kjansen 1:260e834a8dc1 857 written into the device over the SPI*/
Kjansen 1:260e834a8dc1 858 uint8_t end_key = EXIT_CONT_READ;
Kjansen 1:260e834a8dc1 859 ret = spi_write_and_read(dev->spi_desc, &end_key, 1);
Kjansen 1:260e834a8dc1 860 }
Kjansen 1:260e834a8dc1 861
Kjansen 1:260e834a8dc1 862 return ret;
Kjansen 1:260e834a8dc1 863 }
Kjansen 1:260e834a8dc1 864
Kjansen 1:260e834a8dc1 865 /**
Kjansen 1:260e834a8dc1 866 * Power down / power up the device
Kjansen 1:260e834a8dc1 867 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 868 * @param sleep_wake - Power down, or power up the ADC
Kjansen 1:260e834a8dc1 869 * Accepted values: AD77681_SLEEP
Kjansen 1:260e834a8dc1 870 * AD77681_WAKE
Kjansen 1:260e834a8dc1 871 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 872 */
Kjansen 1:260e834a8dc1 873 int32_t ad77681_power_down(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 874 enum ad77681_sleep_wake sleep_wake)
Kjansen 1:260e834a8dc1 875 {
Kjansen 1:260e834a8dc1 876 int32_t ret;
Kjansen 1:260e834a8dc1 877
Kjansen 1:260e834a8dc1 878 if (sleep_wake == AD77681_SLEEP) {
Kjansen 1:260e834a8dc1 879 ret = ad77681_spi_reg_write(dev, AD77681_REG_POWER_CLOCK,
Kjansen 1:260e834a8dc1 880 AD77681_POWER_CLK_POWER_DOWN);
Kjansen 1:260e834a8dc1 881 } else {
Kjansen 1:260e834a8dc1 882 /* Wake up the ADC over SPI, by sending a wake-up sequence:
Kjansen 1:260e834a8dc1 883 1 followed by 63 zeroes and CS hold low*/
Kjansen 1:260e834a8dc1 884 uint8_t wake_sequence[8] = { 0 };
Kjansen 1:260e834a8dc1 885 /* Insert '1' to the beginning of the wake_sequence*/
Kjansen 1:260e834a8dc1 886 wake_sequence[0] = 0x80;
Kjansen 1:260e834a8dc1 887 ret = spi_write_and_read(dev->spi_desc, wake_sequence,
Kjansen 1:260e834a8dc1 888 ARRAY_SIZE(wake_sequence));
Kjansen 1:260e834a8dc1 889 }
Kjansen 1:260e834a8dc1 890
Kjansen 1:260e834a8dc1 891 return ret;
Kjansen 1:260e834a8dc1 892 }
Kjansen 1:260e834a8dc1 893
Kjansen 1:260e834a8dc1 894 /**
Kjansen 1:260e834a8dc1 895 * Conversion mode and source select
Kjansen 1:260e834a8dc1 896 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 897 * @param conv_mode - Sets the conversion mode of the ADC
Kjansen 1:260e834a8dc1 898 * Accepted values: AD77681_CONV_CONTINUOUS
Kjansen 1:260e834a8dc1 899 * AD77681_CONV_ONE_SHOT
Kjansen 1:260e834a8dc1 900 * AD77681_CONV_SINGLE
Kjansen 1:260e834a8dc1 901 * AD77681_CONV_PERIODIC
Kjansen 1:260e834a8dc1 902 * @param diag_mux_sel - Selects which signal to route through diagnostic mux
Kjansen 1:260e834a8dc1 903 * Accepted values: AD77681_TEMP_SENSOR
Kjansen 1:260e834a8dc1 904 * AD77681_AIN_SHORT
Kjansen 1:260e834a8dc1 905 * AD77681_POSITIVE_FS
Kjansen 1:260e834a8dc1 906 * AD77681_NEGATIVE_FS
Kjansen 1:260e834a8dc1 907 * @param conv_diag_sel - Select the input for conversion as AIN or diagnostic mux
Kjansen 1:260e834a8dc1 908 * Accepted values: true
Kjansen 1:260e834a8dc1 909 * false
Kjansen 1:260e834a8dc1 910 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 911 */
Kjansen 1:260e834a8dc1 912 int32_t ad77681_set_conv_mode(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 913 enum ad77681_conv_mode conv_mode,
Kjansen 1:260e834a8dc1 914 enum ad77681_conv_diag_mux diag_mux_sel,
Kjansen 1:260e834a8dc1 915 bool conv_diag_sel)
Kjansen 1:260e834a8dc1 916 {
Kjansen 1:260e834a8dc1 917 int32_t ret;
Kjansen 1:260e834a8dc1 918
Kjansen 1:260e834a8dc1 919 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 920 AD77681_REG_CONVERSION,
Kjansen 1:260e834a8dc1 921 AD77681_CONVERSION_MODE_MSK,
Kjansen 1:260e834a8dc1 922 AD77681_CONVERSION_MODE(conv_mode));
Kjansen 1:260e834a8dc1 923
Kjansen 1:260e834a8dc1 924 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 925 AD77681_REG_CONVERSION,
Kjansen 1:260e834a8dc1 926 AD77681_CONVERSION_DIAG_MUX_MSK,
Kjansen 1:260e834a8dc1 927 AD77681_CONVERSION_DIAG_MUX_SEL(diag_mux_sel));
Kjansen 1:260e834a8dc1 928
Kjansen 1:260e834a8dc1 929 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 930 AD77681_REG_CONVERSION,
Kjansen 1:260e834a8dc1 931 AD77681_CONVERSION_DIAG_SEL_MSK,
Kjansen 1:260e834a8dc1 932 AD77681_CONVERSION_DIAG_SEL(conv_diag_sel));
Kjansen 1:260e834a8dc1 933
Kjansen 1:260e834a8dc1 934 if (ret == SUCCESS) {
Kjansen 1:260e834a8dc1 935 dev->conv_mode = conv_mode;
Kjansen 1:260e834a8dc1 936 dev->diag_mux_sel = diag_mux_sel;
Kjansen 1:260e834a8dc1 937 dev->conv_diag_sel = conv_diag_sel;
Kjansen 1:260e834a8dc1 938 }
Kjansen 1:260e834a8dc1 939
Kjansen 1:260e834a8dc1 940 return ret;
Kjansen 1:260e834a8dc1 941 }
Kjansen 1:260e834a8dc1 942
Kjansen 1:260e834a8dc1 943 /**
Kjansen 1:260e834a8dc1 944 * Set the Conversion Result Output Length.
Kjansen 1:260e834a8dc1 945 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 946 * @param conv_len - The MCLK divider.
Kjansen 1:260e834a8dc1 947 * Accepted values: AD77681_CONV_24BIT
Kjansen 1:260e834a8dc1 948 * AD77681_CONV_16BIT
Kjansen 1:260e834a8dc1 949 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 950 */
Kjansen 1:260e834a8dc1 951 int32_t ad77681_set_convlen(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 952 enum ad77681_conv_len conv_len)
Kjansen 1:260e834a8dc1 953 {
Kjansen 1:260e834a8dc1 954 int32_t ret;
Kjansen 1:260e834a8dc1 955
Kjansen 1:260e834a8dc1 956 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 957 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 958 AD77681_INTERFACE_CONVLEN_MSK,
Kjansen 1:260e834a8dc1 959 AD77681_INTERFACE_CONVLEN(conv_len));
Kjansen 1:260e834a8dc1 960
Kjansen 1:260e834a8dc1 961 if (ret == SUCCESS) {
Kjansen 1:260e834a8dc1 962 dev->conv_len = conv_len;
Kjansen 1:260e834a8dc1 963 ad77681_get_frame_byte(dev);
Kjansen 1:260e834a8dc1 964 }
Kjansen 1:260e834a8dc1 965
Kjansen 1:260e834a8dc1 966 return ret;
Kjansen 1:260e834a8dc1 967 }
Kjansen 1:260e834a8dc1 968
Kjansen 1:260e834a8dc1 969 /**
Kjansen 1:260e834a8dc1 970 * Activates CRC on all SPI transactions and
Kjansen 1:260e834a8dc1 971 * Selects CRC method as XOR or 8-bit polynomial
Kjansen 1:260e834a8dc1 972 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 973 * @param crc_sel - The CRC type.
Kjansen 1:260e834a8dc1 974 * Accepted values: AD77681_CRC
Kjansen 1:260e834a8dc1 975 * AD77681_XOR
Kjansen 1:260e834a8dc1 976 * AD77681_NO_CRC
Kjansen 1:260e834a8dc1 977 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 978 */
Kjansen 1:260e834a8dc1 979 int32_t ad77681_set_crc_sel(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 980 enum ad77681_crc_sel crc_sel)
Kjansen 1:260e834a8dc1 981 {
Kjansen 1:260e834a8dc1 982 int32_t ret;
Kjansen 1:260e834a8dc1 983
Kjansen 1:260e834a8dc1 984 if (crc_sel == AD77681_NO_CRC) {
Kjansen 1:260e834a8dc1 985 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 986 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 987 AD77681_INTERFACE_CRC_EN_MSK,
Kjansen 1:260e834a8dc1 988 AD77681_INTERFACE_CRC_EN(0));
Kjansen 1:260e834a8dc1 989 } else {
Kjansen 1:260e834a8dc1 990 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 991 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 992 AD77681_INTERFACE_CRC_EN_MSK,
Kjansen 1:260e834a8dc1 993 AD77681_INTERFACE_CRC_EN(1));
Kjansen 1:260e834a8dc1 994
Kjansen 1:260e834a8dc1 995 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 996 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 997 AD77681_INTERFACE_CRC_TYPE_MSK,
Kjansen 1:260e834a8dc1 998 AD77681_INTERFACE_CRC_TYPE(crc_sel));
Kjansen 1:260e834a8dc1 999 }
Kjansen 1:260e834a8dc1 1000
Kjansen 1:260e834a8dc1 1001 if (ret == SUCCESS) {
Kjansen 1:260e834a8dc1 1002 dev->crc_sel = crc_sel;
Kjansen 1:260e834a8dc1 1003 ad77681_get_frame_byte(dev);
Kjansen 1:260e834a8dc1 1004 }
Kjansen 1:260e834a8dc1 1005
Kjansen 1:260e834a8dc1 1006 return ret;
Kjansen 1:260e834a8dc1 1007 }
Kjansen 1:260e834a8dc1 1008
Kjansen 1:260e834a8dc1 1009 /**
Kjansen 1:260e834a8dc1 1010 * Enables Status bits output
Kjansen 1:260e834a8dc1 1011 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1012 * @param status_bit - enable or disable status bit
Kjansen 1:260e834a8dc1 1013 * Accepted values: true
Kjansen 1:260e834a8dc1 1014 * false
Kjansen 1:260e834a8dc1 1015 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1016 */
Kjansen 1:260e834a8dc1 1017 int32_t ad77681_set_status_bit(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1018 bool status_bit)
Kjansen 1:260e834a8dc1 1019 {
Kjansen 1:260e834a8dc1 1020 int32_t ret;
Kjansen 1:260e834a8dc1 1021
Kjansen 1:260e834a8dc1 1022 // Set status bit
Kjansen 1:260e834a8dc1 1023 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1024 AD77681_REG_INTERFACE_FORMAT,
Kjansen 1:260e834a8dc1 1025 AD77681_INTERFACE_STATUS_EN_MSK,
Kjansen 1:260e834a8dc1 1026 AD77681_INTERFACE_STATUS_EN(status_bit));
Kjansen 1:260e834a8dc1 1027
Kjansen 1:260e834a8dc1 1028 if (ret == SUCCESS) {
Kjansen 1:260e834a8dc1 1029 dev->status_bit = status_bit;
Kjansen 1:260e834a8dc1 1030 ad77681_get_frame_byte(dev);
Kjansen 1:260e834a8dc1 1031 }
Kjansen 1:260e834a8dc1 1032
Kjansen 1:260e834a8dc1 1033 return ret;
Kjansen 1:260e834a8dc1 1034 }
Kjansen 1:260e834a8dc1 1035
Kjansen 1:260e834a8dc1 1036 /**
Kjansen 1:260e834a8dc1 1037 * Device reset over SPI.
Kjansen 1:260e834a8dc1 1038 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1039 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1040 */
Kjansen 1:260e834a8dc1 1041 int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 1042 {
Kjansen 1:260e834a8dc1 1043 int32_t ret = 0;
Kjansen 1:260e834a8dc1 1044
Kjansen 1:260e834a8dc1 1045 // Two writes are required to initialize the reset
Kjansen 1:260e834a8dc1 1046 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1047 AD77681_REG_SYNC_RESET,
Kjansen 1:260e834a8dc1 1048 AD77681_SYNC_RST_SPI_RESET_MSK,
Kjansen 1:260e834a8dc1 1049 AD77681_SYNC_RST_SPI_RESET(0x3));
Kjansen 1:260e834a8dc1 1050
Kjansen 1:260e834a8dc1 1051 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1052 AD77681_REG_SYNC_RESET,
Kjansen 1:260e834a8dc1 1053 AD77681_SYNC_RST_SPI_RESET_MSK,
Kjansen 1:260e834a8dc1 1054 AD77681_SYNC_RST_SPI_RESET(0x2));
Kjansen 1:260e834a8dc1 1055
Kjansen 1:260e834a8dc1 1056 return ret;
Kjansen 1:260e834a8dc1 1057 }
Kjansen 1:260e834a8dc1 1058
Kjansen 1:260e834a8dc1 1059 /**
Kjansen 1:260e834a8dc1 1060 * Initiate a SYNC_OUT pulse over spi
Kjansen 1:260e834a8dc1 1061 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1062 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1063 */
Kjansen 1:260e834a8dc1 1064 int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 1065 {
Kjansen 1:260e834a8dc1 1066 return ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1067 AD77681_REG_SYNC_RESET,
Kjansen 1:260e834a8dc1 1068 AD77681_SYNC_RST_SPI_STARTB_MSK,
Kjansen 1:260e834a8dc1 1069 AD77681_SYNC_RST_SPI_STARTB(0));
Kjansen 1:260e834a8dc1 1070 }
Kjansen 1:260e834a8dc1 1071
Kjansen 1:260e834a8dc1 1072 /**
Kjansen 1:260e834a8dc1 1073 * Write to offset registers
Kjansen 1:260e834a8dc1 1074 * @param dev The device structure.
Kjansen 1:260e834a8dc1 1075 * @param value The desired value of the whole 24-bit offset register
Kjansen 1:260e834a8dc1 1076 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1077 */
Kjansen 1:260e834a8dc1 1078 int32_t ad77681_apply_offset(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1079 uint32_t value)
Kjansen 1:260e834a8dc1 1080 {
Kjansen 1:260e834a8dc1 1081 int32_t ret;
Kjansen 1:260e834a8dc1 1082 uint8_t offset_HI = 0, offset_MID = 0, offset_LO = 0;
Kjansen 1:260e834a8dc1 1083
Kjansen 1:260e834a8dc1 1084 offset_HI = (value & 0x00FF0000) >> 16;
Kjansen 1:260e834a8dc1 1085 offset_MID = (value & 0x0000FF00) >> 8;
Kjansen 1:260e834a8dc1 1086 offset_LO = (value & 0x000000FF);
Kjansen 1:260e834a8dc1 1087
Kjansen 1:260e834a8dc1 1088 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1089 AD77681_REG_OFFSET_HI,
Kjansen 1:260e834a8dc1 1090 AD77681_OFFSET_HI_MSK,
Kjansen 1:260e834a8dc1 1091 AD77681_OFFSET_HI(offset_HI));
Kjansen 1:260e834a8dc1 1092
Kjansen 1:260e834a8dc1 1093 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1094 AD77681_REG_OFFSET_MID,
Kjansen 1:260e834a8dc1 1095 AD77681_OFFSET_MID_MSK,
Kjansen 1:260e834a8dc1 1096 AD77681_OFFSET_MID(offset_MID));
Kjansen 1:260e834a8dc1 1097
Kjansen 1:260e834a8dc1 1098 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1099 AD77681_REG_OFFSET_LO,
Kjansen 1:260e834a8dc1 1100 AD77681_OFFSET_LO_MSK,
Kjansen 1:260e834a8dc1 1101 AD77681_OFFSET_LO(offset_LO));
Kjansen 1:260e834a8dc1 1102
Kjansen 1:260e834a8dc1 1103 return ret;
Kjansen 1:260e834a8dc1 1104 }
Kjansen 1:260e834a8dc1 1105
Kjansen 1:260e834a8dc1 1106 /**
Kjansen 1:260e834a8dc1 1107 * Write to gain registers
Kjansen 1:260e834a8dc1 1108 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1109 * @param value - The desired value of the whole 24-bit gain register
Kjansen 1:260e834a8dc1 1110 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1111 */
Kjansen 1:260e834a8dc1 1112 int32_t ad77681_apply_gain(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1113 uint32_t value)
Kjansen 1:260e834a8dc1 1114 {
Kjansen 1:260e834a8dc1 1115 int32_t ret;
Kjansen 1:260e834a8dc1 1116 uint8_t gain_HI = 0, gain_MID = 0, gain_LO = 0;
Kjansen 1:260e834a8dc1 1117
Kjansen 1:260e834a8dc1 1118 gain_HI = (value & 0x00FF0000) >> 16;
Kjansen 1:260e834a8dc1 1119 gain_MID = (value & 0x0000FF00) >> 8;
Kjansen 1:260e834a8dc1 1120 gain_LO = (value & 0x000000FF);
Kjansen 1:260e834a8dc1 1121
Kjansen 1:260e834a8dc1 1122 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1123 AD77681_REG_GAIN_HI,
Kjansen 1:260e834a8dc1 1124 AD77681_GAIN_HI_MSK,
Kjansen 1:260e834a8dc1 1125 AD77681_GAIN_HI(gain_HI));
Kjansen 1:260e834a8dc1 1126
Kjansen 1:260e834a8dc1 1127 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1128 AD77681_REG_GAIN_MID,
Kjansen 1:260e834a8dc1 1129 AD77681_GAIN_MID_MSK,
Kjansen 1:260e834a8dc1 1130 AD77681_GAIN_MID(gain_MID));
Kjansen 1:260e834a8dc1 1131
Kjansen 1:260e834a8dc1 1132 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1133 AD77681_REG_GAIN_LO,
Kjansen 1:260e834a8dc1 1134 AD77681_GAIN_LOW_MSK,
Kjansen 1:260e834a8dc1 1135 AD77681_GAIN_LOW(gain_LO));
Kjansen 1:260e834a8dc1 1136
Kjansen 1:260e834a8dc1 1137 return ret;
Kjansen 1:260e834a8dc1 1138 }
Kjansen 1:260e834a8dc1 1139
Kjansen 1:260e834a8dc1 1140 /**
Kjansen 1:260e834a8dc1 1141 * Upload sequence for Programmamble FIR filter
Kjansen 1:260e834a8dc1 1142 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1143 * @param coeffs - Pointer to the desired filter coefficients array to be written
Kjansen 1:260e834a8dc1 1144 * @param num_coeffs - Count of active filter coeffs
Kjansen 1:260e834a8dc1 1145 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1146 */
Kjansen 1:260e834a8dc1 1147 int32_t ad77681_programmable_filter(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1148 const float *coeffs,
Kjansen 1:260e834a8dc1 1149 uint8_t num_coeffs)
Kjansen 1:260e834a8dc1 1150 {
Kjansen 1:260e834a8dc1 1151 uint8_t coeffs_buf[4], coeffs_index, check_back = 0, i, address;
Kjansen 1:260e834a8dc1 1152 uint32_t twait;
Kjansen 1:260e834a8dc1 1153 int32_t twos_complement, ret;
Kjansen 1:260e834a8dc1 1154 const uint8_t coeff_reg_length = 56;
Kjansen 1:260e834a8dc1 1155
Kjansen 1:260e834a8dc1 1156 /* Specific keys in the upload sequence */
Kjansen 1:260e834a8dc1 1157 const uint8_t key1 = 0xAC, key2 = 0x45, key3 = 0x55;
Kjansen 1:260e834a8dc1 1158 /* Scaling factor for all coefficients 2^22 */
Kjansen 1:260e834a8dc1 1159 const float coeff_scale_factor = (1 << 22);
Kjansen 1:260e834a8dc1 1160 /* Wait time in uS necessary to access the COEFF_CONTROL and */
Kjansen 1:260e834a8dc1 1161 /* COEFF_DATA registers. Twait = 512/MCLK */
Kjansen 1:260e834a8dc1 1162 twait = (uint32_t)(((512.0) / ((float)(dev->mclk))) * 1000.0) + 1;
Kjansen 1:260e834a8dc1 1163
Kjansen 1:260e834a8dc1 1164 /* Set Filter to FIR */
Kjansen 1:260e834a8dc1 1165 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1166 AD77681_REG_DIGITAL_FILTER,
Kjansen 1:260e834a8dc1 1167 AD77681_DIGI_FILTER_FILTER_MSK,
Kjansen 1:260e834a8dc1 1168 AD77681_DIGI_FILTER_FILTER(AD77681_FIR));
Kjansen 1:260e834a8dc1 1169
Kjansen 1:260e834a8dc1 1170 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1171 if (ret < 0)
Kjansen 1:260e834a8dc1 1172 return ret;
Kjansen 1:260e834a8dc1 1173
Kjansen 1:260e834a8dc1 1174 /* Write the first access key to the ACCESS_KEY register */
Kjansen 1:260e834a8dc1 1175 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1176 AD77681_REG_ACCESS_KEY,
Kjansen 1:260e834a8dc1 1177 AD77681_ACCESS_KEY_MSK,
Kjansen 1:260e834a8dc1 1178 AD77681_ACCESS_KEY(key1));
Kjansen 1:260e834a8dc1 1179
Kjansen 1:260e834a8dc1 1180 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1181 if (ret < 0)
Kjansen 1:260e834a8dc1 1182 return ret;
Kjansen 1:260e834a8dc1 1183
Kjansen 1:260e834a8dc1 1184 /* Write the second access key to the ACCESS_KEY register */
Kjansen 1:260e834a8dc1 1185 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1186 AD77681_REG_ACCESS_KEY,
Kjansen 1:260e834a8dc1 1187 AD77681_ACCESS_KEY_MSK,
Kjansen 1:260e834a8dc1 1188 AD77681_ACCESS_KEY(key2));
Kjansen 1:260e834a8dc1 1189
Kjansen 1:260e834a8dc1 1190 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1191 if (ret < 0)
Kjansen 1:260e834a8dc1 1192 return ret;
Kjansen 1:260e834a8dc1 1193
Kjansen 1:260e834a8dc1 1194 /* Read the the ACCESS_KEY register bit 0, the key bit */
Kjansen 1:260e834a8dc1 1195 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1196 AD77681_REG_ACCESS_KEY,
Kjansen 1:260e834a8dc1 1197 AD77681_ACCESS_KEY_CHECK_MSK,
Kjansen 1:260e834a8dc1 1198 &check_back);
Kjansen 1:260e834a8dc1 1199
Kjansen 1:260e834a8dc1 1200 /* Checks ret and key bit, return FAILURE in case key bit not equal to 1 */
Kjansen 1:260e834a8dc1 1201 if ((ret < 0) || (check_back != 1))
Kjansen 1:260e834a8dc1 1202 return FAILURE;
Kjansen 1:260e834a8dc1 1203
Kjansen 1:260e834a8dc1 1204 /* Set the initial adress to 0 and enable the write and coefficient access bits */
Kjansen 1:260e834a8dc1 1205 address = AD77681_COEF_CONTROL_COEFFACCESSEN_MSK
Kjansen 1:260e834a8dc1 1206 | AD77681_COEF_CONTROL_COEFFWRITEEN_MSK;
Kjansen 1:260e834a8dc1 1207
Kjansen 1:260e834a8dc1 1208 /* The COEFF_DATA register has to be filled with 56 coeffs.*/
Kjansen 1:260e834a8dc1 1209 /* In case the number of active filter coefficient is less */
Kjansen 1:260e834a8dc1 1210 /* than 56, zeros will be padded before the desired coeff. */
Kjansen 1:260e834a8dc1 1211 for (i = 0; i < coeff_reg_length; i++) {
Kjansen 1:260e834a8dc1 1212 /* Set the coeff address */
Kjansen 1:260e834a8dc1 1213 ret = ad77681_spi_reg_write(dev,
Kjansen 1:260e834a8dc1 1214 AD77681_REG_COEFF_CONTROL,
Kjansen 1:260e834a8dc1 1215 address);
Kjansen 1:260e834a8dc1 1216
Kjansen 1:260e834a8dc1 1217 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1218 if (ret < 0)
Kjansen 1:260e834a8dc1 1219 return ret;
Kjansen 1:260e834a8dc1 1220
Kjansen 1:260e834a8dc1 1221 /* Wait for Twait uSeconds*/
Kjansen 1:260e834a8dc1 1222 udelay(twait);
Kjansen 1:260e834a8dc1 1223
Kjansen 1:260e834a8dc1 1224 /* Padding of zeros before the desired coef in case the coef count in less than 56 */
Kjansen 1:260e834a8dc1 1225 if((num_coeffs + i) < coeff_reg_length) {
Kjansen 1:260e834a8dc1 1226 /* wirte zeroes to COEFF_DATA, in case of less coeffs than 56*/
Kjansen 1:260e834a8dc1 1227 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
Kjansen 1:260e834a8dc1 1228 coeffs_buf[1] = 0;
Kjansen 1:260e834a8dc1 1229 coeffs_buf[2] = 0;
Kjansen 1:260e834a8dc1 1230 coeffs_buf[3] = 0;
Kjansen 1:260e834a8dc1 1231 } else {/* Writting of desired filter coefficients */
Kjansen 1:260e834a8dc1 1232 /* Computes the index of coefficients to be uploaded */
Kjansen 1:260e834a8dc1 1233 coeffs_index = (num_coeffs + i) - coeff_reg_length;
Kjansen 1:260e834a8dc1 1234 /* Scaling the coefficient value and converting it to 2's complement */
Kjansen 1:260e834a8dc1 1235 twos_complement = (int32_t)(coeffs[coeffs_index] * coeff_scale_factor);
Kjansen 1:260e834a8dc1 1236
Kjansen 1:260e834a8dc1 1237 /* Write coefficients to COEFF_DATA */
Kjansen 1:260e834a8dc1 1238 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
Kjansen 1:260e834a8dc1 1239 coeffs_buf[1] = (twos_complement & 0xFF0000) >> 16;
Kjansen 1:260e834a8dc1 1240 coeffs_buf[2] = (twos_complement & 0x00FF00) >> 8;
Kjansen 1:260e834a8dc1 1241 coeffs_buf[3] = (twos_complement & 0x0000FF);
Kjansen 1:260e834a8dc1 1242 }
Kjansen 1:260e834a8dc1 1243
Kjansen 1:260e834a8dc1 1244 ret = spi_write_and_read(dev->spi_desc, coeffs_buf, 4);
Kjansen 1:260e834a8dc1 1245
Kjansen 1:260e834a8dc1 1246 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1247 if (ret < 0)
Kjansen 1:260e834a8dc1 1248 return ret;
Kjansen 1:260e834a8dc1 1249
Kjansen 1:260e834a8dc1 1250 /* Increment the address*/
Kjansen 1:260e834a8dc1 1251 address++;
Kjansen 1:260e834a8dc1 1252 /* Wait for Twait uSeconds*/
Kjansen 1:260e834a8dc1 1253 udelay(twait);
Kjansen 1:260e834a8dc1 1254 }
Kjansen 1:260e834a8dc1 1255
Kjansen 1:260e834a8dc1 1256 /* Disable coefficient write */
Kjansen 1:260e834a8dc1 1257 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1258 AD77681_REG_COEFF_CONTROL,
Kjansen 1:260e834a8dc1 1259 AD77681_COEF_CONTROL_COEFFWRITEEN_MSK,
Kjansen 1:260e834a8dc1 1260 AD77681_COEF_CONTROL_COEFFWRITEEN(0x00));
Kjansen 1:260e834a8dc1 1261
Kjansen 1:260e834a8dc1 1262 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1263 if (ret < 0)
Kjansen 1:260e834a8dc1 1264 return ret;
Kjansen 1:260e834a8dc1 1265
Kjansen 1:260e834a8dc1 1266 udelay(twait);
Kjansen 1:260e834a8dc1 1267
Kjansen 1:260e834a8dc1 1268 /* Disable coefficient access */
Kjansen 1:260e834a8dc1 1269 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1270 AD77681_REG_COEFF_CONTROL,
Kjansen 1:260e834a8dc1 1271 AD77681_COEF_CONTROL_COEFFACCESSEN_MSK,
Kjansen 1:260e834a8dc1 1272 AD77681_COEF_CONTROL_COEFFACCESSEN(0x00));
Kjansen 1:260e834a8dc1 1273
Kjansen 1:260e834a8dc1 1274 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1275 if (ret < 0)
Kjansen 1:260e834a8dc1 1276 return ret;
Kjansen 1:260e834a8dc1 1277
Kjansen 1:260e834a8dc1 1278 /* Toggle the synchronization pulse and to begin reading data */
Kjansen 1:260e834a8dc1 1279 /* Write 0x800000 to COEFF_DATA */
Kjansen 1:260e834a8dc1 1280 coeffs_buf[0] = AD77681_REG_WRITE(AD77681_REG_COEFF_DATA);
Kjansen 1:260e834a8dc1 1281 coeffs_buf[1] = 0x80;
Kjansen 1:260e834a8dc1 1282 coeffs_buf[2] = 0x00;
Kjansen 1:260e834a8dc1 1283 coeffs_buf[3] = 0x00;
Kjansen 1:260e834a8dc1 1284
Kjansen 1:260e834a8dc1 1285 ret = spi_write_and_read(dev->spi_desc, coeffs_buf, 4);
Kjansen 1:260e834a8dc1 1286
Kjansen 1:260e834a8dc1 1287 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1288 if (ret < 0)
Kjansen 1:260e834a8dc1 1289 return ret;
Kjansen 1:260e834a8dc1 1290
Kjansen 1:260e834a8dc1 1291 /* Exit filter upload by wirting specific access key 0x55*/
Kjansen 1:260e834a8dc1 1292 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1293 AD77681_REG_ACCESS_KEY,
Kjansen 1:260e834a8dc1 1294 AD77681_ACCESS_KEY_MSK,
Kjansen 1:260e834a8dc1 1295 AD77681_ACCESS_KEY(key3));
Kjansen 1:260e834a8dc1 1296
Kjansen 1:260e834a8dc1 1297 /* Check return value before proceeding */
Kjansen 1:260e834a8dc1 1298 if (ret < 0)
Kjansen 1:260e834a8dc1 1299 return ret;
Kjansen 1:260e834a8dc1 1300
Kjansen 1:260e834a8dc1 1301 /* Send synchronization pulse */
Kjansen 1:260e834a8dc1 1302 ad77681_initiate_sync(dev);
Kjansen 1:260e834a8dc1 1303
Kjansen 1:260e834a8dc1 1304 return ret;
Kjansen 1:260e834a8dc1 1305 }
Kjansen 1:260e834a8dc1 1306
Kjansen 1:260e834a8dc1 1307 /**
Kjansen 1:260e834a8dc1 1308 * Read value from GPIOs present in AD7768-1 separately, or all GPIOS at once.
Kjansen 1:260e834a8dc1 1309 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1310 * @param value - Readed value.
Kjansen 1:260e834a8dc1 1311 * @param gpio_number - Number of GPIO, the value will be written into
Kjansen 1:260e834a8dc1 1312 * Accepted values: AD77681_GPIO0
Kjansen 1:260e834a8dc1 1313 * AD77681_GPIO1
Kjansen 1:260e834a8dc1 1314 * AD77681_GPIO2
Kjansen 1:260e834a8dc1 1315 * AD77681_GPIO3
Kjansen 1:260e834a8dc1 1316 * AD77681_ALL_GPIOS
Kjansen 1:260e834a8dc1 1317 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1318 */
Kjansen 1:260e834a8dc1 1319 int32_t ad77681_gpio_read(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1320 uint8_t *value,
Kjansen 1:260e834a8dc1 1321 enum ad77681_gpios gpio_number)
Kjansen 1:260e834a8dc1 1322 {
Kjansen 1:260e834a8dc1 1323 int32_t ret;
Kjansen 1:260e834a8dc1 1324
Kjansen 1:260e834a8dc1 1325 switch (gpio_number) {
Kjansen 1:260e834a8dc1 1326 case AD77681_GPIO0: /* Read to GPIO0 */
Kjansen 1:260e834a8dc1 1327 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1328 AD77681_REG_GPIO_READ,
Kjansen 1:260e834a8dc1 1329 AD77681_GPIO_READ_0_MSK,
Kjansen 1:260e834a8dc1 1330 value);
Kjansen 1:260e834a8dc1 1331 break;
Kjansen 1:260e834a8dc1 1332 case AD77681_GPIO1: /* Read to GPIO1 */
Kjansen 1:260e834a8dc1 1333 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1334 AD77681_REG_GPIO_READ,
Kjansen 1:260e834a8dc1 1335 AD77681_GPIO_READ_1_MSK,
Kjansen 1:260e834a8dc1 1336 value);
Kjansen 1:260e834a8dc1 1337 break;
Kjansen 1:260e834a8dc1 1338 case AD77681_GPIO2: /* Read to GPIO2 */
Kjansen 1:260e834a8dc1 1339 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1340 AD77681_REG_GPIO_READ,
Kjansen 1:260e834a8dc1 1341 AD77681_GPIO_READ_2_MSK,
Kjansen 1:260e834a8dc1 1342 value);
Kjansen 1:260e834a8dc1 1343 break;
Kjansen 1:260e834a8dc1 1344 case AD77681_GPIO3: /* Read to GPIO3 */
Kjansen 1:260e834a8dc1 1345 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1346 AD77681_REG_GPIO_READ,
Kjansen 1:260e834a8dc1 1347 AD77681_GPIO_READ_3_MSK,
Kjansen 1:260e834a8dc1 1348 value);
Kjansen 1:260e834a8dc1 1349 break;
Kjansen 1:260e834a8dc1 1350 case AD77681_ALL_GPIOS: /* Read to all GPIOs */
Kjansen 1:260e834a8dc1 1351 ret = ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1352 AD77681_REG_GPIO_READ,
Kjansen 1:260e834a8dc1 1353 AD77681_GPIO_READ_ALL_MSK,
Kjansen 1:260e834a8dc1 1354 value);
Kjansen 1:260e834a8dc1 1355 break;
Kjansen 1:260e834a8dc1 1356 default:
Kjansen 1:260e834a8dc1 1357 return FAILURE;
Kjansen 1:260e834a8dc1 1358 break;
Kjansen 1:260e834a8dc1 1359 }
Kjansen 1:260e834a8dc1 1360
Kjansen 1:260e834a8dc1 1361 return ret;
Kjansen 1:260e834a8dc1 1362 }
Kjansen 1:260e834a8dc1 1363
Kjansen 1:260e834a8dc1 1364 /**
Kjansen 1:260e834a8dc1 1365 * Write value to GPIOs present in AD7768-1 separately, or all GPIOS at once.
Kjansen 1:260e834a8dc1 1366 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1367 * @param value - Value to be written into GPIO
Kjansen 1:260e834a8dc1 1368 * Accepted values: GPIO_HIGH
Kjansen 1:260e834a8dc1 1369 * GPIO_LOW
Kjansen 1:260e834a8dc1 1370 * 4-bit value for all gpios
Kjansen 1:260e834a8dc1 1371 * @param gpio_number - Number of GPIO, the value will be written into
Kjansen 1:260e834a8dc1 1372 * Accepted values: AD77681_GPIO0
Kjansen 1:260e834a8dc1 1373 * AD77681_GPIO1
Kjansen 1:260e834a8dc1 1374 * AD77681_GPIO2
Kjansen 1:260e834a8dc1 1375 * AD77681_GPIO3
Kjansen 1:260e834a8dc1 1376 * AD77681_ALL_GPIOS
Kjansen 1:260e834a8dc1 1377 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1378 */
Kjansen 1:260e834a8dc1 1379 int32_t ad77681_gpio_write(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1380 uint8_t value,
Kjansen 1:260e834a8dc1 1381 enum ad77681_gpios gpio_number)
Kjansen 1:260e834a8dc1 1382 {
Kjansen 1:260e834a8dc1 1383 int32_t ret;
Kjansen 1:260e834a8dc1 1384
Kjansen 1:260e834a8dc1 1385 switch (gpio_number) {
Kjansen 1:260e834a8dc1 1386 case AD77681_GPIO0: /* Write to GPIO0 */
Kjansen 1:260e834a8dc1 1387 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1388 AD77681_REG_GPIO_WRITE,
Kjansen 1:260e834a8dc1 1389 AD77681_GPIO_WRITE_0_MSK,
Kjansen 1:260e834a8dc1 1390 AD77681_GPIO_WRITE_0(value));
Kjansen 1:260e834a8dc1 1391 break;
Kjansen 1:260e834a8dc1 1392 case AD77681_GPIO1: /* Write to GPIO1 */
Kjansen 1:260e834a8dc1 1393 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1394 AD77681_REG_GPIO_WRITE,
Kjansen 1:260e834a8dc1 1395 AD77681_GPIO_WRITE_1_MSK,
Kjansen 1:260e834a8dc1 1396 AD77681_GPIO_WRITE_1(value));
Kjansen 1:260e834a8dc1 1397 break;
Kjansen 1:260e834a8dc1 1398 case AD77681_GPIO2: /* Write to GPIO2 */
Kjansen 1:260e834a8dc1 1399 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1400 AD77681_REG_GPIO_WRITE,
Kjansen 1:260e834a8dc1 1401 AD77681_GPIO_WRITE_2_MSK,
Kjansen 1:260e834a8dc1 1402 AD77681_GPIO_WRITE_2(value));
Kjansen 1:260e834a8dc1 1403 break;
Kjansen 1:260e834a8dc1 1404 case AD77681_GPIO3: /* Write to GPIO3 */
Kjansen 1:260e834a8dc1 1405 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1406 AD77681_REG_GPIO_WRITE,
Kjansen 1:260e834a8dc1 1407 AD77681_GPIO_WRITE_3_MSK,
Kjansen 1:260e834a8dc1 1408 AD77681_GPIO_WRITE_3(value));
Kjansen 1:260e834a8dc1 1409 break;
Kjansen 1:260e834a8dc1 1410 case AD77681_ALL_GPIOS: /* Write to all GPIOs */
Kjansen 1:260e834a8dc1 1411 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1412 AD77681_REG_GPIO_WRITE,
Kjansen 1:260e834a8dc1 1413 AD77681_GPIO_WRITE_ALL_MSK,
Kjansen 1:260e834a8dc1 1414 AD77681_GPIO_WRITE_ALL(value));
Kjansen 1:260e834a8dc1 1415 break;
Kjansen 1:260e834a8dc1 1416 default:
Kjansen 1:260e834a8dc1 1417 return FAILURE;
Kjansen 1:260e834a8dc1 1418 break;
Kjansen 1:260e834a8dc1 1419 }
Kjansen 1:260e834a8dc1 1420
Kjansen 1:260e834a8dc1 1421 return ret;
Kjansen 1:260e834a8dc1 1422 }
Kjansen 1:260e834a8dc1 1423
Kjansen 1:260e834a8dc1 1424 /**
Kjansen 1:260e834a8dc1 1425 * Set AD7768-1s GPIO as input or output.
Kjansen 1:260e834a8dc1 1426 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1427 * @param direction - Direction of the GPIO
Kjansen 1:260e834a8dc1 1428 * Accepted values: GPIO_INPUT
Kjansen 1:260e834a8dc1 1429 * GPIO_OUTPUT
Kjansen 1:260e834a8dc1 1430 * 4-bit value for all gpios
Kjansen 1:260e834a8dc1 1431 * @param gpio_number - Number of GPIO, which will be affected
Kjansen 1:260e834a8dc1 1432 * Accepted values: AD77681_GPIO0
Kjansen 1:260e834a8dc1 1433 * AD77681_GPIO1
Kjansen 1:260e834a8dc1 1434 * AD77681_GPIO2
Kjansen 1:260e834a8dc1 1435 * AD77681_GPIO3
Kjansen 1:260e834a8dc1 1436 * AD77681_ALL_GPIOS
Kjansen 1:260e834a8dc1 1437 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1438 */
Kjansen 1:260e834a8dc1 1439 int32_t ad77681_gpio_inout(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1440 uint8_t direction,
Kjansen 1:260e834a8dc1 1441 enum ad77681_gpios gpio_number)
Kjansen 1:260e834a8dc1 1442 {
Kjansen 1:260e834a8dc1 1443 int32_t ret;
Kjansen 1:260e834a8dc1 1444
Kjansen 1:260e834a8dc1 1445 switch (gpio_number) {
Kjansen 1:260e834a8dc1 1446 case AD77681_GPIO0: /* Set direction of GPIO0 */
Kjansen 1:260e834a8dc1 1447 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1448 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1449 AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK,
Kjansen 1:260e834a8dc1 1450 AD77681_GPIO_CNTRL_GPIO0_OP_EN(direction));
Kjansen 1:260e834a8dc1 1451 break;
Kjansen 1:260e834a8dc1 1452 case AD77681_GPIO1: /* Set direction of GPIO1 */
Kjansen 1:260e834a8dc1 1453 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1454 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1455 AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK,
Kjansen 1:260e834a8dc1 1456 AD77681_GPIO_CNTRL_GPIO1_OP_EN(direction));
Kjansen 1:260e834a8dc1 1457 break;
Kjansen 1:260e834a8dc1 1458 case AD77681_GPIO2: /* Set direction of GPIO2 */
Kjansen 1:260e834a8dc1 1459 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1460 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1461 AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK,
Kjansen 1:260e834a8dc1 1462 AD77681_GPIO_CNTRL_GPIO2_OP_EN(direction));
Kjansen 1:260e834a8dc1 1463 break;
Kjansen 1:260e834a8dc1 1464 case AD77681_GPIO3: /* Set direction of GPIO3 */
Kjansen 1:260e834a8dc1 1465 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1466 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1467 AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK,
Kjansen 1:260e834a8dc1 1468 AD77681_GPIO_CNTRL_GPIO3_OP_EN(direction));
Kjansen 1:260e834a8dc1 1469 break;
Kjansen 1:260e834a8dc1 1470 case AD77681_ALL_GPIOS: /* Set direction of all GPIOs */
Kjansen 1:260e834a8dc1 1471 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1472 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1473 AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK,
Kjansen 1:260e834a8dc1 1474 AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(direction));
Kjansen 1:260e834a8dc1 1475 break;
Kjansen 1:260e834a8dc1 1476 default:
Kjansen 1:260e834a8dc1 1477 return FAILURE;
Kjansen 1:260e834a8dc1 1478 break;
Kjansen 1:260e834a8dc1 1479 }
Kjansen 1:260e834a8dc1 1480
Kjansen 1:260e834a8dc1 1481 return ret;
Kjansen 1:260e834a8dc1 1482 }
Kjansen 1:260e834a8dc1 1483
Kjansen 1:260e834a8dc1 1484 /**
Kjansen 1:260e834a8dc1 1485 * Enable global GPIO bit.
Kjansen 1:260e834a8dc1 1486 * This bit must be set high to change GPIO settings.
Kjansen 1:260e834a8dc1 1487 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1488 * @param gpio_enable - Enable or diable the global GPIO pin
Kjansen 1:260e834a8dc1 1489 * Accepted values: AD77681_GLOBAL_GPIO_ENABLE
Kjansen 1:260e834a8dc1 1490 * AD77681_GLOBAL_GPIO_DISABLE
Kjansen 1:260e834a8dc1 1491 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1492 */
Kjansen 1:260e834a8dc1 1493 int32_t ad77681_global_gpio(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1494 enum ad77681_gobal_gpio_enable gpio_enable)
Kjansen 1:260e834a8dc1 1495 {
Kjansen 1:260e834a8dc1 1496 return ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1497 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1498 AD77681_GPIO_CNTRL_UGPIO_EN_MSK,
Kjansen 1:260e834a8dc1 1499 AD77681_GPIO_CNTRL_UGPIO_EN(gpio_enable));
Kjansen 1:260e834a8dc1 1500 }
Kjansen 1:260e834a8dc1 1501
Kjansen 1:260e834a8dc1 1502 /**
Kjansen 1:260e834a8dc1 1503 * Read and write from ADC scratchpad register to check SPI Communication in
Kjansen 1:260e834a8dc1 1504 * the very beginning, during inicialization.
Kjansen 1:260e834a8dc1 1505 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1506 * @param sequence - The sequence which will be written into scratchpad and the
Kjansen 1:260e834a8dc1 1507 * readed sequence will be returned
Kjansen 1:260e834a8dc1 1508 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1509 */
Kjansen 1:260e834a8dc1 1510 int32_t ad77681_scratchpad(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1511 uint8_t *sequence)
Kjansen 1:260e834a8dc1 1512 {
Kjansen 1:260e834a8dc1 1513 int32_t ret;
Kjansen 1:260e834a8dc1 1514 const uint8_t check = *sequence;/* Save the original sequence */
Kjansen 1:260e834a8dc1 1515 uint8_t ret_sequence = 0;/* Return sequence */
Kjansen 1:260e834a8dc1 1516
Kjansen 1:260e834a8dc1 1517 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1518 AD77681_REG_SCRATCH_PAD,
Kjansen 1:260e834a8dc1 1519 AD77681_SCRATCHPAD_MSK,
Kjansen 1:260e834a8dc1 1520 AD77681_SCRATCHPAD(check));
Kjansen 1:260e834a8dc1 1521
Kjansen 1:260e834a8dc1 1522 ret |= ad77681_spi_read_mask(dev,
Kjansen 1:260e834a8dc1 1523 AD77681_REG_SCRATCH_PAD,
Kjansen 1:260e834a8dc1 1524 AD77681_SCRATCHPAD_MSK,
Kjansen 1:260e834a8dc1 1525 &ret_sequence);
Kjansen 1:260e834a8dc1 1526
Kjansen 1:260e834a8dc1 1527 if (check != ret_sequence)/* Compare original an returned sequence */
Kjansen 1:260e834a8dc1 1528 return FAILURE;
Kjansen 1:260e834a8dc1 1529
Kjansen 1:260e834a8dc1 1530 return ret;
Kjansen 1:260e834a8dc1 1531 }
Kjansen 1:260e834a8dc1 1532
Kjansen 1:260e834a8dc1 1533 /**
Kjansen 1:260e834a8dc1 1534 * Set AD7768-1s GPIO output type between strong driver and open drain.
Kjansen 1:260e834a8dc1 1535 * GPIO3 can not be accessed!
Kjansen 1:260e834a8dc1 1536 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1537 * @param gpio_number - AD7768-1s GPIO to be affected (Only GPIO0, GPIO1 and GPIO2)
Kjansen 1:260e834a8dc1 1538 * Accepted values: AD77681_GPIO0
Kjansen 1:260e834a8dc1 1539 * AD77681_GPIO1
Kjansen 1:260e834a8dc1 1540 * AD77681_GPIO2
Kjansen 1:260e834a8dc1 1541 * AD77681_ALL_GPIOS
Kjansen 1:260e834a8dc1 1542 *
Kjansen 1:260e834a8dc1 1543 * @param output_type - Output type of the GPIO
Kjansen 1:260e834a8dc1 1544 * Accepted values: AD77681_GPIO_STRONG_DRIVER
Kjansen 1:260e834a8dc1 1545 * AD77681_GPIO_OPEN_DRAIN
Kjansen 1:260e834a8dc1 1546 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1547 */
Kjansen 1:260e834a8dc1 1548 int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1549 enum ad77681_gpios gpio_number,
Kjansen 1:260e834a8dc1 1550 enum ad77681_gpio_output_type output_type)
Kjansen 1:260e834a8dc1 1551 {
Kjansen 1:260e834a8dc1 1552 int32_t ret;
Kjansen 1:260e834a8dc1 1553
Kjansen 1:260e834a8dc1 1554 switch (gpio_number) {
Kjansen 1:260e834a8dc1 1555 case AD77681_GPIO0: /* Set ouptut type of GPIO0 */
Kjansen 1:260e834a8dc1 1556 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1557 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1558 AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK,
Kjansen 1:260e834a8dc1 1559 AD77681_GPIO_CNTRL_GPIO0_OD_EN(output_type));
Kjansen 1:260e834a8dc1 1560 break;
Kjansen 1:260e834a8dc1 1561 case AD77681_GPIO1: /* Set ouptut type of GPIO1 */
Kjansen 1:260e834a8dc1 1562 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1563 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1564 AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK,
Kjansen 1:260e834a8dc1 1565 AD77681_GPIO_CNTRL_GPIO1_OD_EN(output_type));
Kjansen 1:260e834a8dc1 1566 break;
Kjansen 1:260e834a8dc1 1567 case AD77681_GPIO2: /* Set ouptut type of GPIO2 */
Kjansen 1:260e834a8dc1 1568 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1569 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1570 AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK,
Kjansen 1:260e834a8dc1 1571 AD77681_GPIO_CNTRL_GPIO2_OD_EN(output_type));
Kjansen 1:260e834a8dc1 1572 break;
Kjansen 1:260e834a8dc1 1573 case AD77681_ALL_GPIOS: /* Set ouptut type of all GPIOs */
Kjansen 1:260e834a8dc1 1574 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1575 AD77681_REG_GPIO_CONTROL,
Kjansen 1:260e834a8dc1 1576 AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK,
Kjansen 1:260e834a8dc1 1577 AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(output_type));
Kjansen 1:260e834a8dc1 1578 break;
Kjansen 1:260e834a8dc1 1579 default:
Kjansen 1:260e834a8dc1 1580 return FAILURE;
Kjansen 1:260e834a8dc1 1581 break;
Kjansen 1:260e834a8dc1 1582 }
Kjansen 1:260e834a8dc1 1583
Kjansen 1:260e834a8dc1 1584 return ret;
Kjansen 1:260e834a8dc1 1585 }
Kjansen 1:260e834a8dc1 1586
Kjansen 1:260e834a8dc1 1587 /**
Kjansen 1:260e834a8dc1 1588 * Clear all error flags at once
Kjansen 1:260e834a8dc1 1589 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1590 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1591 */
Kjansen 1:260e834a8dc1 1592 int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 1593 {
Kjansen 1:260e834a8dc1 1594 int32_t ret;
Kjansen 1:260e834a8dc1 1595
Kjansen 1:260e834a8dc1 1596 /* SPI ignore error CLEAR */
Kjansen 1:260e834a8dc1 1597 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1598 AD77681_REG_SPI_DIAG_STATUS,
Kjansen 1:260e834a8dc1 1599 AD77681_SPI_IGNORE_ERROR_MSK,
Kjansen 1:260e834a8dc1 1600 AD77681_SPI_IGNORE_ERROR_CLR(ENABLE));
Kjansen 1:260e834a8dc1 1601 /* SPI read error CLEAR */
Kjansen 1:260e834a8dc1 1602 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1603 AD77681_REG_SPI_DIAG_STATUS,
Kjansen 1:260e834a8dc1 1604 AD77681_SPI_READ_ERROR_MSK,
Kjansen 1:260e834a8dc1 1605 AD77681_SPI_READ_ERROR_CLR(ENABLE));
Kjansen 1:260e834a8dc1 1606 /* SPI write error CLEAR */
Kjansen 1:260e834a8dc1 1607 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1608 AD77681_REG_SPI_DIAG_STATUS,
Kjansen 1:260e834a8dc1 1609 AD77681_SPI_WRITE_ERROR_MSK,
Kjansen 1:260e834a8dc1 1610 AD77681_SPI_WRITE_ERROR_CLR(ENABLE));
Kjansen 1:260e834a8dc1 1611 /* SPI CRC error CLEAR */
Kjansen 1:260e834a8dc1 1612 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1613 AD77681_REG_SPI_DIAG_STATUS,
Kjansen 1:260e834a8dc1 1614 AD77681_SPI_CRC_ERROR_MSK,
Kjansen 1:260e834a8dc1 1615 AD77681_SPI_CRC_ERROR_CLR(ENABLE));
Kjansen 1:260e834a8dc1 1616
Kjansen 1:260e834a8dc1 1617 return ret;
Kjansen 1:260e834a8dc1 1618 }
Kjansen 1:260e834a8dc1 1619
Kjansen 1:260e834a8dc1 1620 /**
Kjansen 1:260e834a8dc1 1621 * Enabling error flags. All error flags enabled by default
Kjansen 1:260e834a8dc1 1622 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1623 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1624 */
Kjansen 1:260e834a8dc1 1625 int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Kjansen 1:260e834a8dc1 1626 {
Kjansen 1:260e834a8dc1 1627 int32_t ret;
Kjansen 1:260e834a8dc1 1628
Kjansen 1:260e834a8dc1 1629 /* SPI ERRORS ENABLE */
Kjansen 1:260e834a8dc1 1630 /* SPI ignore error enable */
Kjansen 1:260e834a8dc1 1631 ret = ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1632 AD77681_REG_SPI_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1633 AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK,
Kjansen 1:260e834a8dc1 1634 AD77681_SPI_DIAG_ERR_SPI_IGNORE(ENABLE));
Kjansen 1:260e834a8dc1 1635 /* SPI Clock count error enable */
Kjansen 1:260e834a8dc1 1636 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1637 AD77681_REG_SPI_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1638 AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK,
Kjansen 1:260e834a8dc1 1639 AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(ENABLE));
Kjansen 1:260e834a8dc1 1640 /* SPI Read error enable */
Kjansen 1:260e834a8dc1 1641 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1642 AD77681_REG_SPI_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1643 AD77681_SPI_DIAG_ERR_SPI_RD_MSK,
Kjansen 1:260e834a8dc1 1644 AD77681_SPI_DIAG_ERR_SPI_RD(ENABLE));
Kjansen 1:260e834a8dc1 1645 /* SPI Write error enable */
Kjansen 1:260e834a8dc1 1646 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1647 AD77681_REG_SPI_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1648 AD77681_SPI_DIAG_ERR_SPI_WR_MSK,
Kjansen 1:260e834a8dc1 1649 AD77681_SPI_DIAG_ERR_SPI_WR(ENABLE));
Kjansen 1:260e834a8dc1 1650
Kjansen 1:260e834a8dc1 1651 /* ADC DIAG ERRORS ENABLE */
Kjansen 1:260e834a8dc1 1652 /* DLDO PSM error enable */
Kjansen 1:260e834a8dc1 1653 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1654 AD77681_REG_ADC_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1655 AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK,
Kjansen 1:260e834a8dc1 1656 AD77681_ADC_DIAG_ERR_DLDO_PSM(ENABLE));
Kjansen 1:260e834a8dc1 1657 /* ALDO PSM error enable */
Kjansen 1:260e834a8dc1 1658 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1659 AD77681_REG_ADC_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1660 AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK,
Kjansen 1:260e834a8dc1 1661 AD77681_ADC_DIAG_ERR_ALDO_PSM(ENABLE));
Kjansen 1:260e834a8dc1 1662 /* Filter saturated error enable */
Kjansen 1:260e834a8dc1 1663 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1664 AD77681_REG_ADC_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1665 AD77681_ADC_DIAG_ERR_FILT_SAT_MSK,
Kjansen 1:260e834a8dc1 1666 AD77681_ADC_DIAG_ERR_FILT_SAT(ENABLE));
Kjansen 1:260e834a8dc1 1667 /* Filter not settled error enable */
Kjansen 1:260e834a8dc1 1668 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1669 AD77681_REG_ADC_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1670 AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK,
Kjansen 1:260e834a8dc1 1671 AD77681_ADC_DIAG_ERR_FILT_NOT_SET(ENABLE));
Kjansen 1:260e834a8dc1 1672 /* External clock check error enable */
Kjansen 1:260e834a8dc1 1673 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1674 AD77681_REG_ADC_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1675 AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK,
Kjansen 1:260e834a8dc1 1676 AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(ENABLE));
Kjansen 1:260e834a8dc1 1677
Kjansen 1:260e834a8dc1 1678 /* DIG DIAG ENABLE */
Kjansen 1:260e834a8dc1 1679 /* Memory map CRC error enabled */
Kjansen 1:260e834a8dc1 1680 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1681 AD77681_REG_DIG_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1682 AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK,
Kjansen 1:260e834a8dc1 1683 AD77681_DIG_DIAG_ERR_MEMMAP_CRC(ENABLE));
Kjansen 1:260e834a8dc1 1684 /* RAM CRC error enabled */
Kjansen 1:260e834a8dc1 1685 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1686 AD77681_REG_DIG_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1687 AD77681_DIG_DIAG_ERR_RAM_CRC_MSK,
Kjansen 1:260e834a8dc1 1688 AD77681_DIG_DIAG_ERR_RAM_CRC(ENABLE));
Kjansen 1:260e834a8dc1 1689 /* FUSE CRC error enabled */
Kjansen 1:260e834a8dc1 1690 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1691 AD77681_REG_DIG_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1692 AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK,
Kjansen 1:260e834a8dc1 1693 AD77681_DIG_DIAG_ERR_FUSE_CRC(ENABLE));
Kjansen 1:260e834a8dc1 1694 /* Enable MCLK Counter */
Kjansen 1:260e834a8dc1 1695 ret |= ad77681_spi_write_mask(dev,
Kjansen 1:260e834a8dc1 1696 AD77681_REG_DIG_DIAG_ENABLE,
Kjansen 1:260e834a8dc1 1697 AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK,
Kjansen 1:260e834a8dc1 1698 AD77681_DIG_DIAG_FREQ_COUNT_EN(ENABLE));
Kjansen 1:260e834a8dc1 1699
Kjansen 1:260e834a8dc1 1700 return ret;
Kjansen 1:260e834a8dc1 1701 }
Kjansen 1:260e834a8dc1 1702
Kjansen 1:260e834a8dc1 1703 /**
Kjansen 1:260e834a8dc1 1704 * Read from all ADC status registers
Kjansen 1:260e834a8dc1 1705 * @param dev - The device structure.
Kjansen 1:260e834a8dc1 1706 * @param status - Structure with all satuts bits
Kjansen 1:260e834a8dc1 1707 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1708 */
Kjansen 1:260e834a8dc1 1709 int32_t ad77681_status(struct ad77681_dev *dev,
Kjansen 1:260e834a8dc1 1710 struct ad77681_status_registers *status)
Kjansen 1:260e834a8dc1 1711 {
Kjansen 1:260e834a8dc1 1712 int32_t ret;
Kjansen 1:260e834a8dc1 1713 uint8_t buf[3];
Kjansen 1:260e834a8dc1 1714
Kjansen 1:260e834a8dc1 1715 /* Master status register */
Kjansen 1:260e834a8dc1 1716 ret = ad77681_spi_reg_read(dev, AD77681_REG_MASTER_STATUS,buf);
Kjansen 1:260e834a8dc1 1717 status->master_error = buf[1] & AD77681_MASTER_ERROR_MSK;
Kjansen 1:260e834a8dc1 1718 status->adc_error = buf[1] & AD77681_MASTER_ADC_ERROR_MSK;
Kjansen 1:260e834a8dc1 1719 status->dig_error = buf[1] & AD77681_MASTER_DIG_ERROR_MSK;
Kjansen 1:260e834a8dc1 1720 status->adc_err_ext_clk_qual = buf[1] & AD77681_MASTER_DIG_ERR_EXT_CLK_MSK;
Kjansen 1:260e834a8dc1 1721 status->adc_filt_saturated = buf[1] & AD77681_MASTER_FILT_SAT_MSK;
Kjansen 1:260e834a8dc1 1722 status->adc_filt_not_settled = buf[1] & AD77681_MASTER_FILT_NOT_SET_MSK;
Kjansen 1:260e834a8dc1 1723 status->spi_error = buf[1] & AD77681_MASTER_SPI_ERROR_MSK;
Kjansen 1:260e834a8dc1 1724 status->por_flag = buf[1] & AD77681_MASTER_POR_FLAG_MSK;
Kjansen 1:260e834a8dc1 1725 /* SPI diag status register */
Kjansen 1:260e834a8dc1 1726 ret |= ad77681_spi_reg_read(dev, AD77681_REG_SPI_DIAG_STATUS, buf);
Kjansen 1:260e834a8dc1 1727 status->spi_ignore = buf[1] & AD77681_SPI_IGNORE_ERROR_MSK;
Kjansen 1:260e834a8dc1 1728 status->spi_clock_count = buf[1] & AD77681_SPI_CLK_CNT_ERROR_MSK;
Kjansen 1:260e834a8dc1 1729 status->spi_read_error = buf[1] & AD77681_SPI_READ_ERROR_MSK;
Kjansen 1:260e834a8dc1 1730 status->spi_write_error = buf[1] & AD77681_SPI_WRITE_ERROR_MSK;
Kjansen 1:260e834a8dc1 1731 status->spi_crc_error = buf[1] & AD77681_SPI_CRC_ERROR_MSK;
Kjansen 1:260e834a8dc1 1732 /* ADC diag status register */
Kjansen 1:260e834a8dc1 1733 ret |= ad77681_spi_reg_read(dev, AD77681_REG_ADC_DIAG_STATUS,buf);
Kjansen 1:260e834a8dc1 1734 status->dldo_psm_error = buf[1] & AD77681_ADC_DLDO_PSM_ERROR_MSK;
Kjansen 1:260e834a8dc1 1735 status->aldo_psm_error = buf[1] & AD77681_ADC_ALDO_PSM_ERROR_MSK;
Kjansen 1:260e834a8dc1 1736 status->ref_det_error = buf[1] & AD77681_ADC_REF_DET_ERROR_MSK;
Kjansen 1:260e834a8dc1 1737 status->filt_sat_error = buf[1] & AD77681_ADC_FILT_SAT_MSK;
Kjansen 1:260e834a8dc1 1738 status->filt_not_set_error = buf[1] & AD77681_ADC_FILT_NOT_SET_MSK;
Kjansen 1:260e834a8dc1 1739 status->ext_clk_qual_error = buf[1] & AD77681_ADC_DIG_ERR_EXT_CLK_MSK;
Kjansen 1:260e834a8dc1 1740 /* DIG diag status register */
Kjansen 1:260e834a8dc1 1741 ret |= ad77681_spi_reg_read(dev, AD77681_REG_DIG_DIAG_STATUS,buf);
Kjansen 1:260e834a8dc1 1742 status->memoy_map_crc_error = buf[1] & AD77681_DIG_MEMMAP_CRC_ERROR_MSK;
Kjansen 1:260e834a8dc1 1743 status->ram_crc_error = buf[1] & AD77681_DIG_RAM_CRC_ERROR_MSK;
Kjansen 1:260e834a8dc1 1744 status->fuse_crc_error = buf[1] & AD77681_DIG_FUS_CRC_ERROR_MSK;
Kjansen 1:260e834a8dc1 1745
Kjansen 1:260e834a8dc1 1746 return ret;
Kjansen 1:260e834a8dc1 1747 }
Kjansen 1:260e834a8dc1 1748
Kjansen 1:260e834a8dc1 1749 /**
Kjansen 1:260e834a8dc1 1750 * Initialize the device.
Kjansen 1:260e834a8dc1 1751 * @param device - The device structure.
Kjansen 1:260e834a8dc1 1752 * @param init_param - The structure that contains the device initial
Kjansen 1:260e834a8dc1 1753 * parameters.
Kjansen 1:260e834a8dc1 1754 * @param status - The structure that will contains the ADC status
Kjansen 1:260e834a8dc1 1755 * @return 0 in case of success, negative error code otherwise.
Kjansen 1:260e834a8dc1 1756 */
Kjansen 1:260e834a8dc1 1757 int32_t ad77681_setup(struct ad77681_dev **device,
Kjansen 1:260e834a8dc1 1758 struct ad77681_init_param init_param,
Kjansen 1:260e834a8dc1 1759 struct ad77681_status_registers **status)
Kjansen 1:260e834a8dc1 1760 {
Kjansen 1:260e834a8dc1 1761 struct ad77681_dev *dev;
Kjansen 1:260e834a8dc1 1762 struct ad77681_status_registers *stat;
Kjansen 1:260e834a8dc1 1763 int32_t ret;
Kjansen 1:260e834a8dc1 1764 uint8_t scratchpad_check = 0xAD;
Kjansen 1:260e834a8dc1 1765
Kjansen 1:260e834a8dc1 1766 dev = (struct ad77681_dev *)malloc(sizeof(*dev));
Kjansen 1:260e834a8dc1 1767 if (!dev) {
Kjansen 1:260e834a8dc1 1768 return -1;
Kjansen 1:260e834a8dc1 1769 }
Kjansen 1:260e834a8dc1 1770
Kjansen 1:260e834a8dc1 1771 stat = (struct ad77681_status_registers *)malloc(sizeof(*stat));
Kjansen 1:260e834a8dc1 1772 if (!stat) {
Kjansen 1:260e834a8dc1 1773 free(dev);
Kjansen 1:260e834a8dc1 1774 return -1;
Kjansen 1:260e834a8dc1 1775 }
Kjansen 1:260e834a8dc1 1776
Kjansen 1:260e834a8dc1 1777 dev->power_mode = init_param.power_mode;
Kjansen 1:260e834a8dc1 1778 dev->mclk_div = init_param.mclk_div;
Kjansen 1:260e834a8dc1 1779 dev->conv_diag_sel = init_param.conv_diag_sel;
Kjansen 1:260e834a8dc1 1780 dev->conv_mode = init_param.conv_mode;
Kjansen 1:260e834a8dc1 1781 dev->diag_mux_sel = init_param.diag_mux_sel;
Kjansen 1:260e834a8dc1 1782 dev->conv_len = init_param.conv_len;
Kjansen 1:260e834a8dc1 1783 dev->crc_sel = AD77681_NO_CRC;
Kjansen 1:260e834a8dc1 1784 dev->status_bit = init_param.status_bit;
Kjansen 1:260e834a8dc1 1785 dev->VCM_out = init_param.VCM_out;
Kjansen 1:260e834a8dc1 1786 dev->AINn = init_param.AINn;
Kjansen 1:260e834a8dc1 1787 dev->AINp = init_param.AINp;
Kjansen 1:260e834a8dc1 1788 dev->REFn = init_param.REFn;
Kjansen 1:260e834a8dc1 1789 dev->REFp = init_param.REFp;
Kjansen 1:260e834a8dc1 1790 dev->filter = init_param.filter;
Kjansen 1:260e834a8dc1 1791 dev->decimate = init_param.decimate;
Kjansen 1:260e834a8dc1 1792 dev->sinc3_osr = init_param.sinc3_osr;
Kjansen 1:260e834a8dc1 1793 dev->vref = init_param.vref;
Kjansen 1:260e834a8dc1 1794 dev->mclk = init_param.mclk;
Kjansen 1:260e834a8dc1 1795 dev->sample_rate = init_param.sample_rate;
Kjansen 1:260e834a8dc1 1796 dev->data_frame_byte = init_param.data_frame_byte;
Kjansen 1:260e834a8dc1 1797
Kjansen 1:260e834a8dc1 1798 ret = spi_init(&dev->spi_desc, &init_param.spi_eng_dev_init);
Kjansen 1:260e834a8dc1 1799 if (ret < 0) {
Kjansen 1:260e834a8dc1 1800 free(dev);
Kjansen 1:260e834a8dc1 1801 free(stat);
Kjansen 1:260e834a8dc1 1802 return ret;
Kjansen 1:260e834a8dc1 1803 }
Kjansen 1:260e834a8dc1 1804
Kjansen 1:260e834a8dc1 1805 ret |= ad77681_soft_reset(dev);
Kjansen 1:260e834a8dc1 1806
Kjansen 1:260e834a8dc1 1807 udelay(200);
Kjansen 1:260e834a8dc1 1808
Kjansen 1:260e834a8dc1 1809 /* Check physical connection using scratchpad*/
Kjansen 1:260e834a8dc1 1810 if (ad77681_scratchpad(dev, &scratchpad_check) == FAILURE) {
Kjansen 1:260e834a8dc1 1811 scratchpad_check = 0xAD;/* If failure, second try */
Kjansen 1:260e834a8dc1 1812 ret |= (ad77681_scratchpad(dev, &scratchpad_check));
Kjansen 1:260e834a8dc1 1813 if(ret == FAILURE) {
Kjansen 1:260e834a8dc1 1814 free(dev);
Kjansen 1:260e834a8dc1 1815 free(stat);
Kjansen 1:260e834a8dc1 1816 return ret;
Kjansen 1:260e834a8dc1 1817 }
Kjansen 1:260e834a8dc1 1818 }
Kjansen 1:260e834a8dc1 1819 ret |= ad77681_set_power_mode(dev, dev->power_mode);
Kjansen 1:260e834a8dc1 1820 ret |= ad77681_set_mclk_div(dev, dev->mclk_div);
Kjansen 1:260e834a8dc1 1821 ret |= ad77681_set_conv_mode(dev,
Kjansen 1:260e834a8dc1 1822 dev->conv_mode,
Kjansen 1:260e834a8dc1 1823 dev->diag_mux_sel,
Kjansen 1:260e834a8dc1 1824 dev->conv_diag_sel);
Kjansen 1:260e834a8dc1 1825 ret |= ad77681_set_convlen(dev, dev->conv_len);
Kjansen 1:260e834a8dc1 1826 ret |= ad77681_set_status_bit(dev, dev->status_bit);
Kjansen 1:260e834a8dc1 1827 ret |= ad77681_set_crc_sel(dev, init_param.crc_sel);
Kjansen 1:260e834a8dc1 1828 ret |= ad77681_set_VCM_output(dev, dev->VCM_out);
Kjansen 1:260e834a8dc1 1829 ret |= ad77681_set_AINn_buffer(dev, dev->AINn);
Kjansen 1:260e834a8dc1 1830 ret |= ad77681_set_AINp_buffer(dev, dev->AINp);
Kjansen 1:260e834a8dc1 1831 ret |= ad77681_set_REFn_buffer(dev, dev->REFn);
Kjansen 1:260e834a8dc1 1832 ret |= ad77681_set_REFp_buffer(dev, dev->REFp);
Kjansen 1:260e834a8dc1 1833 ret |= ad77681_set_filter_type(dev, dev->decimate, dev->filter, dev->sinc3_osr);
Kjansen 1:260e834a8dc1 1834 ret |= ad77681_error_flags_enabe(dev);
Kjansen 1:260e834a8dc1 1835 ret |= ad77681_clear_error_flags(dev);
Kjansen 1:260e834a8dc1 1836 ret |= ad77681_status(dev, stat);
Kjansen 1:260e834a8dc1 1837 ad77681_get_frame_byte(dev);
Kjansen 1:260e834a8dc1 1838 ad77681_update_sample_rate(dev);
Kjansen 1:260e834a8dc1 1839 *status = stat;
Kjansen 1:260e834a8dc1 1840 *device = dev;
Kjansen 1:260e834a8dc1 1841
Kjansen 1:260e834a8dc1 1842 if (!ret)
Kjansen 1:260e834a8dc1 1843 printf("ad77681 successfully initialized\n");
Kjansen 1:260e834a8dc1 1844
Kjansen 1:260e834a8dc1 1845 return ret;
Kjansen 1:260e834a8dc1 1846 }
Kjansen 1:260e834a8dc1 1847