Diff: app/ad7124_support.h

Revision:

7:3e1005bd4d41

Parent:

3:779bb1e55f1a

--- a/app/ad7124_support.h	Wed Dec 02 11:23:19 2020 +0000
+++ b/app/ad7124_support.h	Tue Aug 03 12:05:42 2021 +0100
@@ -6,7 +6,7 @@
 
   @details:
  -----------------------------------------------------------------------------
- Copyright (c) 2019, 2020 Analog Devices, Inc.
+ Copyright (c) 2019-2021 Analog Devices, Inc.
  All rights reserved.
 
  This software is proprietary to Analog Devices, Inc. and its licensors.
@@ -18,6 +18,7 @@
 #define AD7124_SUPPORT_H_
 
 #include "ad7124.h"
+#include "util.h"
 
 /* PGA Gain Value */
 #define AD7124_PGA_GAIN(x) (1 << (x))
@@ -25,6 +26,37 @@
 #define AD7124_REF_VOLTAGE 2.5
 #define AD7124_ADC_N_BITS 24
 
+/* ADC_Control Register bits */
+#define AD7124_ADC_CTRL_REG_POWER_MODE_MSK    GENMASK(7,6)
+#define AD7124_ADC_CTRL_REG_POWER_MODE_RD(x)  (((x) >> 6) & 0x3)
+#define AD7124_ADC_CTRL_REG_MSK				  GENMASK(5,2)
+
+/* Channel Registers 0-15 bits */
+#define AD7124_CH_MAP_REG_CH_ENABLE_RD(x)     (((x) >> 15) & 0x1)
+#define AD7124_CH_MAP_REG_SETUP_MSK           GENMASK(14, 12)
+#define AD7124_CH_MAP_REG_SETUP_RD(x)         (((x) >> 12) & 0x7)
+#define AD7124_CH_MAP_REG_AINP_MSK            GENMASK(9, 5)
+#define AD7124_CH_MAP_REG_AINP_RD(x)          (((x) >> 5) & 0x1F)
+#define AD7124_CH_MAP_REG_AINM_MSK            GENMASK(4, 0)
+#define AD7124_CH_MAP_REG_AINM_RD(x)          (((x) >> 0) & 0x1F)
+
+/* Configuration Registers 0-7 bits */
+#define AD7124_CFG_REG_BIPOLAR_RD(x)          (((x) >> 11) & 0x1)
+#define AD7124_CFG_REG_REF_BUFP_RD(x)         (((x) >> 8) & 0x1)
+#define AD7124_CFG_REG_REF_BUFM_RD(x)         (((x) >> 7) & 0x1)
+#define AD7124_CFG_REG_AIN_BUFP_RD(x)         (((x) >> 6) & 0x1)
+#define AD7124_CFG_REG_AINM_BUFP_RD(x)        (((x) >> 5) & 0x1)
+#define AD7124_CFG_REG_REF_SEL_MSK            GENMASK(4, 3)
+#define AD7124_CFG_REG_REF_SEL_RD(x)          (((x) >> 3) & 0x3)
+#define AD7124_CFG_REG_PGA_MSK                GENMASK(2, 0)
+#define AD7124_CFG_REG_PGA_RD(x)              (((x) >> 0) & 0x7)
+
+/* Filter Register 0-7 bits */
+#define AD7124_FILT_REG_FILTER_MSK            GENMASK(23, 21)
+#define AD7124_FILT_REG_FILTER_RD(x)          (((x) >> 21) & 0x7)
+#define AD7124_FILT_REG_FS_MSK                GENMASK(10, 0)
+#define AD7124_FILT_REG_FS_RD(x)              (((x) >> 0) & 0x7FF)
+
 uint8_t ad7124_get_channel_setup(struct ad7124_dev *dev, uint8_t channel);
 uint8_t ad7124_get_channel_pga(struct ad7124_dev *dev, uint8_t channel);
 bool ad7124_get_channel_bipolar(struct ad7124_dev *dev, uint8_t channel);