Analog Devices / AD7124

Analog Devices AD7124-8 - 8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

Dependents:   CN0398 CN0391 CN0398_arduino

AD7124.h@5:5fa802deb471, 2016-11-08 (annotated)

Committer:
adisuciu
Date:
Tue Nov 08 09:41:47 2016 +0000
Revision:
5:5fa802deb471
Parent:
4:502352a643e6
Parent:
3:8478d36355fc 
Merge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
adisuciu 0:f32d3fb1d3e2 1 /**
adisuciu 0:f32d3fb1d3e2 2 * @file AD7124.h
adisuciu 0:f32d3fb1d3e2 3 * @brief Header file for AD7790 ADC
adisuciu 0:f32d3fb1d3e2 4 * @author Analog Devices Inc.
adisuciu 0:f32d3fb1d3e2 5 *
adisuciu 0:f32d3fb1d3e2 6 * For support please go to:
adisuciu 0:f32d3fb1d3e2 7 * Github: https://github.com/analogdevicesinc/mbed-adi
adisuciu 0:f32d3fb1d3e2 8 * Support: https://ez.analog.com/community/linux-device-drivers/microcontroller-no-os-drivers
adisuciu 0:f32d3fb1d3e2 9 * Product: http://www.analog.com/AD7124
adisuciu 0:f32d3fb1d3e2 10 * More: https://wiki.analog.com/resources/tools-software/mbed-drivers-all
adisuciu 0:f32d3fb1d3e2 11
adisuciu 0:f32d3fb1d3e2 12 ********************************************************************************
adisuciu 0:f32d3fb1d3e2 13 * Copyright 2016(c) Analog Devices, Inc.
adisuciu 0:f32d3fb1d3e2 14 *
adisuciu 0:f32d3fb1d3e2 15 * All rights reserved.
adisuciu 0:f32d3fb1d3e2 16 *
adisuciu 0:f32d3fb1d3e2 17 * Redistribution and use in source and binary forms, with or without
adisuciu 0:f32d3fb1d3e2 18 * modification, are permitted provided that the following conditions are met:
adisuciu 0:f32d3fb1d3e2 19 * - Redistributions of source code must retain the above copyright
adisuciu 0:f32d3fb1d3e2 20 * notice, this list of conditions and the following disclaimer.
adisuciu 0:f32d3fb1d3e2 21 * - Redistributions in binary form must reproduce the above copyright
adisuciu 0:f32d3fb1d3e2 22 * notice, this list of conditions and the following disclaimer in
adisuciu 0:f32d3fb1d3e2 23 * the documentation and/or other materials provided with the
adisuciu 0:f32d3fb1d3e2 24 * distribution.
adisuciu 0:f32d3fb1d3e2 25 * - Neither the name of Analog Devices, Inc. nor the names of its
adisuciu 0:f32d3fb1d3e2 26 * contributors may be used to endorse or promote products derived
adisuciu 0:f32d3fb1d3e2 27 * from this software without specific prior written permission.
adisuciu 0:f32d3fb1d3e2 28 * - The use of this software may or may not infringe the patent rights
adisuciu 0:f32d3fb1d3e2 29 * of one or more patent holders. This license does not release you
adisuciu 0:f32d3fb1d3e2 30 * from the requirement that you obtain separate licenses from these
adisuciu 0:f32d3fb1d3e2 31 * patent holders to use this software.
adisuciu 0:f32d3fb1d3e2 32 * - Use of the software either in source or binary form, must be run
adisuciu 0:f32d3fb1d3e2 33 * on or directly connected to an Analog Devices Inc. component.
adisuciu 0:f32d3fb1d3e2 34 *
adisuciu 0:f32d3fb1d3e2 35 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
adisuciu 0:f32d3fb1d3e2 36 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
adisuciu 0:f32d3fb1d3e2 37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
adisuciu 0:f32d3fb1d3e2 38 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
adisuciu 0:f32d3fb1d3e2 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
adisuciu 0:f32d3fb1d3e2 40 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
adisuciu 0:f32d3fb1d3e2 41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
adisuciu 0:f32d3fb1d3e2 42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
adisuciu 0:f32d3fb1d3e2 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
adisuciu 0:f32d3fb1d3e2 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
adisuciu 0:f32d3fb1d3e2 45 *
adisuciu 0:f32d3fb1d3e2 46 ********************************************************************************/
adisuciu 0:f32d3fb1d3e2 47
adisuciu 0:f32d3fb1d3e2 48 #ifndef AD7790_H
adisuciu 0:f32d3fb1d3e2 49 #define AD7790_H
adisuciu 0:f32d3fb1d3e2 50
adisuciu 0:f32d3fb1d3e2 51 #include "mbed.h"
adisuciu 0:f32d3fb1d3e2 52
adisuciu 0:f32d3fb1d3e2 53 /**
adisuciu 0:f32d3fb1d3e2 54 * Comment this line if you want to turn off the debug mode.
adisuciu 0:f32d3fb1d3e2 55 * The debug mode will send a message if an exception occurs within AD7790 driver
adisuciu 0:f32d3fb1d3e2 56 */
adisuciu 0:f32d3fb1d3e2 57
adisuciu 0:f32d3fb1d3e2 58 #define AD7124_DEBUG_MODE
adisuciu 0:f32d3fb1d3e2 59
adisuciu 0:f32d3fb1d3e2 60 /**
adisuciu 0:f32d3fb1d3e2 61 * @brief Analog Devices AD7790 SPI 16-bit Buffered Sigma-Delta ADC
adisuciu 0:f32d3fb1d3e2 62 */
adisuciu 4:502352a643e6 63
adisuciu 4:502352a643e6 64
adisuciu 0:f32d3fb1d3e2 65 class AD7124
adisuciu 0:f32d3fb1d3e2 66 {
adisuciu 0:f32d3fb1d3e2 67 public:
adisuciu 0:f32d3fb1d3e2 68 enum ad7124_registers {
adisuciu 0:f32d3fb1d3e2 69 AD7124_Status = 0x00,
adisuciu 0:f32d3fb1d3e2 70 AD7124_ADC_Control,
adisuciu 0:f32d3fb1d3e2 71 AD7124_Data,
adisuciu 0:f32d3fb1d3e2 72 AD7124_IOCon1,
adisuciu 0:f32d3fb1d3e2 73 AD7124_IOCon2,
adisuciu 0:f32d3fb1d3e2 74 AD7124_ID,
adisuciu 0:f32d3fb1d3e2 75 AD7124_Error,
adisuciu 0:f32d3fb1d3e2 76 AD7124_Error_En,
adisuciu 0:f32d3fb1d3e2 77 AD7124_Mclk_Count,
adisuciu 0:f32d3fb1d3e2 78 AD7124_Channel_0,
adisuciu 0:f32d3fb1d3e2 79 AD7124_Channel_1,
adisuciu 0:f32d3fb1d3e2 80 AD7124_Channel_2,
adisuciu 0:f32d3fb1d3e2 81 AD7124_Channel_3,
adisuciu 0:f32d3fb1d3e2 82 AD7124_Channel_4,
adisuciu 0:f32d3fb1d3e2 83 AD7124_Channel_5,
adisuciu 0:f32d3fb1d3e2 84 AD7124_Channel_6,
adisuciu 0:f32d3fb1d3e2 85 AD7124_Channel_7,
adisuciu 0:f32d3fb1d3e2 86 AD7124_Channel_8,
adisuciu 0:f32d3fb1d3e2 87 AD7124_Channel_9,
adisuciu 0:f32d3fb1d3e2 88 AD7124_Channel_10,
adisuciu 0:f32d3fb1d3e2 89 AD7124_Channel_11,
adisuciu 0:f32d3fb1d3e2 90 AD7124_Channel_12,
adisuciu 0:f32d3fb1d3e2 91 AD7124_Channel_13,
adisuciu 0:f32d3fb1d3e2 92 AD7124_Channel_14,
adisuciu 0:f32d3fb1d3e2 93 AD7124_Channel_15,
adisuciu 0:f32d3fb1d3e2 94 AD7124_Config_0,
adisuciu 0:f32d3fb1d3e2 95 AD7124_Config_1,
adisuciu 0:f32d3fb1d3e2 96 AD7124_Config_2,
adisuciu 0:f32d3fb1d3e2 97 AD7124_Config_3,
adisuciu 0:f32d3fb1d3e2 98 AD7124_Config_4,
adisuciu 0:f32d3fb1d3e2 99 AD7124_Config_5,
adisuciu 0:f32d3fb1d3e2 100 AD7124_Config_6,
adisuciu 0:f32d3fb1d3e2 101 AD7124_Config_7,
adisuciu 0:f32d3fb1d3e2 102 AD7124_Filter_0,
adisuciu 0:f32d3fb1d3e2 103 AD7124_Filter_1,
adisuciu 0:f32d3fb1d3e2 104 AD7124_Filter_2,
adisuciu 0:f32d3fb1d3e2 105 AD7124_Filter_3,
adisuciu 0:f32d3fb1d3e2 106 AD7124_Filter_4,
adisuciu 0:f32d3fb1d3e2 107 AD7124_Filter_5,
adisuciu 0:f32d3fb1d3e2 108 AD7124_Filter_6,
adisuciu 0:f32d3fb1d3e2 109 AD7124_Filter_7,
adisuciu 0:f32d3fb1d3e2 110 AD7124_Offset_0,
adisuciu 0:f32d3fb1d3e2 111 AD7124_Offset_1,
adisuciu 0:f32d3fb1d3e2 112 AD7124_Offset_2,
adisuciu 0:f32d3fb1d3e2 113 AD7124_Offset_3,
adisuciu 0:f32d3fb1d3e2 114 AD7124_Offset_4,
adisuciu 0:f32d3fb1d3e2 115 AD7124_Offset_5,
adisuciu 0:f32d3fb1d3e2 116 AD7124_Offset_6,
adisuciu 0:f32d3fb1d3e2 117 AD7124_Offset_7,
adisuciu 0:f32d3fb1d3e2 118 AD7124_Gain_0,
adisuciu 0:f32d3fb1d3e2 119 AD7124_Gain_1,
adisuciu 0:f32d3fb1d3e2 120 AD7124_Gain_2,
adisuciu 0:f32d3fb1d3e2 121 AD7124_Gain_3,
adisuciu 0:f32d3fb1d3e2 122 AD7124_Gain_4,
adisuciu 0:f32d3fb1d3e2 123 AD7124_Gain_5,
adisuciu 0:f32d3fb1d3e2 124 AD7124_Gain_6,
adisuciu 0:f32d3fb1d3e2 125 AD7124_Gain_7,
adisuciu 0:f32d3fb1d3e2 126 AD7124_REG_NO
adisuciu 0:f32d3fb1d3e2 127 };
adisuciu 1:4a4194a5a8ed 128
adisuciu 4:502352a643e6 129 /*! Device register info */
adisuciu 4:502352a643e6 130
adisuciu 4:502352a643e6 131
adisuciu 0:f32d3fb1d3e2 132 typedef struct _ad7124_st_reg {
adisuciu 0:f32d3fb1d3e2 133 int32_t addr;
adisuciu 0:f32d3fb1d3e2 134 int32_t value;
adisuciu 0:f32d3fb1d3e2 135 int32_t size;
adisuciu 0:f32d3fb1d3e2 136 int32_t rw;
adisuciu 0:f32d3fb1d3e2 137 } ad7124_st_reg;
adisuciu 0:f32d3fb1d3e2 138 /*! Array holding the info for the ad7124 registers - address, initial value,
adisuciu 0:f32d3fb1d3e2 139 size and access type. */
adisuciu 1:4a4194a5a8ed 140 ad7124_st_reg ad7124_regs[57];
adisuciu 1:4a4194a5a8ed 141
adisuciu 1:4a4194a5a8ed 142 private:
adisuciu 1:4a4194a5a8ed 143 enum {
adisuciu 1:4a4194a5a8ed 144 AD7124_RW = 1, /* Read and Write */
adisuciu 1:4a4194a5a8ed 145 AD7124_R = 2, /* Read only */
adisuciu 1:4a4194a5a8ed 146 AD7124_W = 3, /* Write only */
adisuciu 1:4a4194a5a8ed 147 } ad7124_reg_access;
adisuciu 1:4a4194a5a8ed 148
adisuciu 1:4a4194a5a8ed 149
adisuciu 0:f32d3fb1d3e2 150
adisuciu 0:f32d3fb1d3e2 151
adisuciu 0:f32d3fb1d3e2 152 /* AD7124 Register Map */
adisuciu 0:f32d3fb1d3e2 153 enum AD7124_reg_map {
adisuciu 0:f32d3fb1d3e2 154 COMM_REG = 0x00,
adisuciu 0:f32d3fb1d3e2 155 STATUS_REG = 0x00,
adisuciu 0:f32d3fb1d3e2 156 ADC_CTRL_REG = 0x01,
adisuciu 0:f32d3fb1d3e2 157 DATA_REG = 0x02,
adisuciu 0:f32d3fb1d3e2 158 IO_CTRL1_REG = 0x03,
adisuciu 0:f32d3fb1d3e2 159 IO_CTRL2_REG = 0x04,
adisuciu 0:f32d3fb1d3e2 160 ID_REG = 0x05,
adisuciu 0:f32d3fb1d3e2 161 ERR_REG = 0x06,
adisuciu 0:f32d3fb1d3e2 162 ERREN_REG = 0x07,
adisuciu 0:f32d3fb1d3e2 163 CH0_MAP_REG = 0x09,
adisuciu 0:f32d3fb1d3e2 164 CH1_MAP_REG = 0x0A,
adisuciu 0:f32d3fb1d3e2 165 CH2_MAP_REG = 0x0B,
adisuciu 0:f32d3fb1d3e2 166 CH3_MAP_REG = 0x0C,
adisuciu 0:f32d3fb1d3e2 167 CH4_MAP_REG = 0x0D,
adisuciu 0:f32d3fb1d3e2 168 CH5_MAP_REG = 0x0E,
adisuciu 0:f32d3fb1d3e2 169 CH6_MAP_REG = 0x0F,
adisuciu 0:f32d3fb1d3e2 170 CH7_MAP_REG = 0x10,
adisuciu 0:f32d3fb1d3e2 171 CH8_MAP_REG = 0x11,
adisuciu 0:f32d3fb1d3e2 172 CH9_MAP_REG = 0x12,
adisuciu 0:f32d3fb1d3e2 173 CH10_MAP_REG = 0x13,
adisuciu 0:f32d3fb1d3e2 174 CH11_MAP_REG = 0x14,
adisuciu 0:f32d3fb1d3e2 175 CH12_MAP_REG = 0x15,
adisuciu 0:f32d3fb1d3e2 176 CH13_MAP_REG = 0x16,
adisuciu 0:f32d3fb1d3e2 177 CH14_MAP_REG = 0x17,
adisuciu 0:f32d3fb1d3e2 178 CH15_MAP_REG = 0x18,
adisuciu 0:f32d3fb1d3e2 179 CFG0_REG = 0x19,
adisuciu 0:f32d3fb1d3e2 180 CFG1_REG = 0x1A,
adisuciu 0:f32d3fb1d3e2 181 CFG2_REG = 0x1B,
adisuciu 0:f32d3fb1d3e2 182 CFG3_REG = 0x1C,
adisuciu 0:f32d3fb1d3e2 183 CFG4_REG = 0x1D,
adisuciu 0:f32d3fb1d3e2 184 CFG5_REG = 0x1E,
adisuciu 0:f32d3fb1d3e2 185 CFG6_REG = 0x1F,
adisuciu 0:f32d3fb1d3e2 186 CFG7_REG = 0x20,
adisuciu 0:f32d3fb1d3e2 187 FILT0_REG = 0x21,
adisuciu 0:f32d3fb1d3e2 188 FILT1_REG = 0x22,
adisuciu 0:f32d3fb1d3e2 189 FILT2_REG = 0x23,
adisuciu 0:f32d3fb1d3e2 190 FILT3_REG = 0x24,
adisuciu 0:f32d3fb1d3e2 191 FILT4_REG = 0x25,
adisuciu 0:f32d3fb1d3e2 192 FILT5_REG = 0x26,
adisuciu 0:f32d3fb1d3e2 193 FILT6_REG = 0x27,
adisuciu 0:f32d3fb1d3e2 194 FILT7_REG = 0x28,
adisuciu 0:f32d3fb1d3e2 195 OFFS0_REG = 0x29,
adisuciu 0:f32d3fb1d3e2 196 OFFS1_REG = 0x2A,
adisuciu 0:f32d3fb1d3e2 197 OFFS2_REG = 0x2B,
adisuciu 0:f32d3fb1d3e2 198 OFFS3_REG = 0x2C,
adisuciu 0:f32d3fb1d3e2 199 OFFS4_REG = 0x2D,
adisuciu 0:f32d3fb1d3e2 200 OFFS5_REG = 0x2E,
adisuciu 0:f32d3fb1d3e2 201 OFFS6_REG = 0x2F,
adisuciu 0:f32d3fb1d3e2 202 OFFS7_REG = 0x30,
adisuciu 0:f32d3fb1d3e2 203 GAIN0_REG = 0x31,
adisuciu 0:f32d3fb1d3e2 204 GAIN1_REG = 0x32,
adisuciu 0:f32d3fb1d3e2 205 GAIN2_REG = 0x33,
adisuciu 0:f32d3fb1d3e2 206 GAIN3_REG = 0x34,
adisuciu 0:f32d3fb1d3e2 207 GAIN4_REG = 0x35,
adisuciu 0:f32d3fb1d3e2 208 GAIN5_REG = 0x36,
adisuciu 0:f32d3fb1d3e2 209 GAIN6_REG = 0x37,
adisuciu 0:f32d3fb1d3e2 210 GAIN7_REG = 0x38,
adisuciu 0:f32d3fb1d3e2 211 };
adisuciu 0:f32d3fb1d3e2 212
adisuciu 0:f32d3fb1d3e2 213 /* Communication Register bits */
adisuciu 0:f32d3fb1d3e2 214 #define AD7124_COMM_REG_WEN (0 << 7)
adisuciu 0:f32d3fb1d3e2 215 #define AD7124_COMM_REG_WR (0 << 6)
adisuciu 0:f32d3fb1d3e2 216 #define AD7124_COMM_REG_RD (1 << 6)
adisuciu 0:f32d3fb1d3e2 217 #define AD7124_COMM_REG_RA(x) ((x) & 0x3F)
adisuciu 0:f32d3fb1d3e2 218
adisuciu 0:f32d3fb1d3e2 219 /* Status Register bits */
adisuciu 0:f32d3fb1d3e2 220 #define AD7124_STATUS_REG_RDY (1 << 7)
adisuciu 0:f32d3fb1d3e2 221 #define AD7124_STATUS_REG_ERROR_FLAG (1 << 6)
adisuciu 0:f32d3fb1d3e2 222 #define AD7124_STATUS_REG_POR_FLAG (1 << 4)
adisuciu 0:f32d3fb1d3e2 223 #define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF)
adisuciu 0:f32d3fb1d3e2 224
adisuciu 0:f32d3fb1d3e2 225 /* ADC_Control Register bits */
adisuciu 0:f32d3fb1d3e2 226 #define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL (1 << 12)
adisuciu 0:f32d3fb1d3e2 227 #define AD7124_ADC_CTRL_REG_CONT_READ (1 << 11)
adisuciu 0:f32d3fb1d3e2 228 #define AD7124_ADC_CTRL_REG_DATA_STATUS (1 << 10)
adisuciu 0:f32d3fb1d3e2 229 #define AD7124_ADC_CTRL_REG_CS_EN (1 << 9)
adisuciu 0:f32d3fb1d3e2 230 #define AD7124_ADC_CTRL_REG_REF_EN (1 << 8)
adisuciu 0:f32d3fb1d3e2 231 #define AD7124_ADC_CTRL_REG_POWER_MODE(x) (((x) & 0x3) << 6)
adisuciu 0:f32d3fb1d3e2 232 #define AD7124_ADC_CTRL_REG_MODE(x) (((x) & 0xF) << 2)
adisuciu 0:f32d3fb1d3e2 233 #define AD7124_ADC_CTRL_REG_CLK_SEL(x) (((x) & 0x3) << 0)
adisuciu 0:f32d3fb1d3e2 234
adisuciu 0:f32d3fb1d3e2 235 /* IO_Control_1 Register bits */
adisuciu 0:f32d3fb1d3e2 236 #define AD7124_IO_CTRL1_REG_GPIO_DAT2 (1 << 23)
adisuciu 0:f32d3fb1d3e2 237 #define AD7124_IO_CTRL1_REG_GPIO_DAT1 (1 << 22)
adisuciu 0:f32d3fb1d3e2 238 #define AD7124_IO_CTRL1_REG_GPIO_CTRL2 (1 << 19)
adisuciu 0:f32d3fb1d3e2 239 #define AD7124_IO_CTRL1_REG_GPIO_CTRL1 (1 << 18)
adisuciu 0:f32d3fb1d3e2 240 #define AD7124_IO_CTRL1_REG_PDSW (1 << 15)
adisuciu 0:f32d3fb1d3e2 241 #define AD7124_IO_CTRL1_REG_IOUT1(x) (((x) & 0x7) << 11)
adisuciu 0:f32d3fb1d3e2 242 #define AD7124_IO_CTRL1_REG_IOUT0(x) (((x) & 0x7) << 8)
adisuciu 0:f32d3fb1d3e2 243 #define AD7124_IO_CTRL1_REG_IOUT_CH1(x) (((x) & 0xF) << 4)
adisuciu 0:f32d3fb1d3e2 244 #define AD7124_IO_CTRL1_REG_IOUT_CH0(x) (((x) & 0xF) << 0)
adisuciu 0:f32d3fb1d3e2 245
adisuciu 0:f32d3fb1d3e2 246 /*IO_Control_1 AD7124-8 specific bits */
adisuciu 0:f32d3fb1d3e2 247 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 (1 << 23)
adisuciu 0:f32d3fb1d3e2 248 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT3 (1 << 22)
adisuciu 0:f32d3fb1d3e2 249 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT2 (1 << 21)
adisuciu 0:f32d3fb1d3e2 250 #define AD7124_8_IO_CTRL1_REG_GPIO_DAT1 (1 << 20)
adisuciu 0:f32d3fb1d3e2 251 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4 (1 << 19)
adisuciu 0:f32d3fb1d3e2 252 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3 (1 << 18)
adisuciu 0:f32d3fb1d3e2 253 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2 (1 << 17)
adisuciu 0:f32d3fb1d3e2 254 #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1 (1 << 16)
adisuciu 0:f32d3fb1d3e2 255
adisuciu 0:f32d3fb1d3e2 256 /* IO_Control_2 Register bits */
adisuciu 0:f32d3fb1d3e2 257 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 15)
adisuciu 0:f32d3fb1d3e2 258 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 14)
adisuciu 0:f32d3fb1d3e2 259 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 11)
adisuciu 0:f32d3fb1d3e2 260 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 10)
adisuciu 0:f32d3fb1d3e2 261 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 5)
adisuciu 0:f32d3fb1d3e2 262 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 4)
adisuciu 0:f32d3fb1d3e2 263 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
adisuciu 0:f32d3fb1d3e2 264 #define AD7124_IO_CTRL2_REG_GPIO_VBIAS0 (1)
adisuciu 0:f32d3fb1d3e2 265
adisuciu 0:f32d3fb1d3e2 266 /*IO_Control_2 AD7124-8 specific bits */
adisuciu 0:f32d3fb1d3e2 267 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15 (1 << 15)
adisuciu 0:f32d3fb1d3e2 268 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14 (1 << 14)
adisuciu 0:f32d3fb1d3e2 269 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13 (1 << 13)
adisuciu 0:f32d3fb1d3e2 270 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12 (1 << 12)
adisuciu 0:f32d3fb1d3e2 271 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11 (1 << 11)
adisuciu 0:f32d3fb1d3e2 272 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10 (1 << 10)
adisuciu 0:f32d3fb1d3e2 273 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9 (1 << 9)
adisuciu 0:f32d3fb1d3e2 274 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8 (1 << 8)
adisuciu 0:f32d3fb1d3e2 275 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 7)
adisuciu 0:f32d3fb1d3e2 276 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 6)
adisuciu 0:f32d3fb1d3e2 277 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 5)
adisuciu 0:f32d3fb1d3e2 278 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 4)
adisuciu 0:f32d3fb1d3e2 279 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 3)
adisuciu 0:f32d3fb1d3e2 280 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 2)
adisuciu 0:f32d3fb1d3e2 281 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
adisuciu 0:f32d3fb1d3e2 282 #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0)
adisuciu 0:f32d3fb1d3e2 283
adisuciu 0:f32d3fb1d3e2 284 /* ID Register bits */
adisuciu 0:f32d3fb1d3e2 285 #define AD7124_ID_REG_DEVICE_ID(x) (((x) & 0xF) << 4)
adisuciu 0:f32d3fb1d3e2 286 #define AD7124_ID_REG_SILICON_REV(x) (((x) & 0xF) << 0)
adisuciu 0:f32d3fb1d3e2 287
adisuciu 0:f32d3fb1d3e2 288 /* Error Register bits */
adisuciu 0:f32d3fb1d3e2 289 #define AD7124_ERR_REG_LDO_CAP_ERR (1 << 19)
adisuciu 0:f32d3fb1d3e2 290 #define AD7124_ERR_REG_ADC_CAL_ERR (1 << 18)
adisuciu 0:f32d3fb1d3e2 291 #define AD7124_ERR_REG_ADC_CONV_ERR (1 << 17)
adisuciu 0:f32d3fb1d3e2 292 #define AD7124_ERR_REG_ADC_SAT_ERR (1 << 16)
adisuciu 0:f32d3fb1d3e2 293 #define AD7124_ERR_REG_AINP_OV_ERR (1 << 15)
adisuciu 0:f32d3fb1d3e2 294 #define AD7124_ERR_REG_AINP_UV_ERR (1 << 14)
adisuciu 0:f32d3fb1d3e2 295 #define AD7124_ERR_REG_AINM_OV_ERR (1 << 13)
adisuciu 0:f32d3fb1d3e2 296 #define AD7124_ERR_REG_AINM_UV_ERR (1 << 12)
adisuciu 0:f32d3fb1d3e2 297 #define AD7124_ERR_REG_REF_DET_ERR (1 << 11)
adisuciu 0:f32d3fb1d3e2 298 #define AD7124_ERR_REG_DLDO_PSM_ERR (1 << 9)
adisuciu 0:f32d3fb1d3e2 299 #define AD7124_ERR_REG_ALDO_PSM_ERR (1 << 7)
adisuciu 0:f32d3fb1d3e2 300 #define AD7124_ERR_REG_SPI_IGNORE_ERR (1 << 6)
adisuciu 0:f32d3fb1d3e2 301 #define AD7124_ERR_REG_SPI_SLCK_CNT_ERR (1 << 5)
adisuciu 0:f32d3fb1d3e2 302 #define AD7124_ERR_REG_SPI_READ_ERR (1 << 4)
adisuciu 0:f32d3fb1d3e2 303 #define AD7124_ERR_REG_SPI_WRITE_ERR (1 << 3)
adisuciu 0:f32d3fb1d3e2 304 #define AD7124_ERR_REG_SPI_CRC_ERR (1 << 2)
adisuciu 0:f32d3fb1d3e2 305 #define AD7124_ERR_REG_MM_CRC_ERR (1 << 1)
adisuciu 0:f32d3fb1d3e2 306
adisuciu 0:f32d3fb1d3e2 307 /* Error_En Register bits */
adisuciu 0:f32d3fb1d3e2 308 #define AD7124_ERREN_REG_MCLK_CNT_EN (1 << 22)
adisuciu 0:f32d3fb1d3e2 309 #define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN (1 << 21)
adisuciu 0:f32d3fb1d3e2 310 #define AD7124_ERREN_REG_LDO_CAP_CHK(x) (((x) & 0x3) << 19)
adisuciu 0:f32d3fb1d3e2 311 #define AD7124_ERREN_REG_ADC_CAL_ERR_EN (1 << 18)
adisuciu 0:f32d3fb1d3e2 312 #define AD7124_ERREN_REG_ADC_CONV_ERR_EN (1 << 17)
adisuciu 0:f32d3fb1d3e2 313 #define AD7124_ERREN_REG_ADC_SAT_ERR_EN (1 << 16)
adisuciu 0:f32d3fb1d3e2 314 #define AD7124_ERREN_REG_AINP_OV_ERR_EN (1 << 15)
adisuciu 0:f32d3fb1d3e2 315 #define AD7124_ERREN_REG_AINP_UV_ERR_EN (1 << 14)
adisuciu 0:f32d3fb1d3e2 316 #define AD7124_ERREN_REG_AINM_OV_ERR_EN (1 << 13)
adisuciu 0:f32d3fb1d3e2 317 #define AD7124_ERREN_REG_AINM_UV_ERR_EN (1 << 12)
adisuciu 0:f32d3fb1d3e2 318 #define AD7124_ERREN_REG_REF_DET_ERR_EN (1 << 11)
adisuciu 0:f32d3fb1d3e2 319 #define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN (1 << 10)
adisuciu 0:f32d3fb1d3e2 320 #define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR (1 << 9)
adisuciu 0:f32d3fb1d3e2 321 #define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN (1 << 8)
adisuciu 0:f32d3fb1d3e2 322 #define AD7124_ERREN_REG_ALDO_PSM_ERR_EN (1 << 7)
adisuciu 0:f32d3fb1d3e2 323 #define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN (1 << 6)
adisuciu 0:f32d3fb1d3e2 324 #define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN (1 << 5)
adisuciu 0:f32d3fb1d3e2 325 #define AD7124_ERREN_REG_SPI_READ_ERR_EN (1 << 4)
adisuciu 0:f32d3fb1d3e2 326 #define AD7124_ERREN_REG_SPI_WRITE_ERR_EN (1 << 3)
adisuciu 0:f32d3fb1d3e2 327 #define AD7124_ERREN_REG_SPI_CRC_ERR_EN (1 << 2)
adisuciu 0:f32d3fb1d3e2 328 #define AD7124_ERREN_REG_MM_CRC_ERR_EN (1 << 1)
adisuciu 0:f32d3fb1d3e2 329
adisuciu 0:f32d3fb1d3e2 330 /* Channel Registers 0-15 bits */
adisuciu 0:f32d3fb1d3e2 331 #define AD7124_CH_MAP_REG_CH_ENABLE (1 << 15)
adisuciu 0:f32d3fb1d3e2 332 #define AD7124_CH_MAP_REG_SETUP(x) (((x) & 0x7) << 12)
adisuciu 0:f32d3fb1d3e2 333 #define AD7124_CH_MAP_REG_AINP(x) (((x) & 0x1F) << 5)
adisuciu 0:f32d3fb1d3e2 334 #define AD7124_CH_MAP_REG_AINM(x) (((x) & 0x1F) << 0)
adisuciu 0:f32d3fb1d3e2 335
adisuciu 0:f32d3fb1d3e2 336 /* Configuration Registers 0-7 bits */
adisuciu 0:f32d3fb1d3e2 337 #define AD7124_CFG_REG_BIPOLAR (1 << 11)
adisuciu 0:f32d3fb1d3e2 338 #define AD7124_CFG_REG_BURNOUT(x) (((x) & 0x3) << 9)
adisuciu 0:f32d3fb1d3e2 339 #define AD7124_CFG_REG_REF_BUFP (1 << 8)
adisuciu 0:f32d3fb1d3e2 340 #define AD7124_CFG_REG_REF_BUFM (1 << 7)
adisuciu 0:f32d3fb1d3e2 341 #define AD7124_CFG_REG_AIN_BUFP (1 << 6)
adisuciu 0:f32d3fb1d3e2 342 #define AD7124_CFG_REG_AINN_BUFM (1 << 5)
adisuciu 0:f32d3fb1d3e2 343 #define AD7124_CFG_REG_REF_SEL(x) ((x) & 0x3) << 3
adisuciu 0:f32d3fb1d3e2 344 #define AD7124_CFG_REG_PGA(x) (((x) & 0x7) << 0)
adisuciu 0:f32d3fb1d3e2 345
adisuciu 0:f32d3fb1d3e2 346 /* Filter Register 0-7 bits */
adisuciu 0:f32d3fb1d3e2 347 #define AD7124_FILT_REG_FILTER(x) ((uint32_t)((x) & 0x7) << 21)
adisuciu 0:f32d3fb1d3e2 348 #define AD7124_FILT_REG_REJ60 ((uint32_t)1 << 20)
adisuciu 0:f32d3fb1d3e2 349 #define AD7124_FILT_REG_POST_FILTER(x) ((uint32_t)((x) & 0x7) << 17)
adisuciu 0:f32d3fb1d3e2 350 #define AD7124_FILT_REG_SINGLE_CYCLE ((uint32_t)1 << 16)
adisuciu 0:f32d3fb1d3e2 351 #define AD7124_FILT_REG_FS(x) ((uint32_t)((x) & 0x7FF) << 0)
adisuciu 0:f32d3fb1d3e2 352
adisuciu 0:f32d3fb1d3e2 353 public:
adisuciu 0:f32d3fb1d3e2 354
adisuciu 0:f32d3fb1d3e2 355 /** SPI configuration & constructor */
adisuciu 0:f32d3fb1d3e2 356 AD7124( PinName CS = SPI_CS, PinName MOSI = SPI_MOSI, PinName MISO = SPI_MISO, PinName SCK = SPI_SCK);
adisuciu 0:f32d3fb1d3e2 357 void frequency(int hz);
adisuciu 0:f32d3fb1d3e2 358
adisuciu 0:f32d3fb1d3e2 359 /** Low level SPI bus comm methods */
adisuciu 0:f32d3fb1d3e2 360 void reset(void);
adisuciu 0:f32d3fb1d3e2 361
adisuciu 0:f32d3fb1d3e2 362 void write_reg(uint8_t regAddress, uint8_t regValue);
adisuciu 0:f32d3fb1d3e2 363 uint16_t write_spi(uint16_t data);
adisuciu 0:f32d3fb1d3e2 364 uint16_t read_reg (uint8_t regAddress);
adisuciu 0:f32d3fb1d3e2 365 bool get_miso();
adisuciu 0:f32d3fb1d3e2 366
adisuciu 0:f32d3fb1d3e2 367
adisuciu 0:f32d3fb1d3e2 368 int32_t Reset();
adisuciu 0:f32d3fb1d3e2 369 /* Reads and returns the value of a device register. */
adisuciu 0:f32d3fb1d3e2 370 uint32_t ReadDeviceRegister(enum ad7124_registers reg);
adisuciu 0:f32d3fb1d3e2 371
adisuciu 0:f32d3fb1d3e2 372 /* Writes the specified value to a device register. */
adisuciu 0:f32d3fb1d3e2 373 int32_t WriteDeviceRegister(enum ad7124_registers reg, uint32_t value);
adisuciu 0:f32d3fb1d3e2 374
adisuciu 0:f32d3fb1d3e2 375 /*! Reads the value of the specified register. */
adisuciu 0:f32d3fb1d3e2 376 int32_t ReadRegister(ad7124_st_reg* pReg);
adisuciu 0:f32d3fb1d3e2 377
adisuciu 0:f32d3fb1d3e2 378 /*! Writes the value of the specified register. */
adisuciu 0:f32d3fb1d3e2 379 int32_t WriteRegister(ad7124_st_reg reg);
adisuciu 0:f32d3fb1d3e2 380
adisuciu 0:f32d3fb1d3e2 381 /*! Reads the value of the specified register without a device state check. */
adisuciu 0:f32d3fb1d3e2 382 int32_t NoCheckReadRegister(ad7124_st_reg* pReg);
adisuciu 0:f32d3fb1d3e2 383
adisuciu 0:f32d3fb1d3e2 384 /*! Writes the value of the specified register without a device state check. */
adisuciu 0:f32d3fb1d3e2 385 int32_t NoCheckWriteRegister(ad7124_st_reg reg);
adisuciu 0:f32d3fb1d3e2 386
adisuciu 0:f32d3fb1d3e2 387 /*! Waits until the device can accept read and write user actions. */
adisuciu 0:f32d3fb1d3e2 388 int32_t WaitForSpiReady(uint32_t timeout);
adisuciu 0:f32d3fb1d3e2 389
adisuciu 0:f32d3fb1d3e2 390 /*! Waits until a new conversion result is available. */
adisuciu 0:f32d3fb1d3e2 391 int32_t WaitForConvReady(uint32_t timeout);
adisuciu 0:f32d3fb1d3e2 392
adisuciu 0:f32d3fb1d3e2 393 /*! Reads the conversion result from the device. */
adisuciu 0:f32d3fb1d3e2 394 int32_t ReadData(int32_t* pData);
adisuciu 0:f32d3fb1d3e2 395
adisuciu 0:f32d3fb1d3e2 396 /*! Computes the CRC checksum for a data buffer. */
adisuciu 0:f32d3fb1d3e2 397 uint8_t ComputeCRC8(uint8_t* pBuf, uint8_t bufSize);
adisuciu 0:f32d3fb1d3e2 398
adisuciu 0:f32d3fb1d3e2 399 /*! Updates the device SPI interface settings. */
adisuciu 0:f32d3fb1d3e2 400 void UpdateDevSpiSettings();
adisuciu 0:f32d3fb1d3e2 401
adisuciu 0:f32d3fb1d3e2 402 /*! Initializes the AD7124. */
adisuciu 0:f32d3fb1d3e2 403 int32_t Setup();
adisuciu 0:f32d3fb1d3e2 404
adisuciu 0:f32d3fb1d3e2 405 uint8_t SPI_Read(uint8_t *data, uint8_t bytes_number);
adisuciu 0:f32d3fb1d3e2 406 uint8_t SPI_Write(uint8_t *data, uint8_t bytes_number);
adisuciu 0:f32d3fb1d3e2 407
adisuciu 0:f32d3fb1d3e2 408 DigitalIn miso;///< DigitalIn must be initialized before SPI to prevent pin MUX overwrite
adisuciu 0:f32d3fb1d3e2 409 SPI ad7124; ///< SPI instance of the AD7790
adisuciu 0:f32d3fb1d3e2 410 DigitalOut cs; ///< DigitalOut instance for the chipselect of the AD7790
adisuciu 0:f32d3fb1d3e2 411
adisuciu 0:f32d3fb1d3e2 412 private:
adisuciu 0:f32d3fb1d3e2 413
adisuciu 0:f32d3fb1d3e2 414
adisuciu 0:f32d3fb1d3e2 415 ad7124_st_reg *regs; // reg map 38 bytes ?
adisuciu 0:f32d3fb1d3e2 416 uint8_t useCRC; // boolean ?
adisuciu 0:f32d3fb1d3e2 417 int check_ready; // ?
adisuciu 0:f32d3fb1d3e2 418 int spi_rdy_poll_cnt; // timer ?
adisuciu 0:f32d3fb1d3e2 419
adisuciu 0:f32d3fb1d3e2 420 const static uint8_t _SPI_MODE = 0x03;
adisuciu 0:f32d3fb1d3e2 421 const static uint8_t _RESET = 0xFF;
adisuciu 0:f32d3fb1d3e2 422 const static uint8_t _DUMMY_BYTE = 0xFF;
adisuciu 0:f32d3fb1d3e2 423 const static uint16_t _READ_FLAG = 0x4000;
adisuciu 0:f32d3fb1d3e2 424 const static uint8_t _DELAY_TIMING = 0x02;
adisuciu 0:f32d3fb1d3e2 425
adisuciu 0:f32d3fb1d3e2 426 #define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */
adisuciu 0:f32d3fb1d3e2 427 #define AD7124_DISABLE_CRC 0
adisuciu 0:f32d3fb1d3e2 428 #define AD7124_USE_CRC 1
adisuciu 0:f32d3fb1d3e2 429 #define AD7124_READ_DATA 2
adisuciu 0:f32d3fb1d3e2 430
adisuciu 0:f32d3fb1d3e2 431 #define INVALID_VAL -1 /* Invalid argument */
adisuciu 0:f32d3fb1d3e2 432 #define COMM_ERR -2 /* Communication error on receive */
adisuciu 0:f32d3fb1d3e2 433 #define TIMEOUT -3 /* A timeout has occured */
adisuciu 0:f32d3fb1d3e2 434
adisuciu 0:f32d3fb1d3e2 435 };
adisuciu 1:4a4194a5a8ed 436
adisuciu 1:4a4194a5a8ed 437
adisuciu 0:f32d3fb1d3e2 438 #endif
adisuciu 0:f32d3fb1d3e2 439
adisuciu 0:f32d3fb1d3e2 440