Akafugu / BurstSPI

BurstSPI fork

Fork of BurstSPI by Erik -

BurstSPI_LPC_X.cpp@14:c99022511536, 2015-04-03 (annotated)

Committer:
Backstrom
Date:
Fri Apr 03 06:14:57 2015 +0000
Revision:
14:c99022511536
Parent:
9:b69faea5252c 
As we set receive ignore flag we don't need any code in clearRX.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 9:b69faea5252c 1 #if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24) || defined(TARGET_LPC13XX)
Sissors 9:b69faea5252c 2 #include "BurstSPI.h"
Sissors 9:b69faea5252c 3
Sissors 9:b69faea5252c 4 void BurstSPI::fastWrite(int data) {
Sissors 9:b69faea5252c 5 //Wait until FIFO has space
Sissors 9:b69faea5252c 6 while(((_spi.spi->SR) & 0x02) == 0);
Sissors 9:b69faea5252c 7
Sissors 9:b69faea5252c 8 //transmit data
Sissors 9:b69faea5252c 9 _spi.spi->DR = data;
Sissors 9:b69faea5252c 10 }
Sissors 9:b69faea5252c 11
Sissors 9:b69faea5252c 12 void BurstSPI::clearRX( void ) {
Sissors 9:b69faea5252c 13 //Do it while either data in RX buffer, or while it is busy
Sissors 9:b69faea5252c 14 while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) {
Sissors 9:b69faea5252c 15 //Wait until data in RX buffer
Sissors 9:b69faea5252c 16 while(((_spi.spi->SR) & (1<<2)) == 0);
Sissors 9:b69faea5252c 17 int dummy = _spi.spi->DR;
Sissors 9:b69faea5252c 18 }
Sissors 9:b69faea5252c 19 }
Sissors 9:b69faea5252c 20 #endif