AKM Development Platform
Driver for the AKM AK9752 IR sensor device.
Library for the AK9752 Ultra-Small IR Sensor with I2C Interface. Includes integrated temperature sensor (0 - 50C) and 16-bit ADC.
AK9752_reg.h@11:e4a64ed3ed58, 2017-03-17 (annotated)
- Committer:
- masahikofukasawa
- Date:
- Fri Mar 17 23:29:48 2017 +0000
- Revision:
- 11:e4a64ed3ed58
- Parent:
- 10:1cb542a62421
Modified for multi sensor demo.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| masahikofukasawa | 0:51fa46d39a3e | 1 | #ifndef __AK9752_REG_H__ |
| masahikofukasawa | 0:51fa46d39a3e | 2 | #define __AK9752_REG_H__ |
| masahikofukasawa | 0:51fa46d39a3e | 3 | |
| tkstreet | 5:a979c36482fc | 4 | /** |
| tkstreet | 5:a979c36482fc | 5 | * Register Addresses for AK9752 |
| tkstreet | 5:a979c36482fc | 6 | */ |
| tkstreet | 5:a979c36482fc | 7 | #define AK9752_REG_ADDR_WIA1 0x00 // Manufacturer ID |
| tkstreet | 5:a979c36482fc | 8 | #define AK9752_REG_ADDR_WIA2 0x01 // Product ID |
| tkstreet | 5:a979c36482fc | 9 | #define AK9752_REG_ADDR_INFO1 0x02 // AKM Internal Info |
| tkstreet | 5:a979c36482fc | 10 | #define AK9752_REG_ADDR_INFO2 0x03 // AKM Internal Info |
| tkstreet | 6:254b7e5820e7 | 11 | #define AK9752_REG_ADDR_ST1 0x04 // Status1: D0=DRDY |
| tkstreet | 5:a979c36482fc | 12 | #define AK9752_REG_ADDR_INTCAUSE 0x05 // Interrupt Cause: D4:D0=IRH,IRL,TMPH,TMPL,DR |
| tkstreet | 5:a979c36482fc | 13 | #define AK9752_REG_ADDR_IRL 0x06 // IR Data, Low Byte |
| tkstreet | 5:a979c36482fc | 14 | #define AK9752_REG_ADDR_IRH 0x07 // IR Data, High Byte |
| tkstreet | 5:a979c36482fc | 15 | #define AK9752_REG_ADDR_TMPL 0x08 // Temperature Data, Low Byte |
| tkstreet | 5:a979c36482fc | 16 | #define AK9752_REG_ADDR_TMPH 0x09 // Temperature Data, High Byte |
| tkstreet | 6:254b7e5820e7 | 17 | #define AK9752_REG_ADDR_ST2 0x0A // Status2: D0=DOR |
| tkstreet | 5:a979c36482fc | 18 | #define AK9752_REG_ADDR_THIRHL 0x0B // IR High Threshold, Low Byte |
| tkstreet | 5:a979c36482fc | 19 | #define AK9752_REG_ADDR_THIRHH 0x0C // IR High Threshold, High Byte |
| tkstreet | 5:a979c36482fc | 20 | #define AK9752_REG_ADDR_THIRLL 0x0D // IR Low Threshold, Low Byte |
| tkstreet | 5:a979c36482fc | 21 | #define AK9752_REG_ADDR_THIRLH 0x0E // IR Low Threshold, High Byte |
| tkstreet | 5:a979c36482fc | 22 | #define AK9752_REG_ADDR_THTMPHL 0x0F // Temp High Threshold, Low Byte |
| tkstreet | 5:a979c36482fc | 23 | #define AK9752_REG_ADDR_THTMPHH 0x10 // Temp High Threshold, High Byte |
| tkstreet | 5:a979c36482fc | 24 | #define AK9752_REG_ADDR_THTMPLL 0x11 // Temp Low Threshold, Low Byte |
| tkstreet | 5:a979c36482fc | 25 | #define AK9752_REG_ADDR_THTMPLH 0x12 // Temp Low Threshold, High Byte |
| tkstreet | 5:a979c36482fc | 26 | #define AK9752_REG_ADDR_INTEN 0x13 // Interrupt Enable: D4:D0=IRHI,IRLI,TMPHI,TMPLI,DRI |
| tkstreet | 5:a979c36482fc | 27 | #define AK9752_REG_ADDR_CNTL1 0x14 // Frequency Cutoff Control: D4:D0=FCTMP[2:0],FCIR[1:0] |
| tkstreet | 5:a979c36482fc | 28 | #define AK9752_REG_ADDR_CNTL2 0x15 // Operating Mode Control: D1:D0=MODE[1:0] |
| tkstreet | 5:a979c36482fc | 29 | #define AK9752_REG_ADDR_CNTL3 0x16 // Soft Reset: D0=SRST |
| masahikofukasawa | 0:51fa46d39a3e | 30 | |
| tkstreet | 5:a979c36482fc | 31 | #define AK9752_REG_VALUE_WIA1 0x48 // Manufacturer Code (AKM) |
| tkstreet | 5:a979c36482fc | 32 | #define AK9752_REG_VALUE_WIA2 0x14 // Product Code (AK9752) |
| masahikofukasawa | 0:51fa46d39a3e | 33 | |
| masahikofukasawa | 11:e4a64ed3ed58 | 34 | #define AK9752_ST1_MASK_DRDY 0x01 |
| masahikofukasawa | 11:e4a64ed3ed58 | 35 | |
| masahikofukasawa | 11:e4a64ed3ed58 | 36 | |
| masahikofukasawa | 0:51fa46d39a3e | 37 | #endif // __AK9752_REG_H__ |