File content as of revision 3:2035a4a54d3f:

#ifndef __AK9752_REG_H__
#define __AK9752_REG_H__

#define AK9752_REG_ADDR_WIA1        0x00    /* ID: AKM company code register */
#define AK9752_REG_ADDR_WIA2        0x01    /* subID: AK9752 code register */
#define AK9752_REG_ADDR_INFO1       0x02    /* AKM info register */
#define AK9752_REG_ADDR_INFO2       0x03    /* AKM info register */
#define AK9752_REG_ADDR_ST1         0x04    /* Status1: D0->DRDY */
#define AK9752_REG_ADDR_INTCAUSE    0x05    /* Cause of interrupt */
#define AK9752_REG_ADDR_IRL         0x06    /* Interrupt data low byte */
#define AK9752_REG_ADDR_IRH         0x07    /* Interrupt data high byte */
#define AK9752_REG_ADDR_TMPL        0x08    /* Temp data low byte */
#define AK9752_REG_ADDR_TMPH        0x09    /* Temp data high byte */
#define AK9752_REG_ADDR_ST2         0x0A    /* Status2: D0->DOR */
#define AK9752_REG_ADDR_THIRHL      0x0B    /* IR threshold A */
#define AK9752_REG_ADDR_THIRHH      0x0C    /* IR threshold B */
#define AK9752_REG_ADDR_THIRLL      0x0D    /* IR threshold C */
#define AK9752_REG_ADDR_THIRLH      0x0E    /* IR threshold D */
#define AK9752_REG_ADDR_THTMPHL     0x0F    /* Temp threshold A */
#define AK9752_REG_ADDR_THTMPHH     0x10    /* Temp threshold B */
#define AK9752_REG_ADDR_THTMPLL     0x11    /* Temp threshold C */
#define AK9752_REG_ADDR_THTMPLH     0x12    /* Temp threshold D */
#define AK9752_REG_ADDR_INTEN       0x13    /* IR/temp/DRDY threshold interrupt enable */
#define AK9752_REG_ADDR_CNTL1       0x14    /* Cutoff freq setting */
#define AK9752_REG_ADDR_CNTL2       0x15    /* Operating mode settin */
#define AK9752_REG_ADDR_CNTL3       0x16    /* SW reset */

#define AK9752_REG_VALUE_WIA1       0x48    /* AKM company code */
#define AK9752_REG_VALUE_WIA2       0x14    /* AK9752 code */

#endif // __AK9752_REG_H__