ADMW1001_Mbed_FW
/
EV-PRO-MW1001_Development
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Diff: inc/admw1001/ADMW1001_REGISTERS.h
- Revision:
- 59:3d395512b442
- Parent:
- 50:d84305e5e1c0
--- a/inc/admw1001/ADMW1001_REGISTERS.h Mon Mar 16 09:02:06 2020 +0000
+++ b/inc/admw1001/ADMW1001_REGISTERS.h Mon Mar 16 09:43:49 2020 +0000
@@ -1,7 +1,7 @@
/* ================================================================================
Created by :
- Created on : 2020 Jan 08, 12:45 GMT Standard Time
+ Created on : 2020 Mar 12, 16:15 GMT Standard Time
Project : ADMW1001_REGISTERS
File : ADMW1001_REGISTERS.h
@@ -29,13 +29,12 @@
#include <stdint.h>
#endif /* _LANGUAGE_C */
-#ifndef __ADI_GENERATED_DEF_HEADERS__
-#define __ADI_GENERATED_DEF_HEADERS__ 1
+#ifndef __ADMW_GENERATED_DEF_HEADERS__
+#define __ADMW_GENERATED_DEF_HEADERS__ 1
#endif
-#define __ADI_HAS_CORE__ 1
-#define __ADI_HAS_SPI__ 1
-#define __ADI_HAS_ADMW_TEST__ 1
+#define __ADMW_HAS_CORE__ 1
+#define __ADMW_HAS_SPI__ 1
/* ============================================================================================================================
@@ -48,16 +47,12 @@
#define MOD_SPI_MASK 0x00007FFF /* */
#define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */
#define REG_SPI_INTERFACE_CONFIG_A 0x00000000 /* SPI Interface Configuration A */
-#define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */
-#define REG_SPI_INTERFACE_CONFIG_B 0x00000001 /* SPI Interface Configuration B */
#define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */
#define REG_SPI_CHIP_TYPE 0x00000003 /* SPI Chip Type */
#define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */
#define REG_SPI_PRODUCT_ID_L 0x00000004 /* SPI Product ID Low */
#define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */
#define REG_SPI_PRODUCT_ID_H 0x00000005 /* SPI Product ID High */
-#define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */
-#define REG_SPI_CHIP_GRADE 0x00000006 /* SPI Chip Grade */
#define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */
#define REG_SPI_SCRATCH_PAD 0x0000000A /* SPI Scratch Pad */
#define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */
@@ -68,10 +63,6 @@
#define REG_SPI_VENDOR_H 0x0000000D /* SPI Vendor ID High */
#define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */
#define REG_SPI_STREAM_MODE 0x0000000E /* SPI Stream Mode */
-#define REG_SPI_TRANSFER_CONFIG_RESET 0x00000000 /* Reset Value for Transfer_Config */
-#define REG_SPI_TRANSFER_CONFIG 0x0000000F /* SPI Transfer Config */
-#define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000033 /* Reset Value for Interface_Config_C */
-#define REG_SPI_INTERFACE_CONFIG_C 0x00000010 /* SPI Interface Configuration C */
#define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */
#define REG_SPI_INTERFACE_STATUS_A 0x00000011 /* SPI Interface Status A */
@@ -93,14 +84,6 @@
#define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */
/* -------------------------------------------------------------------------------------------------------------------------
- SPI_INTERFACE_CONFIG_B Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 /* Select Streaming or Single Instruction Mode */
-#define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 /* Select Streaming or Single Instruction Mode */
-#define ENUM_SPI_INTERFACE_CONFIG_B_STREAMING_MODE 0x00000000 /* Single_Inst: Streaming mode is enabled */
-#define ENUM_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */
-
-/* -------------------------------------------------------------------------------------------------------------------------
SPI_CHIP_TYPE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */
@@ -109,24 +92,14 @@
/* -------------------------------------------------------------------------------------------------------------------------
SPI_PRODUCT_ID_L Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 /* These Bits are Fixed on Die Configured for Multiple Generics */
-#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 /* These Bits Vary on Die Configured for Multiple Generics */
-#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 /* These Bits are Fixed on Die Configured for Multiple Generics */
-#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F /* These Bits Vary on Die Configured for Multiple Generics */
+#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID 0 /* The Device Chip Type and Family */
+#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID 0x000000FF /* The Device Chip Type and Family */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_PRODUCT_ID_H Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 /* These Bits are Fixed on Die Configured for Multiple Generics */
-#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF /* These Bits are Fixed on Die Configured for Multiple Generics */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- SPI_CHIP_GRADE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_CHIP_GRADE_GRADE 4 /* Device Performance Grade */
-#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* Device Hardware Revision */
-#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 /* Device Performance Grade */
-#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* Device Hardware Revision */
+#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID 0 /* The Device Chip Type and Family */
+#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID 0x000000FF /* The Device Chip Type and Family */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_SCRATCH_PAD Pos/Masks Description
@@ -164,30 +137,6 @@
#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Set the Data Byte Count Before Looping to Start Address */
/* -------------------------------------------------------------------------------------------------------------------------
- SPI_TRANSFER_CONFIG Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Control Master to Slave Transfer */
-#define BITM_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Control Master to Slave Transfer */
-#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */
-#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- SPI_INTERFACE_CONFIG_C Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */
-#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multibyte Registers Must Be Read or Written in Full */
-#define BITP_SPI_INTERFACE_CONFIG_C_SEND_STATUS 4 /* Sends Status in 4-Wire Mode When Enabled */
-#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */
-#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */
-#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multibyte Registers Must Be Read or Written in Full */
-#define BITM_SPI_INTERFACE_CONFIG_C_SEND_STATUS 0x00000010 /* Sends Status in 4-Wire Mode When Enabled */
-#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */
-#define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */
-#define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */
-#define ENUM_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS 0x00000000 /* Strict_Register_Access: Normal mode, no access restrictions */
-#define ENUM_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS 0x00000020 /* Strict_Register_Access: Strict mode, multi-byte registers require all bytes read/written */
-
-/* -------------------------------------------------------------------------------------------------------------------------
SPI_INTERFACE_STATUS_A Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */
@@ -205,21 +154,21 @@
/* ============================================================================================================================
- ADISENSE1000 Core Registers
+ ADMW1001 Core Registers
============================================================================================================================ */
/* ============================================================================================================================
CORE
============================================================================================================================ */
-#define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */
-#define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */
+#define MOD_CORE_BASE 0x00000010 /* ADMW1001 Core Registers */
+#define MOD_CORE_MASK 0x00007FFF /* ADMW1001 Core Registers */
#define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */
#define REG_CORE_COMMAND 0x00000014 /* CORE Special Command Register */
#define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */
#define REG_CORE_MODE 0x00000016 /* CORE Operating Mode and DRDY Control */
#define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */
#define REG_CORE_POWER_CONFIG 0x00000017 /* CORE Power Configuration */
-#define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */
+#define REG_CORE_CYCLE_CONTROL_RESET 0x00002000 /* Reset Value for Cycle_Control */
#define REG_CORE_CYCLE_CONTROL 0x00000018 /* CORE Measurement Cycle */
#define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */
#define REG_CORE_FIFO_NUM_CYCLES 0x0000001A /* CORE Number of Measurement Cycles to Store in FIFO */
@@ -266,6 +215,8 @@
#define REG_CORE_AVDD_VOLTAGE 0x00000058 /* CORE AVDD Voltage */
#define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */
#define REG_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* CORE Diagnostic Control */
+#define REG_CORE_EXT_VBUFF_RESET 0x00000000 /* Reset Value for EXT_VBUFF */
+#define REG_CORE_EXT_VBUFF 0x0000005D /* CORE External Reference Buffer */
#define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */
#define REG_CORE_DATA_FIFO 0x00000060 /* CORE FIFO Buffer of Sensor Results */
#define REG_CORE_DEBUG_CODE_RESET 0x00000000 /* Reset Value for Debug_Code */
@@ -279,7 +230,7 @@
#define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */
#define REG_CORE_LUT_DATA 0x00000074 /* CORE Data to Read/Write from Addressed LUT Entry */
#define REG_CORE_REVISION_RESET 0x01000000 /* Reset Value for Revision */
-#define REG_CORE_REVISION 0x0000008A /* CORE Hardware, Firmware Revision */
+#define REG_CORE_REVISION 0x0000008C /* CORE Hardware, Firmware Revision */
#define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */
#define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */
#define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */
@@ -624,20 +575,20 @@
#define REG_CORE_CHANNEL_SKIP12 0x000003B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIPn(i) (REG_CORE_CHANNEL_SKIP0 + ((i) * 64))
#define REG_CORE_CHANNEL_SKIPn_COUNT 13
-#define REG_CORE_SENSOR_PARAMETERn_RESET 0x7FC00000 /* Reset Value for Sensor_Parameter[n] */
-#define REG_CORE_SENSOR_PARAMETER0_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER0 */
-#define REG_CORE_SENSOR_PARAMETER1_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER1 */
-#define REG_CORE_SENSOR_PARAMETER2_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER2 */
-#define REG_CORE_SENSOR_PARAMETER3_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER3 */
-#define REG_CORE_SENSOR_PARAMETER4_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER4 */
-#define REG_CORE_SENSOR_PARAMETER5_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER5 */
-#define REG_CORE_SENSOR_PARAMETER6_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER6 */
-#define REG_CORE_SENSOR_PARAMETER7_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER7 */
-#define REG_CORE_SENSOR_PARAMETER8_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER8 */
-#define REG_CORE_SENSOR_PARAMETER9_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER9 */
-#define REG_CORE_SENSOR_PARAMETER10_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER10 */
-#define REG_CORE_SENSOR_PARAMETER11_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER11 */
-#define REG_CORE_SENSOR_PARAMETER12_RESET 0x7FC00000 /* Reset Value for REG_CORE_SENSOR_PARAMETER12 */
+#define REG_CORE_SENSOR_PARAMETERn_RESET 0x3F80624E /* Reset Value for Sensor_Parameter[n] */
+#define REG_CORE_SENSOR_PARAMETER0_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER0 */
+#define REG_CORE_SENSOR_PARAMETER1_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER1 */
+#define REG_CORE_SENSOR_PARAMETER2_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER2 */
+#define REG_CORE_SENSOR_PARAMETER3_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER3 */
+#define REG_CORE_SENSOR_PARAMETER4_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER4 */
+#define REG_CORE_SENSOR_PARAMETER5_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER5 */
+#define REG_CORE_SENSOR_PARAMETER6_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER6 */
+#define REG_CORE_SENSOR_PARAMETER7_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER7 */
+#define REG_CORE_SENSOR_PARAMETER8_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER8 */
+#define REG_CORE_SENSOR_PARAMETER9_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER9 */
+#define REG_CORE_SENSOR_PARAMETER10_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER10 */
+#define REG_CORE_SENSOR_PARAMETER11_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER11 */
+#define REG_CORE_SENSOR_PARAMETER12_RESET 0x3F80624E /* Reset Value for REG_CORE_SENSOR_PARAMETER12 */
#define REG_CORE_SENSOR_PARAMETER0 0x000000B4 /* CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER1 0x000000F4 /* CORE Sensor Parameter Adjustment */
#define REG_CORE_SENSOR_PARAMETER2 0x00000134 /* CORE Sensor Parameter Adjustment */
@@ -767,6 +718,7 @@
#define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */
#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data ready per conversion */
#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data ready per cycle */
+#define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data ready per FIFO fill */
#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single cycle conversion mode. A cycle is completed every time a convert command is issued */
#define ENUM_CORE_MODE_RESERVED 0x00000001 /* Conversion_Mode: Reserved for future use */
#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
@@ -798,8 +750,8 @@
#define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00004000 /* Cycle_Time_Units: Seconds */
#define ENUM_CORE_CYCLE_CONTROL_VBIAS_DISABLE 0x00000000 /* Vbias: Vbias disabled */
#define ENUM_CORE_CYCLE_CONTROL_VBIAS_ENABLE 0x00002000 /* Vbias: Enable Vbias output for the duration of a cycle */
-#define ENUM_CORE_CYCLE_CONTROL_CLOSE_SW 0x00000000 /* GND_SW_CTRL: Ground Switch Closed */
-#define ENUM_CORE_CYCLE_CONTROL_CYCLE_SW 0x00001000 /* GND_SW_CTRL: Ground Switch Opens outside of measurement cycle to conserve power */
+#define ENUM_CORE_CYCLE_CONTROL_OPEN_SW 0x00000000 /* GND_SW_CTRL: Ground Switch Opens outside of measurement cycle to conserve power */
+#define ENUM_CORE_CYCLE_CONTROL_CLOSE_SW 0x00001000 /* GND_SW_CTRL: Ground Switch Closed */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_FIFO_NUM_CYCLES Pos/Masks Description
@@ -821,7 +773,7 @@
#define BITM_CORE_STATUS_LUT_ERROR 0x00000080 /* Indicates Error with One or More Lookup Tables */
#define BITM_CORE_STATUS_DIAG_CHECKSUM_ERROR 0x00000040 /* Indicates Error on Internal Checksum Calculations */
#define BITM_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */
-#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates Special Command Active */
+#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates Special Command Active, Active Low */
#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates New Sensor Result Available to Read */
#define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */
#define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensor Alerts Active */
@@ -860,6 +812,7 @@
/* -------------------------------------------------------------------------------------------------------------------------
CORE_ALERT_DETAIL_CH[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CORE_ALERT_DETAIL_CH_THRESHOLD_EXCEEDED 8 /* Channel Threshold Limits Exceeded */
#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 7 /* Indicates Sensor Hard Fault */
#define BITP_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 6 /* Indicates the ADC Input is Overrange */
#define BITP_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 5 /* Cold Junction Hard Fault */
@@ -868,6 +821,7 @@
#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 2 /* Indicates If the Sensor is Underrange */
#define BITP_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 1 /* Indicates If the ADC is Near Overrange */
#define BITP_CORE_ALERT_DETAIL_CH_RESULT_VALID 0 /* Set If a Result is Valid */
+#define BITM_CORE_ALERT_DETAIL_CH_THRESHOLD_EXCEEDED 0x00000100 /* Channel Threshold Limits Exceeded */
#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 0x00000080 /* Indicates Sensor Hard Fault */
#define BITM_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 0x00000040 /* Indicates the ADC Input is Overrange */
#define BITM_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 0x00000020 /* Cold Junction Hard Fault */
@@ -904,12 +858,21 @@
/* -------------------------------------------------------------------------------------------------------------------------
CORE_DIAGNOSTICS_CONTROL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 1 /* Diagnostics Sensor Detect Frequency */
+#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 1 /* Diagnostics Open Sensor Detect Frequency */
#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0 /* Diagnostics Measure Enable */
-#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x000000FE /* Diagnostics Sensor Detect Frequency */
+#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x000000FE /* Diagnostics Open Sensor Detect Frequency */
#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000001 /* Diagnostics Measure Enable */
/* -------------------------------------------------------------------------------------------------------------------------
+ CORE_EXT_VBUFF Pos/Masks Description
+ ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CORE_EXT_VBUFF_EXT_VBUFF 0 /* This field is used to configure the reference buffers */
+#define BITM_CORE_EXT_VBUFF_EXT_VBUFF 0x00000003 /* This field is used to configure the reference buffers */
+#define ENUM_CORE_EXT_VBUFF_BOTH_INACTIVE_MODE 0x00000000 /* EXT_VBUFF: Both Reference Buffers Disabled */
+#define ENUM_CORE_EXT_VBUFF_BOTH_ACTIVE_MODE 0x00000001 /* EXT_VBUFF: Both Reference Buffers Enabled */
+#define ENUM_CORE_EXT_VBUFF_ONLY_VPOS_MODE 0x00000002 /* EXT_VBUFF: VREF+ Enabled Only */
+
+/* -------------------------------------------------------------------------------------------------------------------------
CORE_DATA_FIFO Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* FIFO Buffer of Sensor Results */
@@ -979,18 +942,57 @@
#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type sensor */
#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */
#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_E 0x00000003 /* Sensor_Type: Thermocouple E-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_N 0x00000004 /* Sensor_Type: Thermocouple N-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_R 0x00000005 /* Sensor_Type: Thermocouple R-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_S 0x00000006 /* Sensor_Type: Thermocouple S-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_B 0x00000007 /* Sensor_Type: Thermocouple B-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_CUSTOM 0x00000008 /* Sensor_Type: Thermocouple CUSTOM-Type Sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT100 0x00000020 /* Sensor_Type: RTD 2 wire PT100 sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000 0x00000021 /* Sensor_Type: RTD 2 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT10 0x00000022 /* Sensor_Type: RTD 2 wire PT10 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT50 0x00000023 /* Sensor_Type: RTD 2 wire PT50 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT200 0x00000024 /* Sensor_Type: RTD 2 wire PT200 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT500 0x00000025 /* Sensor_Type: RTD 2 wire PT500 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000_0P00375 0x00000026 /* Sensor_Type: RTD 2 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_NI120 0x00000027 /* Sensor_Type: RTD 2 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_CUSTOM 0x00000028 /* Sensor_Type: RTD 2 wire Custom sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT100 0x00000040 /* Sensor_Type: RTD 3 wire PT100 sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000 0x00000041 /* Sensor_Type: RTD 3 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT10 0x00000042 /* Sensor_Type: RTD 3 wire PT10 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT50 0x00000043 /* Sensor_Type: RTD 3 wire PT50 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT200 0x00000044 /* Sensor_Type: RTD 3 wire PT200 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT500 0x00000045 /* Sensor_Type: RTD 3 wire PT500 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000_0P00375 0x00000046 /* Sensor_Type: RTD 3 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_NI120 0x00000047 /* Sensor_Type: RTD 3 wire NI120 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_CUSTOM 0x00000048 /* Sensor_Type: RTD 3 wire Custom sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT100 0x00000060 /* Sensor_Type: RTD 4 wire PT100 sensor */
#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000 0x00000061 /* Sensor_Type: RTD 4 wire PT1000 sensor */
-#define ENUM_CORE_SENSOR_TYPE_BRIDGE_4W 0x000000A9 /* Sensor_Type: Bridge 4 wire sensor */
-#define ENUM_CORE_SENSOR_TYPE_VOLTAGE 0x00000200 /* Sensor_Type: Voltage Input */
-#define ENUM_CORE_SENSOR_TYPE_CUSTOM1 0x00000400 /* Sensor_Type: Custom1 */
-#define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY_B 0x00000841 /* Sensor_Type: I2C humidity sensor B */
-#define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_1 0x00000FE0 /* Sensor_Type: RESERVED. NOT TO BE USED */
-#define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_2 0x00000FFF /* Sensor_Type: RESERVED. NOT TO BE USED */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT10 0x00000062 /* Sensor_Type: RTD 4 wire PT10 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT50 0x00000063 /* Sensor_Type: RTD 4 wire PT50 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT200 0x00000064 /* Sensor_Type: RTD 4 wire PT200 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT500 0x00000065 /* Sensor_Type: RTD 4 wire PT500 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000_0P00375 0x00000066 /* Sensor_Type: RTD 4 wire PT1000 0.00375 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_NI120 0x00000067 /* Sensor_Type: RTD 4 wire NI120 */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_CUSTOM 0x00000068 /* Sensor_Type: RTD 4 wire Custom sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44004_44033_2P252K_AT_25C 0x00000080 /* Sensor_Type: THERMISTOR_44004_44033_2P252K_AT_25C */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44005_44030_3K_AT_25C 0x00000081 /* Sensor_Type: THERMISTOR_44005_44030_3K_AT_25C */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44007_44034_5K_AT_25C 0x00000082 /* Sensor_Type: THERMISTOR_44007_44034_5K_AT_25C */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44006_44031_10K_AT_25C 0x00000083 /* Sensor_Type: THERMISTOR_44006_44031_10K_AT_25C */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_44008_44032_30K_AT_25C 0x00000084 /* Sensor_Type: THERMISTOR_44008_44032_30K_AT_25C */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_YSI_400 0x00000085 /* Sensor_Type: THERMISTOR_YSI_400 */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_SPECTRUM_1003K_1K 0x00000086 /* Sensor_Type: THERMISTOR_SPECTRUM_1003K_1K */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_STEINHART_HART 0x00000087 /* Sensor_Type: THERMISTOR_CUSTOM_STEINHART_HART */
+#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_TABLE 0x00000088 /* Sensor_Type: THERMISTOR_CUSTOM_TABLE */
+#define ENUM_CORE_SENSOR_TYPE_BRIDGE_4WIRE 0x000000A8 /* Sensor_Type: Bridge 4 wire sensor */
+#define ENUM_CORE_SENSOR_TYPE_BRIDGE_6WIRE 0x000000C8 /* Sensor_Type: Bridge 6 wire sensor */
+#define ENUM_CORE_SENSOR_TYPE_DIODE 0x000000E0 /* Sensor_Type: DIODE Temperature Sensor */
+#define ENUM_CORE_SENSOR_TYPE_SINGLE_ENDED_ABSOLUTE 0x00000240 /* Sensor_Type: Voltage Input Single Ended on V+ */
+#define ENUM_CORE_SENSOR_TYPE_DIFFERENTIAL_ABSOLUTE 0x00000280 /* Sensor_Type: Voltage Input Differential Ended on V+ and V- */
+#define ENUM_CORE_SENSOR_TYPE_SINGLE_ENDED_RATIO 0x00000290 /* Sensor_Type: Ratiometeric Output, Voltage_IN/Voltage_Reference */
+#define ENUM_CORE_SENSOR_TYPE_DIFFERENTIAL_RATIO 0x000002A0 /* Sensor_Type: Ratiometeric Output, Voltage_IN/Voltage_Reference */
+#define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY 0x00000840 /* Sensor_Type: I2C humidity sensor B */
+#define ENUM_CORE_SENSOR_TYPE_I2C_TEMPERATURE_ADT742X 0x000008AA /* Sensor_Type: ADI Precision I2C Digital Temperature Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SENSOR_DETAILS[n] Pos/Masks Description
@@ -1027,9 +1029,8 @@
#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00100000 /* Reference_Select: External voltage reference applied to VERF+ and VREF- */
#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00300000 /* Reference_Select: AVDD supply internally used as reference */
#define ENUM_CORE_SENSOR_DETAILS_LUT_DEFAULT 0x00000000 /* LUT_Select: Default lookup table for selected sensor type */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_UNITY 0x00008000 /* LUT_Select: Unity lookup table. 1:1 mapping from input to output */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00010000 /* LUT_Select: User defined custom lookup table. */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_RESERVED 0x00018000 /* LUT_Select: Reserved */
+#define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00008000 /* LUT_Select: User defined custom lookup table. */
+#define ENUM_CORE_SENSOR_DETAILS_LUT_RESERVED 0x00010000 /* LUT_Select: Reserved */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED 0x00000000 /* Measurement_Units: Not Specified */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_RESERVED 0x00000001 /* Measurement_Units: Reserved */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000002 /* Measurement_Units: Degrees C */
@@ -1064,14 +1065,8 @@
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SETTLING_TIME[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 14 /* Units for Settling Time */
-#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */
-#define BITM_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 0x0000C000 /* Units for Settling Time */
-#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x00003FFF /* Settling Time to Allow When Switching to Channel */
-#define ENUM_CORE_SETTLING_TIME_MILLISECONDS 0x00000000 /* Settling_Time_Units: Micro-seconds */
-#define ENUM_CORE_SETTLING_TIME_SECONDS 0x00004000 /* Settling_Time_Units: Milli-seconds */
-#define ENUM_CORE_SETTLING_TIME_RESERVED 0x00008000 /* Settling_Time_Units: Seconds */
-#define ENUM_CORE_SETTLING_TIME_UNDEFINED 0x0000C000 /* Settling_Time_Units: Undefined */
+#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Additional Settling Time in Milliseconds. Max 255ms */
+#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x000000FF /* Additional Settling Time in Milliseconds. Max 255ms */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_MEASUREMENT_SETUP[n] Pos/Masks Description
@@ -1083,7 +1078,7 @@
#define BITP_CORE_MEASUREMENT_SETUP_ADC_SF 0 /* ADC Digital Filter Speed */
#define BITM_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 0x00008000 /* Disable Buffers */
#define BITM_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 0x00001000 /* ADC Digital Filter Type */
-#define BITM_CORE_MEASUREMENT_SETUP_CHOP_MODE 0x00000C00 /* Enabled and Disable Chop Mode */
+#define BITM_CORE_MEASUREMENT_SETUP_CHOP_MODE 0x00000400 /* Enabled and Disable Chop Mode */
#define BITM_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 0x00000100 /* Enable Notch 2 Filter Mode */
#define BITM_CORE_MEASUREMENT_SETUP_ADC_SF 0x0000007F /* ADC Digital Filter Speed */
#define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED 0x00000000 /* Buffer_Bypass: Input buffers enabled */
@@ -1091,9 +1086,7 @@
#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC4 0x00000000 /* ADC_Filter_Type: Enabled SINC4 filter */
#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC3 0x00001000 /* ADC_Filter_Type: Enabled SINC3 filter */
#define ENUM_CORE_MEASUREMENT_SETUP_DISABLE_CHOP 0x00000000 /* Chop_Mode: ADC front end chopping disabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_HW_CHOP 0x00000400 /* Chop_Mode: Hardware chopping enabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_SW_CHOP 0x00000800 /* Chop_Mode: SW chop enabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_HW_SW_CHOP 0x00000C00 /* Chop_Mode: Hardware and software chop enabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_CHOP 0x00000400 /* Chop_Mode: ADC front end chopping enabled */
#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_DIS 0x00000000 /* NOTCH_EN_2: Disable notch filter */
#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_EN 0x00000100 /* NOTCH_EN_2: Enable notch 2 filter option. */
@@ -1110,12 +1103,6 @@
#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */
/* -------------------------------------------------------------------------------------------------------------------------
- CORE_IDEALITY_FACTOR[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_IDEALITY_FACTOR_IDEALITY_FACTOR 0 /* Diode Ideality Factor, Default 1.003. */
-#define BITM_CORE_IDEALITY_FACTOR_IDEALITY_FACTOR 0xFFFFFFFF /* Diode Ideality Factor, Default 1.003. */
-
-/* -------------------------------------------------------------------------------------------------------------------------
CORE_SENSOR_OFFSET[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */
@@ -1171,11 +1158,9 @@
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 10 /* Configuration for Sensor SPI Protocol */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 5 /* Controls SCLK Frequency for I2C Sensors */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 1 /* Controls Clock Frequency for SPI Sensors */
-#define BITP_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0 /* Enable Digital Sensor Communications Register Parameters */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 0x00000C00 /* Configuration for Sensor SPI Protocol */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 0x00000060 /* Controls SCLK Frequency for I2C Sensors */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 0x0000001E /* Controls Clock Frequency for SPI Sensors */
-#define BITM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0x00000001 /* Enable Digital Sensor Communications Register Parameters */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock polarity = 0 Clock phase = 0 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock polarity = 0 Clock phase = 1 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock polarity = 1 Clock phase = 0 */
@@ -1200,8 +1185,6 @@
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ 0x0000001A /* SPI_Clock: 977Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ 0x0000001C /* SPI_Clock: 488Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ 0x0000001E /* SPI_Clock: 244Hz */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 0x00000000 /* Digital_Sensor_Comms_En: Default parameters used for digital sensor communications */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 0x00000001 /* Digital_Sensor_Comms_En: User supplied parameters used for digital sensor communications */
/* SPI Parameters */